JPH0170362U - - Google Patents
Info
- Publication number
- JPH0170362U JPH0170362U JP1987164995U JP16499587U JPH0170362U JP H0170362 U JPH0170362 U JP H0170362U JP 1987164995 U JP1987164995 U JP 1987164995U JP 16499587 U JP16499587 U JP 16499587U JP H0170362 U JPH0170362 U JP H0170362U
- Authority
- JP
- Japan
- Prior art keywords
- solid
- imaging device
- state imaging
- substrates
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003384 imaging method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims 4
- 230000002093 peripheral effect Effects 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
第１図Ａ及びＢは、この考案による固体撮像装
置の一実施例を示す平面図及び断面図、第２図は
、前記固体撮像装置の他の実施例を示す部分平面
図、第３図は、前記固体撮像装置の更に他の実施
例を示す断面図、第４図は、前記固体撮像装置の
更に他の実施例を示す断面図、第５図Ａ及びＢは
、従来の固体撮像装置の一例を示す平面図及び断
面図をそれぞれに示す。
１，１０……基板、２……撮像ＩＣ、１１……
基体、１４……ＩＣ、１５……ピン・グリツド・
アレイ。
1A and 1B are a plan view and a sectional view showing one embodiment of the solid-state imaging device according to this invention, FIG. 2 is a partial plan view showing another embodiment of the solid-state imaging device, and FIG. , FIG. 4 is a sectional view showing still another embodiment of the solid-state imaging device, and FIGS. 5A and 5B are cross-sectional views showing still another embodiment of the solid-state imaging device. A plan view and a sectional view showing an example are shown respectively. 1, 10... Board, 2... Imaging IC, 11...
Base, 14...IC, 15...Pin grid
array.
Claims (1)
基板と、周辺回路を構成する機能素子を実装する
基板とを接合してなる基体と、前記基板間を電気
的に接続するピン・グリツド・アレイから成る接
続手段とを備えたことを特徴とする固体撮像装置
。 ２ 前記周辺回路を構成する機能素子を実装する
基板を複数接合して成る基体を設けたことを特徴
とする実用新案登録請求の範囲第１項記載の固体
撮像装置。[Claims for Utility Model Registration] 1. A base body formed by bonding a substrate on which an imaging IC with integrated photoelectric conversion elements is mounted and a substrate on which functional elements constituting a peripheral circuit are mounted, and an electrical connection between said substrates. 1. A solid-state imaging device, comprising: connection means comprising a pin grid array for connection. 2. The solid-state imaging device according to claim 1, which has been registered as a utility model, and includes a base body formed by bonding a plurality of substrates on which functional elements constituting the peripheral circuit are mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987164995U JPH0170362U (en) | 1987-10-28 | 1987-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987164995U JPH0170362U (en) | 1987-10-28 | 1987-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0170362U true JPH0170362U (en) | 1989-05-10 |
Family
ID=31451079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987164995U Pending JPH0170362U (en) | 1987-10-28 | 1987-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0170362U (en) |
-
1987
- 1987-10-28 JP JP1987164995U patent/JPH0170362U/ja active Pending