JPH0170345U - - Google Patents

Info

Publication number
JPH0170345U
JPH0170345U JP16470887U JP16470887U JPH0170345U JP H0170345 U JPH0170345 U JP H0170345U JP 16470887 U JP16470887 U JP 16470887U JP 16470887 U JP16470887 U JP 16470887U JP H0170345 U JPH0170345 U JP H0170345U
Authority
JP
Japan
Prior art keywords
chip carrier
leadless chip
integrated circuit
semiconductor integrated
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16470887U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16470887U priority Critical patent/JPH0170345U/ja
Publication of JPH0170345U publication Critical patent/JPH0170345U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案のリードレスチツプキヤリアの
斜視図、第2図は第1図のリードレスチツプキヤ
リアを実装した基板の縦断面図、第3図は従来の
リードレスチツプキヤリアの斜視図である。 1,14……リードレスチツプキヤリア、2…
…凸部、3,17……底部、4,16……半導体
集積回路素子接続電極、5,6,15……外部接
続用電極、7……フタ、8,9……半田、10…
…基板、13……回路配線パターン、11……半
導体集積回路素子、12……ワイヤー。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体集積回路素子を収容するリードレスチツ
    プキヤリアにおいて、底部に複数の外部接続用電
    極を周囲に配置した凸部を有することを特徴とす
    るリードレスチツプキヤリア。
JP16470887U 1987-10-27 1987-10-27 Pending JPH0170345U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16470887U JPH0170345U (ja) 1987-10-27 1987-10-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16470887U JPH0170345U (ja) 1987-10-27 1987-10-27

Publications (1)

Publication Number Publication Date
JPH0170345U true JPH0170345U (ja) 1989-05-10

Family

ID=31450553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16470887U Pending JPH0170345U (ja) 1987-10-27 1987-10-27

Country Status (1)

Country Link
JP (1) JPH0170345U (ja)

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