JPH0295240U - - Google Patents
Info
- Publication number
- JPH0295240U JPH0295240U JP1989004676U JP467689U JPH0295240U JP H0295240 U JPH0295240 U JP H0295240U JP 1989004676 U JP1989004676 U JP 1989004676U JP 467689 U JP467689 U JP 467689U JP H0295240 U JPH0295240 U JP H0295240U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- mounting
- circuit board
- shaped
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第１図と第２図はこの考案に係る実装構造に用
いる実装用チツプの異なつた外形を示す斜視図、
第３図は第１図のチツプに電極を形成した斜視図
、第４図と第５図は実装の工程を示す縦断面図、
第６図は従来の実装構造を示す縦断面図である。 １…回路基板、２…チツプ状ＩＣ、１１…実装
用チツプ、１２…収納孔、１３…上面電極、１４
…側面電極、１６…ワイヤ、１７…樹脂。
いる実装用チツプの異なつた外形を示す斜視図、
第３図は第１図のチツプに電極を形成した斜視図
、第４図と第５図は実装の工程を示す縦断面図、
第６図は従来の実装構造を示す縦断面図である。 １…回路基板、２…チツプ状ＩＣ、１１…実装
用チツプ、１２…収納孔、１３…上面電極、１４
…側面電極、１６…ワイヤ、１７…樹脂。
Claims (1)
- 回路基板上に固定した実装用チツプにチツプ状
ＩＣの収納孔を上下方向に貫通するように設け、
この実装用チツプの上面に形成した電極と回路基
板の配線パターンを電気的に接続し、収納孔内に
収納したチツプ状ＩＣと前記電極をワイヤボンデ
イングによつて接続し、チツプ状ＩＣの上面から
実装用チツプの上面を樹脂で封止したＩＣの実装
構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989004676U JPH0295240U (ja) | 1989-01-18 | 1989-01-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989004676U JPH0295240U (ja) | 1989-01-18 | 1989-01-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295240U true JPH0295240U (ja) | 1990-07-30 |
Family
ID=31207399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989004676U Pending JPH0295240U (ja) | 1989-01-18 | 1989-01-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295240U (ja) |
-
1989
- 1989-01-18 JP JP1989004676U patent/JPH0295240U/ja active Pending