JPH0158860B2 - - Google Patents

Info

Publication number
JPH0158860B2
JPH0158860B2 JP58153511A JP15351183A JPH0158860B2 JP H0158860 B2 JPH0158860 B2 JP H0158860B2 JP 58153511 A JP58153511 A JP 58153511A JP 15351183 A JP15351183 A JP 15351183A JP H0158860 B2 JPH0158860 B2 JP H0158860B2
Authority
JP
Japan
Prior art keywords
layer
copper foil
plating layer
thickness
nickel plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58153511A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6045089A (ja
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58153511A priority Critical patent/JPS6045089A/ja
Publication of JPS6045089A publication Critical patent/JPS6045089A/ja
Publication of JPH0158860B2 publication Critical patent/JPH0158860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP58153511A 1983-08-22 1983-08-22 回路配線用基板 Granted JPS6045089A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58153511A JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58153511A JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Publications (2)

Publication Number Publication Date
JPS6045089A JPS6045089A (ja) 1985-03-11
JPH0158860B2 true JPH0158860B2 (OSRAM) 1989-12-13

Family

ID=15564137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58153511A Granted JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Country Status (1)

Country Link
JP (1) JPS6045089A (OSRAM)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2518655B2 (ja) * 1987-08-25 1996-07-24 株式会社 ムトウ 物品の仕分方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150292A (en) * 1979-05-11 1980-11-22 Fujitsu Ltd Method of fabricating printed circuit board
JPS5852836A (ja) * 1981-09-24 1983-03-29 Fuji Electric Co Ltd 複合集積回路
JPS5815905A (ja) * 1982-06-15 1983-01-29 Ichimaru Fuarukosu Kk 可溶化シルクペプチド含有皮膚化粧料

Also Published As

Publication number Publication date
JPS6045089A (ja) 1985-03-11

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