JPH0157819B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When a binary series consisting of logic 1 and logic 0 is input, only the output corresponding to the leftmost or rightmost logic 1 position with a high priority is a logic 1. All outputs to the left of the output corresponding to the high-priority logic 1 position are forced to logic 1, and all outputs to the right of it are forced to logic 1. The present invention relates to a configuration of a priority circuit for setting zero, and particularly to a configuration of a priority circuit having an array structure consisting of a plurality of row lines and a plurality of column lines.

Generally speaking, priority circuits are as follows.
In Figure 1, I _i is the input line of priority circuit 1, and O _i is I _i
The output line corresponds to Now, the priority of the data of I _i is set as the top i (i = 1, 2, ...,
n). Then, when thinking in terms of positive logic, if I _n is the line with the highest priority among the inputs I _i whose data is “1”, then I _i = “0” i<m “1” i= For input data m “0” or “1” i>m, Q _i =“0” i≠m “1” I=m is output. (See Figure 1b.) Conventionally, this type of priority circuit has been configured such that when one or more input conductors to which priorities are assigned are simultaneously activated, the input conductor with the highest priority is activated. The priority encoder circuit for providing a binary address was composed of random logic as shown in FIG. FIG. 2a is a truth table for the 8-bit priority encoder 2, in which input conductors D ₀ -D ₇ are assigned higher priorities in descending order of numbers.
When Ein is 1, it provides the binary addresses Q ₂ , Q ₁ , Q ₀ of the highest priority activated conductors. G _s
When Ein=1, if at least one of the input conductors is activated, an output will be produced. On the other hand, the output Eout is D ₀ ~ _{D 7} when Ein = 1
1 when none of the input conductors of
Generates output. The random logic that implements such an 8-bit priority encoder is shown in FIG. 2b.

However, this type of conventional priority circuit 2 does not have a memory structure, so when the number of inputs becomes very large, the chip area becomes large and the delay time becomes very large, making it unsuitable for large-scale integration (LSI). Nakatsuta.

In the present invention, the circuit structure is a memory structure consisting of a plurality of row lines and column lines, and a logic 1 of a column line with a high priority among the column lines or a logic 0 obtained by inverting the logic 1 with an inverter is applied to the row line. to force other row lines to a logical 0 by transmitting to a given row line
Alternatively, by utilizing the logic 1, a priority circuit with a small chip area and a small delay time is provided.

In a memory structure consisting of a plurality of row lines and a plurality of column lines, by transmitting the logic state of a certain column line among the column lines or the inverted logic of the logic state to a predetermined row line of the row lines. Then, the other column lines are forcibly brought into a specific logic state using logic circuits present at each intersection of the row line and the column line.

Next, an embodiment of the priority circuit of the present invention will be described with reference to the drawings.

In realizing a priority circuit, even if the number of inputs n is very large, the circuit area must be made as small as possible, and the delay must also be shortened. A circuit that satisfies these points has been devised, and its basic circuit is the one shown in FIG. Think logically here.

In Figure 3, the horizontal line constitutes an OR array that transmits the OR result to the row line by inputting the data of the column line that intersects at the ● mark, and the result of AND for the column line by inputting the data of the row line that intersects at the circle. Indicates that the The operating principle is that data with a given priority is forcibly set to "0" by the presence of data whose value is "1" among all data with a higher priority. It is a look-ahead method, and the delay is not affected by the number of inputs or the input state. When the area S of the circuit 3 in FIG. 3 is expressed based on the number of row lines and column lines, in the case of n inputs, it becomes S=n×(n-1) . . . (1). Since n is required to be quite large for practical purposes, circuit 3 in FIG. 3 requires too large an area as an additional circuit and is difficult to implement.

Therefore, we devised a circuit with the same function but a small area by dividing circuit 3 in Figure 3, considering a hierarchical structure of small-scale identical circuits, and increasing the density.

FIG. 4 shows a priority circuit 4 in which four inputs of the circuit shown in FIG. 3 are connected in a hierarchical manner. In the second stage
If you note that the AND and OR functions are controlled simultaneously for four column lines as one unit, you will understand that the functions are similar to the first stage.

In general, let the number of inputs of the basic circuit for division be P and the number of hierarchical levels be m (in Figure 4, P = 4, m = 2
) The following can be said about the priority circuit of the hierarchical structure.

When configuring a priority circuit where the number of inputs is N, let M be the maximum number of lines that intersect with the same column line, then P ^m ≧N ……(2) M=m(P-1) ……(3 ) holds true. Since it is most efficient when the sign holds true in equation (2), P ^m =N . The area S _p is expressed as S _p = M × N, and since N is a constant, P that minimizes M
is found from (2)′ and (3). From (2)'(3), M=[(P-1)/lnP]lnN...(4) dM/dP=[lnP-(P-1)/P]/(lnP) ² =0...( 5) The condition is lnP=(P-1)/P...(6). Equation (6) is satisfied when P=1, but this does not satisfy Equation (2), and from the condition that P is an integer, P that minimizes M is P=2...(7) M= (1/ln2)lnN ...(8). For example, if the number of inputs is N = 2 ¹⁰ = 1024 (8)
Therefore, M=10, and only 10 lines are required.
Compared to the circuit shown in FIG. 3, which required N-1=1023 wires, this is a significant area savings. FIG. 5 shows a priority circuit 5 formed by adding an additional circuit for expansion to the optimized priority circuit of P=2.

In FIG. 5, as in FIG. 3, the row lines form an OR array by inputting the data of the column lines that intersect at the ● marks, and the AND array is formed by inputting the horizontal lines that intersect the column lines at the ○ marks. Inputs I ₁ to I _2o are each added as an input to an AND array. Horizontal lines a and b in Figure 5 are expansion circuits for multi-stage connection of this priority circuit, and the input EI can be easily connected to the output EO of the upper priority circuit or to a general carrier head generator. Can be expanded.

As a concrete circuit, it can be easily realized using MOS.

Figure 6 shows circuit example 6 where both row and column lines are NOR.
This shows the case where the inputs I ₁ to _{I 2o} are set to negative logic.

If the priority circuit of the present invention is combined with an associative memory, by devising an address decoder, adding a counter, etc., it is possible to create an associative function, that is, a system that performs designation of a valid area for a key matching operation and writing operations in a stacked manner.

FIG. 7 shows a block diagram of this system 8. The decoder 10 is special here. In the conventional decoder, the following relationship existed between the inputs _I0 to _Io-1 and the outputs _O0 to _O2k-1 .

O _i = “1” “0” i = A i≠A (9) However, A = I _o-1 2 ^n-1 + I _o-2 2 ^n-2 +... This can be transformed into the following relationship. Change to

O _i = “1” “0” i≦A i>A (10) The output 101 of the decoder 10 and the output 201 of the key section 20, that is, the matching information output, are ANDed by 30 and input to the priority circuit 40 in FIG. Become. The output 401 of the priority circuit is comprised of RAM. value part 5
It is connected to the read/write address line of 0 and the write address line 202 of the key section. First, the write operation to the key part and value part will be explained. The write address is common to both the key part and the value part, and is specified in address order by the value of the counter register 60. The address data is the Tecoder 1 mentioned above.
0, AND circuit 30, priority circuit 40, key
The address lines of the section and value section are determined.

In addition, in the write mode, the output of the key part is all “1”
so that it is. Therefore, the decoder output is controlled by the priority circuit 40 as shown in equation (9), and only the word line of the RAM designated by the counter register 60 becomes "1".

Next, we will discuss the search mode. In this case, the counter register 60 is used as a pointer that points to the boundary of the valid area for matching operations in the key section. The input data is compared with the stored contents in the key section, and matching information is output. Note that the mask register 70 is used to make any bit of the input data a don't care for matching operations. The output 201 of the key section is ANDed with the decoder output 101 and input to the priority circuit 40. The area where the output 101 of the decoder 10 is "1" is a valid area.
Then, the priority circuit 40 selects the one with the highest priority and outputs the corresponding data in the value section.

In this way, writing is performed in a stacked manner in the order of addresses, and the written area becomes the effective area for matching operations. Furthermore, by setting an address in the counter register 60, it is possible to write to any location and specify any valid area. In addition,
The AND circuit 30 can be included in the AND array of the priority circuit 40, and the decoder can also be easily realized using an array structure.

It is quite possible that the association shown in Figure 7 will be realized with the MOSLSI1 chip in the future. Furthermore, if the capacity is disadvantageous, it is also possible to separate the value part and output it in the form of an address by passing an encoder through the priority circuit output, and use an external RAM as the value part. Furthermore, by using the expansion function of the priority circuit described above, it is possible to connect in multiple stages to form a large system.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the input/output relationship of the priority circuit, Figure 2
Figures a and b are a truth table of a priority circuit and a configuration diagram of a conventional priority circuit, respectively, Figure 3 is a priority circuit for explaining the operating principle of the present invention, and Figure 4 is for explaining the division method of the present invention. 5 is a priority circuit whose area is minimized according to the division method of the present invention, and FIG.
The figure is a circuit diagram of a priority circuit of the present invention with a minimum area realized using MOS transistors, and FIG. 7 is a system diagram of an associative stack constructed by combining the priority circuit of the present invention and an associative memory. 1... Conceptual diagram of priority circuit, 2... Conventional priority circuit, 3, 4, 5... Priority circuit showing the dividing method of the present invention, 6... Specific illustration of priority circuit omitted, 8... Associative stack , 10... decoder, 20... key section,
40...priority circuit, 50...value section.

Claims (1)

[Claims] 1. When a binary series consisting of logic 1 and logic 0 is input, only the output corresponding to the leftmost or rightmost logic 1 or 0 position, that is, the logic 1 or 0 with a high priority, is logic 1. Or, in a priority circuit that is activated to 0, for n inputs, it has an array structure consisting of n column lines and log ₂ n row lines or a number of row lines close to that, and each row line is OR (or AND) At the intersection where logic is performed, input the logic of the column line and row line and move in the row direction.
OR (or AND) logic, the column direction transmits the logic as it is, and the column line performs AND (or OR) logic.The logic of the row line and column line that intersect at the intersection is input and AND (or OR) is performed in the column direction. The logic and row direction are kept as they are, and the m-th row line is divided into 2 ^m or similar intersection sets, and an inversion circuit exists between the intersections in the center of each intersection set. The result of is used to force the leftmost or rightmost high priority logic 1 of an input line to a logic 0 (or 1) on all column lines to the right or left of it. Features a priority circuit. 2. The priority according to claim 1, which has a hierarchical structure and includes means connected to the output of a storage circuit and sequentially selecting outputs from a high priority position to a low priority output among the activated outputs of the priority circuit. circuit.