JPS63217597A - Storage device - Google Patents

Abstract

PURPOSE:To speedily read bit length data equivalent to one word straddling plural memory cell groups in which internal addresses differ by providing an internal address/control code generation circuit generating the internal addresses and control codes from external addresses. CONSTITUTION:The internal address/control code generation circuit generates the control codes with internal X and Y address data in accordance with external input address data. Internal X and Y address data are switched/detached to and from word line selection circuits 13 of submemory cell allays 11 in which corresponding internal address are different and the multiplexer control circuit 16 by the control code to supply them to control circuits 19. Thus, data of bit length equivalent to one word straddling plural arrays 11 in which internal addresses are different can be read without troubling a computer or the like and without increasing the charge.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory device in which an internal address is assigned to a group of memory cells that store at least one word of data. The present invention relates to a memory device in which data having a bit length equivalent to one word across memory cell groups can be freely read or written based on externally input address data.

[Conventional technology]

FIG. 4 shows the basic configuration of a conventional storage device.

WDC=):Ct=1. ..., M) is the word line BLci); <j='.

. . ., kN) are bit lines, and each intersection thereof has a memory cell 4 that can store at least one bit of information.
5 is connected. A word line is a line that transmits a signal that controls permission or prohibition of reading and writing data to a memory cell, and a bit line is a line that transmits read or write data from a memory cell. In addition, the data bus is a line that transmits output or write data from memory cells to output or output terminals of the storage device.
It is shared within the self-storage device. A device consisting of one word or bits is required. The word line selection circuit 40 has at least 1o
This circuit inputs gtM-bit X address data, decodes it, and outputs a selection signal for selecting one of M word lines.The word line drive circuit 41 outputs a selection signal from the word line selection circuit 40. This circuit controls the state of the word line to be switched between an active state in which data can be input/output to and from a memory cell connected to the word line and an inactive state opposite to the active state based on a selection signal generated by the word line. multiplexer 42
is a circuit that connects or disconnects memory cells arranged on active word lines from a data bus. The multiplexer control circuit 45 has at least 16 g. A circuit that inputs N-bit Y address data and outputs a signal to control the multiplexer 42 arranged for each bit line by switching its state to a connected state or a disconnected state, two pieces can be connected to the same data bus at the same time. Control is performed so that more memory cells are not connected. FIG. 4 shows that the word line of WD (5) is selected and activated based on the input X address data, and the word line of WD (5) is selected and activated based on the input Y address data. k jB indicated by a circle from among the memory cells of the memory cell array 44
memory cells are selected by multi-break f42,
Shows that it is connected to the data bus. In addition to the above circuit, the memory device includes an input/output buffer, an address buffer, a sense circuit that amplifies the memory cell output signal,
Peripheral circuits such as a reference voltage generation circuit and a read/write control circuit are mounted, but are omitted in FIG.

Next, assuming a conventional storage device consisting of one word or one bit, FIG. 3 shows the correspondence between externally designated addresses and internal addresses. Here, AI) RINC
z, y), 1LDRINcz + 1, y
ADRIN (z+2.y), . . . indicate consecutive internal addresses, and the internal addresses are assigned as one group of memory cells to store one word of data.

Now, in a conventional memory device, this internal address is directly specified from the outside, and peripheral circuits such as a word line selection circuit, a word line drive circuit, a multiplexer control circuit, and a multiplexer are operated to store one word of data in a memory cell. One group was selected and data was read or written. Therefore, due to constraints on the memory array configuration, as shown by diagonal lines in FIG. 3, it is not possible to read or write data with a bit length equivalent to one word across memory cell groups with different internal addresses from the storage device. It was impossible.

[Problem that the invention seeks to solve]

When configuring a system using conventional storage devices, the following inconveniences have occurred.

In systems with storage devices such as computer systems,
Basic operations such as concatenating two sets of data into one set of data are often required. On the other hand, a % storage device divides a series of data into word-based data and stores them. Therefore, unless a series of data can be completely divided into word units of data, an empty bit in which no data is stored occurs at the end of a word where the end of a series of data is stored. When concatenating a series of data, it is necessary to fill these empty bits with the data from the beginning of the subsequent data, and to divide the remaining data into new words and rewrite them. .

Conventionally, the above-mentioned operation has been performed by sequentially reading one word from the storage device, performing a concatenation or shift operation on the arithmetic unit to create the desired one-word data, and then reading the data into the storage device again. Therefore, when concatenating a series of data, there are problems such as the processing time is long and each time one word of rewritten data is created, it occupies the most frequently used arithmetic unit among the resources that make up the computer. there were.

[Means for solving problems]

The present invention solves the conventional problems, and in a memory device i in which internal addresses are assigned as a group of memory cells that store at least one word of data, a plurality of memory cells with different internal addresses A storage device that directly connects data with a bit length equivalent to 91 words across groups to the internal structure of the storage device, and can freely read and write data by specifying an external address without being aware of the internal address. It provides:

The present invention comprises (1) configuring a memory array in which internal addresses are assigned as groups of memory cells that store at least one word of data; (2) internal X and A data set consisting of Y address data, a first control code that defines the connection relationship between the sub data bus and the main data bus, tk is internal X and Y address data, and a memory cell arranged on a word line in a selected state. A data set consisting of a second control code that defines the connection relationship with the sub-data bus is generated from externally input address data, and the data readout function is an internal control code that is output for each sub-memory array to which the memory cell to be written belongs. Equipped with an address/control code generation circuit; (3) ■ Connection between the main data bus shared between sub-memory arrays and the data bus within the sub-memory array;
A switching/disconnecting circuit that switches or disconnects the relationship, and a switching/disconnecting control circuit that generates control code No. 1 from the control code No. 1 and outputs it to the switching/disconnecting circuit as soon as its control No. 11 is manually installed are installed for each sub-memory array. to do,
■i9 is a multiplexer having means for switching or disconnecting the connection between the memory cell arranged on the word line in the selected state and the sub-bit line directly connected to the main bit line, and its control signal as an internal Y address. Using the multiplexer control circuit generated from the second control code -
That is, all the main features.

[Effect]

The memory device of the present invention is different from the conventional data read or fold method, in which the internal address is directly specified from the outside, so that the memory cells to be read or folded are limited to one group of memory cells having the same internal address. This eliminates restrictions when writing data, and it is fully equipped with a circuit that internally generates multiple sets of related internal addresses and control codes according to external input and the next address. Data having a bit length equivalent to 91 words can be freely read or read without being aware of differences in internal addresses. Examples will be described below based on the drawings.

[Embodiment] FIG. 1 is a diagram showing an outline of the configuration of a first embodiment of the present invention. In this embodiment, P sub-memory arrays 10 are divided into m
The sub-memory array 10 of the device is composed of a memory array, an internal address/control code generation circuit 12, and a main data bus, which includes a sub-memory cell array 11,
It is composed of a word line selection circuit 15, a word line drive circuit 14, a multiplexer 15, a multiplexer control circuit 16, a sub data bus 17, a switching/disconnection circuit 18, and a switching/disconnection control circuit 19. In addition to the above circuits, the memory device includes peripheral circuits such as a sense circuit that amplifies the output signal from the memory cell, a reference voltage generation circuit, a readout or convolution control circuit, an address buffer 1, and an input/output parallel buffer. is installed, but it is omitted in Figure 1.

First, the internal address/control code generation circuit 12 generates, from externally input address data, internal X address data, internal Y address data, and a first control code that defines the connection relationship between the sub-p path and the main data bus. A circuit 6 generates a set of data and outputs it to each sub-memory array 10. Hereinafter, for convenience of explanation, the first control code in the first embodiment will be simply referred to as a control code.

The method for configuring the internal address/control code generation circuit 12 is as follows. Since this method has a large degree of freedom and is closely related to the method of assigning addresses input externally, the method of assigning addresses will be described later along with an explanation of the method of assigning addresses using an example of application to a main storage device and an example of application to the image field.

In addition, the main data bus is a line that transmits the data on the main data bus from the output to the next input terminal of the storage device, and is shared between the seven arrays. .

Next, each circuit constituting one sub-memory array 1ro will be explained below. WD (i); (4=1,...
..., M) is a word line, EL(j): (j=1...
..., kN) are rough bit lines, and one memory cell that stores at least one bit of information is connected to each intersection thereof. The word line is a line that transmits a signal that controls permission or prohibition of data reading from the memory cell, and the bit line is a line that transmits write data from the memory cell. Also, sub data bus 1
Reference numeral 7 denotes a line for transmitting read or convolution data from the memory cells to the long terminal of the switching/disconnecting circuit 18, which is the sub-memory array 1.

It is shared within. In the case of a storage device in which one word consists of bits, at least one data bus is required. The switching/disconnection circuit 18 is connected to the sub-memory array 10
Switching/disconnection control circuit 1 is a circuit that switches or disconnects the connection between the internal data bus and the main data bus.
A circuit 9 generates a control signal based on the control code output from the internal address/control code generation circuit 12 and outputs it to the switching/disconnection circuit 18. The word line selection circuit 13 is a circuit that inputs at least 1092M bits of internal X address data, decodes it, and outputs a selection signal for selecting one of M word lines,
The word line drive circuit 14 changes the state of the word line based on the selection signal output from the word line selection circuit 15 to an active state opposite to the active state in which data can be input/output to the memory cells connected to the word line. This is a circuit that controls switching to an inactive state. The multiplexer 15 includes a circuit that connects or disconnects the memory cells arranged on the i word line when activated to the sub data bus 17. The multiplexer control circuit 16 has at least 1 of 2
A circuit that inputs N-bit internal Y address data and outputs a signal arranged for each bit line to switch and control the state of the next multiplexer to a connected state or a disconnected state.
Control is performed to prevent two or more memory cells from being connected to the same sub-data bus 17 at the same time.

The operation of the memory device of this embodiment will be described below in the case where data having a bit length equivalent to 91 words is read across a plurality of memory cell groups having different internal addresses.

First, the internal address/control code generation circuit 12 generates, from externally input address data, an internal address of the memory cell group in which the data to be read is stored and a control code that defines the connection relationship between the sub data bus and the main data bus. These data sets are output for each sub-memory array 10 to which the memory cell to be read belongs. Next, in each sub-memory array 10, the word line selection circuit 13 decodes the input internal X address data and sends it to the word line drive circuit 14 as a selection signal for selecting only one of the plurality of word lines. Output. The word line drive circuit 14 switches the state of the word line from a write inhibited state to a write enabled state when reading te to a memory cell. Specifically, the multiplexer control circuit 16 generates a multiplexer control signal based on the input internal Y address data and outputs it to the multiplexer 15.

In response to the control signal, the multiplexer 15 connects the memory cell on the word line in the read/write enabled state to the sub data bus 17. At this time, the number of memory cells connected to the sub data bus 17 does not exceed the number of memory cells corresponding to one word of data. The switching/disconnecting control circuit 19 generates a control signal from the input control code and outputs it to the switching/disconnecting circuit 18 . The switching/disconnecting circuit 18 performs an operation of switching or disconnecting the connection relationship between the data bus in the sub-memory array 10 and the main data bus based on the control signal. Through these series of operations, a specific memory cell is selected from among the memory cell groups having the same internal address in each sub-memory array 10 and electrically connected to the main data node. The output data from the memory cell is
The data is collected on the main data bus in the order of the external output arrangement, becomes one word data to be set out, and is output to the outside of the storage device. FIG. 1 shows sub-memory array 10s1,
The figure shows a state in which two memory cells each from Na2, . . . , SuP are selected and connected to the main data bus. Note that, as a special case, the same applies when all the data to be read is stored in a memory cell group having the same internal address; in this case, the read operation is performed using only one sub-memory array 10. Become.

Next, we will explain the operation of the storage device of this embodiment in the case where data having a bit length equivalent to 91 words is loaded across multiple memory cell groups having different internal addresses. The generation circuit 12 internally generates an internal address and a control code from externally input address data and outputs them to each sub-memory array 10. Next, within the sub-memory array 10, the word line selection circuit 1
3. Word line drive circuit 14, multiplexer control circuit 1
6. Multiplexer 15, switching/disconnection circuit 18 =
Similarly to the read operation, a specific memory cell is selected from a group of memory cells having the same internal address and electrically connected to the main data bus. be. On the other hand, the flow of write data is opposite to that during read.

In other words, one word of data externally input onto the main data bus is divided into data for each memory cell group having the same internal address by the function of the switching/disconnection circuit 18, and the data in each sub-memory array 10 is divided into data for each memory cell group having the same internal address. The data is guided to the bus and written to the memory cell to be written.

The external address assigning method in the first embodiment will be explained using the following application example.

Example of Application to Main Storage Device: As a first example of application of the embodiment shown in FIG. An example of performing a high-speed concatenation operation on data is shown below.

In a storage device, a series of data is divided into data units of words and stored. Therefore, unless a series of data can be divided into word units of data without any remainder, an empty bit in which no data is stored occurs at the end of a word where the end of a series of data is stored. When concatenating a series of data, it is necessary to sequentially fill the empty bits with the data at the beginning of the subsequent data.

Figure 2G shows a one-dimensional data arrangement.
Blocks E(-), E(a+1), 11(a +
2) + E (e ” 3) +・・・・・・
Each corresponds to one word of data, that is, one bit of data. Here, it is assumed that data in each block is stored in a memory cell group having the same internal address.

Also, the data of the end part of the preceding data is stored in the first (a-1) bit in block #(s+1).
It is assumed that the remaining (&-1+1) bits are empty. In order to fill this empty bit with subsequent data, if the first word data of a series of subsequent data is read from the storage device and written from the first bit in block E(s+1), this write data will be written as block ff(*+1). Block E (data spanning 27° lock of #+2 pins).

After that, a series of subsequent data is read out one word at a time,
Even when writing data concatenated to the end of preceding data so that empty bits do not occur, all data will span two blocks. In order to freely read or write data spanning two blocks from a storage device, the memory array is divided into two sub-memory arrays in the embodiment shown in FIG. This can easily be accomplished by configuring the internal address/control code generation circuit so that data in adjacent blocks are stored in different sub-memory arrays, as shown in Figure 2.

When extracting or writing data having a pit length equivalent to one word from this storage device, it is necessary to provide both the above-mentioned information for distinguishing blocks and information for discriminating bit positions within blocks as external addresses. If this condition is satisfied, the internal address data and control code can be internally generated from externally input nine address data by the function of the internal address/control code generation circuit, so the method of assigning external addresses is completely free. As an example of the external addressing method, E(-n; (a = 1 +..., 2kPQ) indicating the above-mentioned block type and LQC(t) indicating the bit position within the block:
(s ” 1 +..., k), two sets of numerical values ADREX (t l g); (#='+...
・・・・・・＃2kPQ)N (s=1+・・・・・・,
There is a method of using k) as an external address. An example of the configuration of the internal address/control code generation circuit in this case is shown in FIG. 3. In the third diagram, M2 is an arithmetic circuit that calculates a remainder modulo 2, and hD and K are subsequent address generation circuits that add 1 to externally input address data.

In addition, in a normal conductor memory device, the externally input address is represented in binary numbers, so it is possible to find the remainder without using a specific logic circuit by focusing on the least significant bit of the address data. be.

The operation of this internal address/control code generation circuit is as follows. External input friend address data ADREX
(go+gg) is divided into preceding address data "su" used for internal generation of the subsequent address and location data "1.degree.1" which becomes part of the control code.

First, the preceding address data "-0" is input to the arithmetic circuit M2, and the remainder modulo 2 is determined. At the same time, data "-0" is also input to the subsequent address generation circuit K, and 1
address data that is larger than that is generated internally. The output destination sub-memory array of the externally input leading address and the internally generated succeeding address is the third one based on the above-mentioned remainder.
Switching is performed by a switching circuit 30 in FIG. When writing data that spans two adjacent words and has a bit length equivalent to a single word, as shown in Figure 2G,
There are two cases. First, as shown by diagonal lines in FIG. If it belongs to Soria Reina 1, switching circuit 3
0 has a connection shape mt as shown by the solid line in FIG. 3G. On the other hand, if the memory cell group corresponding to externally inputted address data belongs to submemory array 1, and the memory cell group corresponding to internally generated friend subsequent address data belongs to submemory array +2, the switching circuit 30 The connection state is as shown by the broken line. The nine address data that has passed through the switching circuit 30 is divided into two parts, for example, into upper and lower bits, and is output as an internal X address and an internal Y address to the word line selection circuit and the multi-branch control circuit in the sub-memory array, respectively, and is sent to the memory. Used to select cell groups.

Next, the externally input location data “gQ” is
Together with the remainder output from the arithmetic circuit M2, a control code is configured and output to each sub-memory array. The switching/disconnection circuit in the valley sub-memory array is based on the remainder:
Memory cells from the ggoth to the last, i.e., the ggoth, in the same memory cell group, or the first, i.e., the first
The memory cells from the th to the (gg1)th are selected and connected to the main data bus in accordance with the data output arrangement order. In addition, as a special case, Tomi. =1
In the case of 1., all bits are selected from the preceding memory cell group, and no bit is selected from the succeeding memory cell group. Assuming that the Q01 word is a bit, and the switching/disconnecting circuit is configured with a switch that takes two states, a conductive state and a non-conductive state, at least two
switches are required.

In addition, it is possible to assign the memory cell in which the first bit in block E is stored as the external address ADREX, and then assign it in ascending order, or any other method of assigning external addresses. When using the above method, a circuit may be required to convert an externally input address to an internal address determined by the memory array configuration, but basically the configuration is the same as the internal address/control code generation circuit described above. It can be realized using the following method.The method for configuring the internal address/control code generation circuit used for reading or writing data spanning two adjacent words is to input the subsequent address data externally and use a subtraction circuit. A configuration method in which the preceding address is generated internally is also possible and has the same effect.

Application example to the image processing field: As a second application example of the embodiment shown in FIG. 1, a display frame memory is configured using this storage device, and image processing is performed on image data in the frame memory. An example of how to do this is shown below.

In the field of image processing, pixel data is read in blocks from frame memory for purposes such as border tracking.

It is often the case that arithmetic processing is added and then written to the frame memory again in blocks. For convenience of explanation, a binary image in which one pixel data can be expressed by one bit is assumed, and a method of dividing frame image data into one unit in units of one word, that is, bit data is shown in FIG. This is 1 pixel vertically and k horizontally.
/a pixel, using a simple division method in which each pixel is one block, and the data of one pixel block is stored in several memory cells having the same internal address. In this division method, as shown in block A in Figure 2, one pixel block at an arbitrary position consisting of # pixels vertically, k/a pixels horizontally, and 1itk pixels has a maximum of 4 pixels on the block-divided frame. You will be crossing blocks.

Therefore, in order to write t7t, which freely reads one pixel block data at an arbitrary position from the frame memory, 94 blocks of pixel data adjacent to each other on the frame must be simultaneously read out in the storage device. Something is necessary. In the embodiment of the present invention, the memory array is divided into four sub-memory arrays, and ÷
As shown in 1-4, this can be easily realized by setting the internal address/control code generation circuit so that the data of adjacent friend pixel blocks on the frame are stored in different submemory arrays.

Book storage device! From the frame memory configured using t,
When reading or writing one pixel block data spanning multiple blocks, as shown by block A in FIG.
It is necessary to provide information that uniquely determines the position of the target pixel block on the frame, including it in the external address.

As long as this condition is met, we are completely free to assign external addresses61, and the internal address/control code generation circuit has one internal address/control code generating circuit that provides related internal address data necessary for reading or writing data from externally input address data. and control codes can be generated internally.

- As an example, assume that the external address represents the top left pixel position in the aforementioned block A, and divide the frame data into blocks and label 9 o'clock B (g, h); (g = L...
...,G)J (A=1.....,H) and 1
LOC' (w+w+
) ; (w=L...* ”/)+ (w=t
, ..., W), ADEEX' (Qrh, vz+u); (g=1.
−・−IG) r C&= 1. H..., H
)+ (w= 1+ -..., V), (so=1
゜..., W) There is a method of using t-external address.

A configuration example of the internal address/control code generation circuit in this case is shown in No. 3116. In Figure 3, M2 and M
4 is an arithmetic circuit that calculates the remainder modulo 2 and 4, respectively, and hD and K' are externally input address data "f,
``Mano'' is necessary in the adjacent address generation circuit that adds 1 to ``50''.In addition, in normal storage devices, addresses input externally are expressed in binary numbers, so we focused on the least significant bit of the address data. Then, it is also possible to obtain the remainder modulo 2, and by focusing on 2 bits including the least significant bit, the remainder modulo 4t can be obtained without using a specific logic circuit.

This internal address/control code generation circuit operates as follows. Externally input address data ADRIf:X
' (go r Ao, var VQ) represents the position of the block to which the upper left pixel belongs, and upper left address data "go + h" used for internal generation of adjacent addresses.
a” and location data “ν” which becomes part of the control code. It is divided into 1wl and 'T.

First, the data "go" is input to the arithmetic circuit M2, and the data "50" is input to the arithmetic circuit M4Vc, and the remainder modulo 2 and the remainder modulo 4 are determined, respectively.

At the same time, the data "go" and 4oIT are also respectively input to the adjacent address generation circuit ', and dog-grained address data by 1 is generated. Four adjacent addresses consisting of the externally inputted upper left address and the internally generated lower left, lower right, and lower right addresses are output to the sub-memory array through the switching circuit shown in FIG. Note that the switching circuit is controlled based on the above-mentioned remainder so that two or more pieces of address data are not output to the same sub-memory array. As an example of the case where data ft, which spans four adjacent words and has a bit length equivalent to one word, is read out, the pixel data t of the next block A is read out with diagonal lines in Figure 2. Explain. In this example,
The data of the block specified by the upper left address "g.,ho" is stored in the memory cell group belonging to the sub-memory arrayer 9.

The data of the adjacent upper right, lower left, and lower right blocks is
They are stored in memory cell groups belonging to sub-memory arrays 1, 2, and 3, respectively.

Therefore, the switching circuit will take the connection shape Mk shown by the solid line in FIG. 3 based on the remainder. Although not shown in the figure, there are at least four connection states of the switch group determined by the position of block A in the switching circuit. Therefore, if the switch is configured with switches that take two states, conductive and non-conductive, two sets of connections for four people and four outputs are required, so at least 32 switches are required. The pair of address data that has passed through the switching circuit is output as an internal X address and an internal Y address to a word line selection circuit and a multi-breather control circuit in the sub-memory array, respectively, and is used to select a memory cell group.

Next, location data “9g+w” is externally input.

” constitutes a control code together with the remainders output from the arithmetic circuits M2 and M4, and is output to each sub-memory array.The switching/disconnection circuit in each sub-memory array is
A memory cell determined by the location data and the above-mentioned remainder is selected from the same memory cell group, and is connected to the main data bus in accordance with the order of data output arrangement. Assuming that one word is a bit, and when the switching/disconnecting circuit is constructed of switches that take two states, conductive and non-conductive, two switches are required for each sub-memory array. An example of a rule for selecting memory cells having data to be output from the same memory cell group will be described below.

First, based on the comparison result between the location data LOC' (w + w) indicating the pixel position within the block and the externally input friend location data LOC' (ν. .As a special case, if !.=1, groups 2 and 4.

= 1 for groups 3 and 4, and also ν. If =1 and town=1, group 2.5.4 will be empty.

1-LOC' (v + w) + (y=1.
t”””+V) r (w-w.p”””+W)2
, LOC'(v+w): (v=' *・・・・・・
·,Ma. -li+ (y-wg, ++m・, W)l
LOC' (v + w): (1=vg r"..."
+ V) + (vFl r”””+ Machi-ri 4, LO
C'Cv*w): Cv='r"""rv.1)t(11
1=1+"""+Vg 1) Next, 1 group is selected from the above 4 groups based on the above-mentioned remainder.For convenience of explanation.

Assuming that one block in FIG. 2 is composed of 25 pixels, FIG. 2d shows an enlarged view of the vicinity of block 4 to be read. Block A to be read is block fl
(2,28B (2,5), B (5,2), B(
3,3), and the position of block E(2,2) of the upper leftmost pixel is LOG' (3°2
) out. Therefore, the address data input externally is AD
REX' (6 in 2, 2, 3, 2. In each memory cell group that has memory cells to be read LJt,
Memory cells storing data at pixel position LOC' (5, 2) t-The memory cells are classified into four groups, and the diagonally shaded memory cells storing nine pixel data are connected to the main data bus. .

In addition, the top left pixel on the frame is set to the external address AD.
RE:
'(1,1) L, frame appeal u! jfco 2
Various methods of assigning external addresses are possible depending on the purpose of use, such as using dimensional coordinates as external addresses as they are.

When using these external addressing methods, a circuit may be required to convert externally input address data to an internal address determined by the memory array configuration, but basically the internal address/control code described above is required. This can be realized using the same configuration method as the generator circuit. The internal address/control code generation circuit used to generate or write data spanning four adjacent words can be configured by externally inputting the address data of the upper right, lower left, or lower right block, and using an addition or subtraction circuit. A configuration method in which addresses of adjacent blocks are internally generated is also possible and has the same effect.

FIG. 20 shows a method for dividing frame data into blocks, assuming a device memory consisting of one word or bit and image data consisting of a binary image, similar to that shown in FIG. The division method is different from that in Figure b. Namely.

In this division method, one block consists of S pixels vertically and 2/8 pixels horizontally, which corresponds to 2 words in data amount. The unit of data reading is shown in Figure 2 C.
The structure shown in the middle block A is S pixels vertically and K/s pixels horizontally, and the total number of pixels is 6, and the amount of data is equivalent to 1 word.
Ru. Internal addresses are assigned to memory cells that store 2 words of data as a group, and are indicated by E in Figure 2C.
'Cdert): Cr=1,...+R)+Ct=
1, . . . , T) in each block are all stored in memory cell groups having the same internal address. In Fig. 2C, numbers 1 to 3 are labels to indicate that adjacent pixel blocks on the frame are stored in different submemory arrays.In the case of this block division method, three submemory arrays are used. It is possible. Since the sub-memory array requires peripheral circuits such as a word line selection circuit and a multiplexer control circuit, the number of memory array divisions tends to deteriorate the storage density of a storage device such as #1, which has a large number of divisions. This frame image data division method can reduce the number of memory array divisions from 4 to 5 compared to the above-described simple division method, leading to higher density storage devices.

In the case of using the division method shown in Figure 2 0, the mamaru is 2 # drawing trees vertically, h/a pixels horizontally, and the division method is 1 c 1 block for a total of 2 pixels. cell t-
Although it is necessary to assign internal addresses as one group, the method of configuring the storage device, the method of configuring the internal address/control code generation circuit, the method of assigning external addresses, and the data read or write operation are based on the simple division method described above. It can be realized in the same way as a user memory device.

In addition, when the data of one pixel is represented by multiple bits,
7'C Memory cell t that stores data of 2 words or more
A similar storage device can be realized even when internal addresses are assigned as a -1 group, and similar effects can be obtained.

9. In the first embodiment shown in FIG. 1, the function given to the multiplexer is to disconnect the electrical connection between the sub data bus and the memory cells arranged on the word line to be put into the selected state. Alternatively, the sub data bus to which the memory cells are connected is fixed. Therefore, when reading or writing data, a switching/disconnecting circuit is required between the main data bus and the data bus in each memory array to exchange the order of data arrangement. As a second embodiment, a configuration example in which the sub-array data bus is directly connected to the main data bus is also possible, and is one aspect of the present invention, in which the function of the switching/disconnection circuit is made to function as a multiplexer. That is, the multiplexer is configured to use a multiplexer control signal to switch the sub-data bus to which the memory cells arranged on the selected word line are connected. In this case, the multiplexer control circuit will generate a multiplexer control signal from the Y address data and a second control code corresponding to the control code in the first embodiment. Note that the operation, external address assignment method, application field, and effects of the second embodiment are the same as those of the first embodiment.

Furthermore, in the first and second embodiments, a configuration was shown in which a memory cell array is arranged for each sub-memory array, but in each embodiment, the memory cell array, word line selection circuit, and word line drive circuit are arranged between sub-memory arrays. The third and fourth embodiments will also be possible as soon as they are made common. third or fourth
In the embodiment, assuming that the total number of memory cells in the first to fourth embodiments is the same, (1) increasing the density in terms of area by reducing the number of word line selection circuits and the number of word line driving circuits; (2) The memory device has the advantage of reducing power consumption by reducing the total number of peripheral circuits such as word line drive circuits that operate during reading or writing. By the way, the sub-memory cell array has a structural restriction that only memory cells arranged on the same word line are enabled for reading or writing at the same time. Therefore, when a memory cell array is shared between sub-memory arrays as in the third or fourth embodiment, memory cell groups that are to be read or written in each memory array at the same time are placed on the same word line. internal address/
It is necessary to set up a control code generation circuit. On the other hand, since the number of memory cells that can be arranged on the same word line is limited, there is a limit to the above setting. This means that, as a special case, data 'Jfr,R' extending across a plurality of memory cell groups and having a bit length equivalent to one word may occur in a case where it is impossible to write.

However, the number of memory cells arranged on the same word line is
Since the number of memory cells is sufficiently large compared to the number of memory cells that store one word of data, a configuration in which the memory cell array is shared among multiple submemory arrays is used, and for a t storage device, 91 times the number of memory cells spanning memory cell groups having different internal addresses is used. When reading and writing data having a bit length equivalent to a word, it is rare to encounter the above-mentioned special case. In addition,
Although the third and fourth embodiments have the above-mentioned restrictions on use, their operation, external address assignment method, field of application,
The effect is equivalent to the first or second embodiment.

Finally, as a memory array partitioning method for the storage device of the present invention, all of the partitioning methods that mix the sub-memory array configurations used in the first to fourth embodiments are also possible.
The same effects as in the embodiment can be obtained. Furthermore, since there is no limit to the number of memory array divisions, even if external read or write data with a pit length equivalent to one word spans four or more memory cell groups with different internal addresses, Embodiments 1 to 4 or a combination of these f
A storage device similar to cw configuration can be realized and similar effects can be obtained.

〔Effect of the invention〕

As explained above, the memory device of the present invention is equipped with an internal address/control code generation circuit that generates related internal address data and control codes from externally input address data. There is an advantage that a user can freely write data having a bit length of one word across the memory without being aware of the internal address. Therefore, when used as the main storage device of a computer system, etc., in the concatenation operation of data in the storage device, which is often used as a basic operation, the main processing unit performs only the detection of the final bit position of the preceding data; can be executed by simply reading and writing data from the storage device, which has the effect of speeding up processing and significantly reducing the time occupied by the arithmetic unit, which is the most frequently used computer system resource. It's big. Also in the field of picture processing, configuring a 7-frame memory using the storage device of the present invention has the effect of greatly reducing the overhead time caused by the time required to transfer data from the frame memory. That's 6.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of the configuration of the first embodiment of the present invention, and FIGS. FIG. 3 ar& is an embodiment configuration diagram of the internal address and control code generation circuit in the first embodiment. FIG. 4 is a diagram showing the basic configuration of a conventional semiconductor memory device. This is a diagram showing the address assignment method. WD(i): (t=1.....,M)...
Word line BL(j) i (j=1.....,k
N)-°°bit line D(q), 5D(qn; (q=1.
......,k)...Data bus ADHIN(z
, y), ADHIN (g+ 1 , y), ADHIN
(z+2.y)roo・Internal address data label 10...Sub memory array 11...Sub memory cell array 12-゛°Internal address and control code generation circuit 15
...Word line selection circuit 14...Word line drive circuit 15...Multiplexer 16...Multiplexer control circuit 17...Sub data bus 18...Switching and disconnection circuit 19...Switching and disconnection control Circuit 30...Switching circuit 40...Word line selection circuit 41...Word line drive circuit 42...Multiplexer 45...Multiple tab control circuit 44...Memory cell array 45...Memory cell FIG. (Part 2) Figure 3

Claims (2)

[Claims] (1) A memory cell capable of storing at least one bit of data is arranged at each intersection of a word line that transmits a signal for switching and controlling permission or prohibition of data read or write and a bit line that transmits read or write data. a memory cell array, a word line selection circuit that inputs internal X address data and outputs a word line selection signal to the word line drive circuit, and a word line drive circuit that controls switching of the state of the signal carried on the word line to an enabled state or a disabled state. a first multiplexer control circuit that inputs internal Y address data and outputs a first control signal to the multiplexer; and a first multiplexer control circuit that inputs internal Y address data and outputs a first control signal to the multiplexer; a first multiplexer that selects a specific memory cell based on a control signal and connects the specific memory cell to a sub data bus; and a switching/disconnection control circuit that generates a second control signal from the first control code. and a first sub-memory array having as a component a switching/disconnecting circuit that switches or disconnects the connection state between the sub-data bus and the main data bus based on the second control signal, or the memory cell array. , the word line selection circuit, the word line drive circuit, and a second multiplexer control circuit that receives the internal Y address and the second control code and outputs a third control signal to the second multiplexer; a second multiplexer that switches or disconnects the connection between the memory cells arranged on the word line in the data read or write enabled state and the sub data bus directly connected to the main data bus based on the third control signal; a first memory array configuration divided into at least one sub-memory array of a second sub-memory array having as a component, or word line selection between at least two sets of sub-memory arrays in the first memory array; Either a second memory array configuration in which a circuit, a word line drive circuit, and a memory cell array are shared, or a third memory array configuration in which submemory array configurations in the first and second memory arrays are mixed. the main data bus, internal X address data and internal Y address necessary for reading or writing data having a bit length equivalent to one word across multiple memory cell groups having different internal addresses; An internal address having means for generating three types of data sets consisting of data and a first or second control code from externally input address data and outputting them for each sub-memory array to which a memory cell to be read or written belongs. 1. A storage device comprising: a control code generation circuit as a component. (2) a first arithmetic circuit that calculates a remainder modulo a certain numerical value from all or part of the externally input address data; a second arithmetic circuit that internally generates subtracted and linked address data; and a sub-memory array to which the internally generated address data including the portion of the externally input address data is output, which is output from the first arithmetic circuit. an internal address/control code generation circuit having a switching circuit that switches based on the remainder, and having means for generating a control code using a part of the externally input address and the remainder output from the first arithmetic circuit; 2. The storage device according to claim 1, wherein the storage device is equipped with a storage device.