JPS58121455A - Priority circuit - Google Patents

Abstract

PURPOSE:To reduce the area of chips and to shorten the delay time, by constituting a titled circuit with a memory structure, transmitting the logical condition of a column line having higher priority to a determined row-line, and by forcibly setting other column lines to specific logical conditions. CONSTITUTION:Horizontal lines of the diagram constitute OR arrays which input data of crossing column lines shown by the dot in the diagram and transmit the result of OR to row lines, and column lines input data of row lines which cross at points O and take the result of ANDs. The operational principle of the priority circuit is of a kind of look-ahead system which forcibly set data having optional priority to 0 (zero) by the existence of some data having a value of ''1'' among all data having higher priority than the optional priority, and the delay is not effected by the number of inputs and the input conditions. When the circuit 3 is divided into small blocks and a hierarchical structure of the same circuit of a small scale is considered and the density is made higher, circuits having the same function and a small area can also be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION When a binary series consisting of logic 1 and logic 0 is input, only the output corresponding to the leftmost or rightmost logic 1 position with a high priority is set to logic l. All outputs to the left of the output corresponding to the high-priority logic 1 position are forced to logic 1, and all outputs to the right of it are forced to logic 1. The present invention relates to a configuration of a priority circuit having an array structure including a plurality of row lines and a plurality of column lines.

Generally speaking, priority circuits are as follows.

In Figure 1, 11 is the input line of priority circuit 1, 01 is rl
The output line corresponds to Now, the priority of the data of ■+ is set as the i-th highest priority (i=1.2°..., n). Then, if we think with positive logic, the data is “1” in the human power 11.
”, the line with the highest priority is 1m.
Then, for the input data of 1+= “O” i<m @ 1 ” i=m “O”or” 1 ” i>m, 01= “O” i≠I “1” ■= Outputs the floor (See Figure 1(b)) Conventionally, this type of priority circuit selects the input conductor with the highest priority when one or more of the input conductors to which priorities are assigned are simultaneously activated. The priority encoder circuit that provides the binary address of the high input conductor was constructed with random logic as shown in Figure 2. The input conductor Do=D7 has a thick number (
They are assigned a higher priority in order of priority.

When Ein is 1, the binary address of the activated conductor with the highest priority Q2. Provides Ql and QO.

The output Gs produces a 1 output if E in = 1 and at least one of the input conductors is activated.

On the other hand, the output Eout is only available when Ein=1.

~1 when none of the input conductors of D7 is activated
Generates output. The random logic that realizes such an 8-bit priority encoder is shown in Figure 2 (
Shown in b).

However, since this type of conventional priority circuit 2 does not have a memory structure, when the number of inputs becomes very large, the chip area becomes large and the delay time becomes very large. It was not suitable for If (LSI).

According to the present invention, the circuit structure is made into a memory structure consisting of a plurality of row lines and column lines, and the logic 1 of the column line with the highest priority among the column lines is
Alternatively, by transmitting a logic O obtained by inverting the logic 1 using an inverter to a predetermined row line, the other column lines are forcibly set to logic 0 or logic 1. The purpose of this invention is to provide a priority circuit with a small delay time.

In a memory structure consisting of multiple row lines and multiple column lines,
By transmitting the logic state of one of the column lines or the inverted logic of the logic state to a predetermined row line of the row lines, the other column line is controlled at each intersection of the row line and the column line. It is to force a logic circuit that exists in a particular logic state into a specific logic state.

Next, an embodiment of the priority circuit of the present invention will be described with reference to the drawings.

In realizing a priority circuit, even when the number of inputs n is very large, the circuit area must be made as small as possible, and the delay must also be shortened. A circuit that satisfies these points has been devised, and its basic circuit is the one shown in FIG. Let's use positive logic here.

In Figure 3, the horizontal line constitutes an OR array that receives the data of the column lines that intersect at the mark and transmits the OR result to the row line, and the column line inputs the data of the row lines that intersect at O, and the result of the AND. The principle of operation is that data of any priority is forced to 0 by the presence of data whose value is 1 among all data of higher priority. This is a kind of look-ahead method, and the delay is not affected by the number of inputs or the input state.If the area S of the circuit 3 in Fig. 3 is expressed based on the number of row lines and column lines, then in the case of n inputs, 3= nx (n-1) ・・・・・・(11) Since n is required to be quite large for practical purposes, it is difficult to implement circuit 3 in Figure 3 as the area is too large as an additional circuit. It is.

Therefore, we devised a circuit with the same function but a small area by dividing circuit 3 in Figure 3, considering a hierarchical structure of small-scale identical circuits, and increasing the density.

FIG. 4 shows a priority circuit 4 in which the four-man power circuit of FIG. 3 is hierarchically connected. In the second stage, AND and O
If it is noted that the function of R is controlled simultaneously for four column lines as one unit, it will be understood that the function is similar to that of the first stage.

In general, let the number of inputs of the basic circuit for division be P, and the number of hierarchical stages be m. In FIG. 4, P=4. The following can be said about the hierarchical priority circuit (m=2).

When configuring a priority circuit where the number of inputs is N, if the maximum number of row lines that intersect with the same column line is M, then pm≧N ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
・ ・ ・ ・ (2) M÷m(P-1) ・ ・
・ ・ ・ ・ ・ ・ ・(3) holds true. (2
) Since it is most efficient when the sign holds true in the equation, Pm=N ..., ...... As (2), the method of division that minimizes the area as a priority circuit is determined. Seek. The area SP is expressed as SP=MXN, and since N is a constant, P that minimizes M is expressed as (2
)′ and (3). (2) ” +31 to M-
((P-1) /1nP) 1nN...141dM
/a p= (1nP-(P-1), /P) /<x
npf=0 ・・・・・・・・・・・・(5) as InP-(P-1)/P ・ ・ ・ ・ ・ ・
- (6) is the condition. Equation (6) is satisfied when P=1, but this does not satisfy Equation (2), and from the condition that P is an integer, P that minimizes M is P==2...・・・・・・・・・(7) M-(
1/1n2)lnN (8). For example, if the number of inputs is N-2"=1024, M=1 from (8)
0, and only 10 lines are required. This is a significant area restriction compared to the circuit shown in FIG. 3, which required N-1=1023 wires. FIG. 5 shows a priority circuit 5 formed by adding an additional circuit for expansion to the optimized priority circuit of P=2.

In Fig. 5, as in Fig. 3, the row lines form an OR array by inputting the data of the column lines that intersect at the * marks, and the AND array for the column lines uses the data of the horizontal lines intersecting at the O marks as input.
Configure the array. Inputs 11 to I2-1 are each AN
Add as input to D array. Horizontal lines a and b in Figure 5
is an expansion circuit for multistage connection of this priority circuit, and the input ET can be easily expanded by connecting directly to the output EO of the higher priority circuit or by connecting it to a general carry look ahead generator.

As a specific circuit, it can be easily realized using MOS.

FIG. 6 shows, as circuit example 6, a case in which both rows and 9 columns are NOR arrays, and inputs I, .about.I2 are set to negative logic.

Also, in Figure 7, when a binary series consisting of logic 1 and logic 0 is input, the output corresponding to the rightmost logic 1 position with the highest priority is the border, and the output to the left is marked with an x. This shows a priority circuit 7 in which all outputs on the right side are forced to be logic 1 with the OR element, and all outputs on the right side are forced to be logic 0 with the AND element marked with ○.Here, the * marks simply represent column lines and row lines. means the connection of

If the priority circuit of the present invention is combined with an associative memory, a system with associative functions, that is, designation of a valid area for matching operations in the key section and writing operations in a stacked manner can be created by devising an address decoder or adding a counter.

FIG. 8 shows a block diagram of this system 8. The decoder 10 is special here. Conventional decoders input I'o
There was the following relationship between ~---1 and the outputs Oo~Of-1.

However, A ”= I,, 2”+-1+ IFl-, 2
″-2+...Change this so that the following relationship holds true.

This decoder 10 can be realized by combining a general-purpose decoder with the priority circuit 7 shown in FIG.

Output 101 of decoder 10 and output 201 of key section 20
That is, the matching information output is ANDed by 30 and becomes an input to the priority circuit 40 in FIG. The output 401 of the priority circuit is R
It is connected to the read/write address line of the value section 50 and the write address line 202 of the key section. First, the write operation to the key section and the value section will be explained. The write address is the key part, va
The blue part is common to both, and is specified in address order by the value of the counter register 60. The address data is sent to the aforementioned decoder 10, AND circuit 30. After passing through the priority circuit 40,
The address lines of the key part and the value part are determined.

In addition, in the write mode, the output of the key part is all "1"
so that it is. Therefore, the decoder output is the priority circuit 40.
is controlled as shown in equation (9), and only the word line of the RAM that is set by the counter register 60 becomes 1''.

λ Next, we will discuss the search mode. In this case, the counter register 60 is used as a pointer that points to the boundary of the valid area for matching operations in the key section. The input data is compared with the stored contents in the key section, and -number information is output. It should be noted that the mask register 70 stores any b of the input data.
This makes it a don't care for matching operations. The output 201 of the key section is the decoder output 10
It is ANDed with 1 and input to the priority circuit 40. The area where the output 101 of the decoder 10 is "1" is a valid area. Then, the priority circuit 40 selects the one with the highest priority, and the value section outputs the corresponding data.

In this way, writing is performed in a stacked manner in address order, and the written area becomes the valid area for matching operations. Furthermore, by setting the address in the counter register 60,
It is possible to write in any location and specify any effective area. Note that the AND circuit 30 can be included in the AND array of the priority circuit 40, and the decoder can also be easily realized using the array structure.

, The association shown in Figure 8 is the future MO5LS
It would be quite possible to realize this with a II chip. If capacity is disadvantageous, it is also possible to separate the value section and output it in the form of an address by passing an encoder through the priority circuit output, and use an external RAM as the value section. Furthermore, by using the expansion function of the priority circuit described above, it is possible to connect in multiple stages to form a large system.

4. Explanation of drawings Figure 1 is an explanatory diagram of the input/output relationship of the priority circuit, Figure 2 (a)
, (b) are a truth table of a priority circuit and a configuration diagram of a conventional priority circuit, FIG. 3 is a priority circuit for explaining the operating principle of the present invention, and FIG. 4 is a diagram for explaining a detailed explanation of the present invention. FIG. 5 is a circuit configuration diagram of the priority circuit with the minimum area according to the present invention realized using MOS transistors.
Figure 187 shows a priority circuit of the present invention, which forcibly sets all outputs to the left of the high-priority logic 1 position to logic 1, and forces all outputs to the right to logic 0. FIG. 8 is a system diagram of an associative stack constructed by combining the priority circuit and associative memory of the present invention.

1... Conceptual diagram of priority circuit, 2... Conventional priority circuit,
3. 4. 5... Priority circuit showing the division method of the present invention, 6... Specific enclosure of the priority circuit, 7... Priority circuit providing a boundary area, 8... Associative stack, 10... Decoder, 20... key part, 40... priority circuit,
50... value section.

Patent applicant 1) Naka Hiroshi Representative Patent Attorney Yoshiyuki Okan ((L) klAl diagram Figure 1A2 ((L) Calculation 2 factors (b) Figure 6 f′= Or 02 0304o5o6 Kuzu 7 Tomoe

Claims (1)

[Scope of Claims] (1) In a memory structure consisting of a plurality of row lines and a plurality of column lines, the logic state of one of the column lines or the inverted logic of the logic state is determined in advance by the predetermined logic of the row line. 1. A priority circuit that forcibly sets other column lines to a specific logic state by a logic circuit existing at each intersection between the row line and the column line. (2. In the priority circuit described in claim 1,
Means for dividing a circuit to minimize the area of said memory structure without changing the functionality of the circuit. (3) A priority circuit according to claim 1, which is connected to an output of a storage circuit and activates and outputs only the output at a higher priority position among the activated outputs of the storage circuit. (4) A hierarchical structure according to claim 1, further comprising means connected to the output of a storage circuit and sequentially selecting outputs from a high priority position to a low priority output among the activated outputs of the storage circuit. priority circuit.