JPH0156412B2 - - Google Patents

Info

Publication number
JPH0156412B2
JPH0156412B2 JP58173574A JP17357483A JPH0156412B2 JP H0156412 B2 JPH0156412 B2 JP H0156412B2 JP 58173574 A JP58173574 A JP 58173574A JP 17357483 A JP17357483 A JP 17357483A JP H0156412 B2 JPH0156412 B2 JP H0156412B2
Authority
JP
Japan
Prior art keywords
key
memory
processor
write
write command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58173574A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6065359A (ja
Inventor
Masakazu Mise
Yoshiro Sakurauchi
Satoshi Tomono
Satoru Fukami
Taichi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58173574A priority Critical patent/JPS6065359A/ja
Publication of JPS6065359A publication Critical patent/JPS6065359A/ja
Publication of JPH0156412B2 publication Critical patent/JPH0156412B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Storage Device Security (AREA)
JP58173574A 1983-09-20 1983-09-20 マルチプロセツサシステム Granted JPS6065359A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58173574A JPS6065359A (ja) 1983-09-20 1983-09-20 マルチプロセツサシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58173574A JPS6065359A (ja) 1983-09-20 1983-09-20 マルチプロセツサシステム

Publications (2)

Publication Number Publication Date
JPS6065359A JPS6065359A (ja) 1985-04-15
JPH0156412B2 true JPH0156412B2 (enrdf_load_stackoverflow) 1989-11-30

Family

ID=15963082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58173574A Granted JPS6065359A (ja) 1983-09-20 1983-09-20 マルチプロセツサシステム

Country Status (1)

Country Link
JP (1) JPS6065359A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6065359A (ja) 1985-04-15

Similar Documents

Publication Publication Date Title
US6151663A (en) Cluster controller for memory and data cache in a multiple cluster processing system
US5682512A (en) Use of deferred bus access for address translation in a shared memory clustered computer system
US4481572A (en) Multiconfigural computers utilizing a time-shared bus
JP2886856B2 (ja) 二重化バス接続方式
US4586133A (en) Multilevel controller for a cache memory interface in a multiprocessing system
US4385351A (en) Multiprocessor system with apparatus for propagating cache buffer invalidation signals around a circular loop
US5835714A (en) Method and apparatus for reservation of data buses between multiple storage control elements
US5089953A (en) Control and arbitration unit
JP3195489B2 (ja) 外部記憶制御装置およびバス切り替え制御方法
JPH08180030A (ja) 複合計算機システムのメモリ装置
JPH0156412B2 (enrdf_load_stackoverflow)
JPH0731666B2 (ja) プロセッサ間通信方式
JPH0452982B2 (enrdf_load_stackoverflow)
JPH0281255A (ja) マルチプロセッサコンピュータ複合装置
USRE38514E1 (en) System for and method of efficiently controlling memory accesses in a multiprocessor computer system
JP3141948B2 (ja) 計算機システム
JP2001167047A (ja) ブリッジ装置
JPS638500B2 (enrdf_load_stackoverflow)
JP2837522B2 (ja) 入出力命令制御方式
JP3348704B2 (ja) 二重化装置及びそれに用いる状態一致制御方法
JPH03232052A (ja) 共有データの排他アクセス方式
JP3012402B2 (ja) 情報処理システム
JPH04330541A (ja) 共通データ転送システム
JPS5975354A (ja) プロセッサ装置
JP2001022710A (ja) 複数のバス制御装置を有するシステム