JPH0155458B2 - - Google Patents
Info
- Publication number
- JPH0155458B2 JPH0155458B2 JP56127217A JP12721781A JPH0155458B2 JP H0155458 B2 JPH0155458 B2 JP H0155458B2 JP 56127217 A JP56127217 A JP 56127217A JP 12721781 A JP12721781 A JP 12721781A JP H0155458 B2 JPH0155458 B2 JP H0155458B2
- Authority
- JP
- Japan
- Prior art keywords
- drive circuit
- display
- electrode
- display section
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 description 7
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
本発明は駆動回路を画素ごとに一体的に設け、
各画素対応の駆動をなすエレクトロルミネツセン
ス（EL）表示装置のような平板形表示装置の改
良に関するものである。[Detailed Description of the Invention] The present invention provides a drive circuit integrally for each pixel,
The present invention relates to improvements in flat panel display devices such as electroluminescent (EL) display devices that drive each pixel individually.
近年、画面走査のフレーム周期に影響されるこ
となく高輝度表示をなす方式のマトリツクス形
EL表示装置の研究、開発が行われている。この
ようなEL表示装置は、表示画素を定める画素電
極をマトリツクス状に配設し、それら表示電極上
に表示媒体となるEL層を積層して表示部を構成
し、また前記各画素電極を個別に駆動するメモリ
機能をもつた駆動回路を例えばSiウエハ上に集積
化して駆動回路基板を形成し、その駆動回路基板
上に層厚1μm程度のSiO2膜を介して前記表示部
を一体的に積層することによつて、各画素対応の
駆動をなすようになつている。第１図はそのよう
なEL表示装置における一画素部分の電気的等価
回路を概略的に示す図であつて、一点鎖線１で囲
んで示した部分は駆動回路であり、その駆動回路
１は電界効果トランジスタ（FET）Q1，Q2と蓄
積キヤパシタCsと走査ラインＳおよびデータラ
インＤから構成される。また２は例えばAlから
なる画素電極であつて、その画素電極２上に誘電
体層３ａ，３ｂにはさまれたEL層４が形成して
あり、さらに誘電体層３ｂ上に透明電極５が配設
してある。そして透明電極５にEL素子駆動電源
６が接続してある。 In recent years, matrix-type displays have been developed that provide high-brightness display without being affected by the frame period of screen scanning.
Research and development of EL display devices is underway. In such an EL display device, pixel electrodes defining display pixels are arranged in a matrix, and an EL layer serving as a display medium is laminated on these display electrodes to form a display section, and each of the pixel electrodes is individually arranged. A drive circuit with a memory function for driving is integrated on, for example, a Si wafer to form a drive circuit board, and the display section is integrally formed on the drive circuit board via a SiO 2 film with a layer thickness of about 1 μm. By stacking them, each pixel can be driven individually. FIG. 1 is a diagram schematically showing an electrical equivalent circuit of one pixel portion in such an EL display device, and the portion surrounded by a dashed line 1 is a drive circuit, and the drive circuit 1 It consists of effect transistors (FETs) Q 1 and Q 2 , a storage capacitor Cs, a scanning line S, and a data line D. Further, 2 is a pixel electrode made of Al, for example, and an EL layer 4 sandwiched between dielectric layers 3a and 3b is formed on the pixel electrode 2, and a transparent electrode 5 is further formed on the dielectric layer 3b. It is arranged. An EL element driving power source 6 is connected to the transparent electrode 5.
ところでこのような構造では画素電極２と駆動
回路１を構成するFETQ1，Q2のゲート等との間
に浮遊容量Ｃが存在するためにEL素子を駆動す
る高圧AC電圧による誘導雑音がFETQ1，Q2に悪
影響をおよぼし表示動作を不安定にする。また図
示を省略したが隣接するEL素子からの光が
FETQ1，Q2のチヤンネル部にもれ込み、
FETQ1，Q2の動作の不安定性の原因ともなる等
の欠点があつた。 By the way, in such a structure, since there is a stray capacitance C between the pixel electrode 2 and the gates of FETQ 1 and Q 2 that constitute the drive circuit 1, the induced noise caused by the high voltage AC voltage that drives the EL element is generated in the FETQ 1. , which adversely affects Q 2 and makes the display operation unstable. Although not shown, light from adjacent EL elements
Leakage into the channels of FETQ 1 and Q 2 ,
It had drawbacks such as causing instability in the operation of FETQ 1 and Q 2 .
本発明は前述の点に鑑みなされたもので、その
目的は表示部と駆動回路との間の不要な電気的な
らびに光学的結合を防止し、もつて安定な動作を
図つた構造の表示装置を提供することであり、そ
の特徴は表示媒体に対面して複数の表示画素を定
める画素電極を配設してなる表示部と、該表示部
の各画素電極を個別に駆動する駆動回路を集積化
した駆動回路基板とを一体的に積層してなる表示
装置において、前記表示部と駆動回路基板との間
に、それらの間を電気的ならびに光学的にシール
ドするシールド電極を介在させ、この接地される
シールド電極に前記駆動回路の接地側電極を接続
し、前記シールド電極に設けた接続孔を通して前
記駆動回路の駆動出力と前記画素電極とを接続し
たところにある。 The present invention has been made in view of the above-mentioned points, and its purpose is to provide a display device having a structure that prevents unnecessary electrical and optical coupling between the display section and the drive circuit, and that ensures stable operation. Its features include a display section in which pixel electrodes defining a plurality of display pixels are arranged facing a display medium, and a drive circuit that individually drives each pixel electrode of the display section. In the display device formed by integrally laminating the display section and the drive circuit board, a shield electrode is interposed between the display section and the drive circuit board to electrically and optically shield the gap between the display section and the drive circuit board. A ground side electrode of the drive circuit is connected to a shield electrode provided on the shield electrode, and a drive output of the drive circuit and the pixel electrode are connected through a connection hole provided in the shield electrode.
以下本発明の一実施例をEL表示装置に適用し
た場合について図面を参照して説明する。 Hereinafter, a case where an embodiment of the present invention is applied to an EL display device will be described with reference to the drawings.
第２図は本発明によるマトリツクス形のEL表
示装置における一画素部分の電気的等価回路を概
略的に示す図であつて、第１図における同等部分
には同一符号を付した。図から明らかなように本
発明によるEL表示装置の従来のものと異なる点
は駆動回路１と表示部を構成する画素電極２との
間にシールド電極７を介在させたところにある。 FIG. 2 is a diagram schematically showing an electrical equivalent circuit of one pixel portion in a matrix type EL display device according to the present invention, and equivalent parts in FIG. 1 are given the same reference numerals. As is clear from the figure, the EL display device according to the present invention differs from the conventional one in that a shield electrode 7 is interposed between the drive circuit 1 and the pixel electrode 2 constituting the display section.
このシールド電極７は駆動回路１上に全面形成
してあり、例えばAl膜からなる。そしてFETQ2
のドレインはシールド電極７に設けた接続孔８を
通して画素電極２に接続され、またシールド電極
７は接地してある。このように駆動回路１上の全
面にシールド電極７を設けることにより、従来存
在していた画素電極２とFETQ1，Q2のゲート等
との間の静電結合が除去されるとともに隣接する
EL素子からの光がFETQ1，Q2のチヤネル部にも
れ込むのも防止され、その結果FETQ1，Q2の安
定な動作が得られるのである。つまりFETQ1，
Q2はシールド電極７によつて電気的にも光学的
にもシールドされることとなる。 This shield electrode 7 is formed entirely on the drive circuit 1, and is made of, for example, an Al film. and FETQ 2
The drain of is connected to the pixel electrode 2 through a connection hole 8 provided in the shield electrode 7, and the shield electrode 7 is grounded. By providing the shield electrode 7 on the entire surface of the drive circuit 1 in this way, the electrostatic coupling between the pixel electrode 2 and the gates of FETQ 1 and Q 2 , etc., which conventionally existed, is removed and the adjacent
Light from the EL element is also prevented from entering the channel portions of FETQ 1 and Q 2 , resulting in stable operation of FETs Q 1 and Q 2 . That is, FETQ 1 ,
Q 2 is electrically and optically shielded by the shield electrode 7.
第３図は本発明によるEL表示装置の構造を説
明するための模式的に示した要部断面図であり、
９は駆動回路基板、１０は表示部である。ここで
駆動回路基板９は例えばSiウエハ９′表面に駆動
回路１を集積化したものであり、各駆動回路１は
FETQ1，Q2蓄積キヤパシシタCs、走査ラインお
よびデータラインＳおよびＤ（第２図参照）で構
成されている。また表示部１０は画素電極２、誘
電体層３ａ，３ｂ，EL層４および透明電極５か
らなつている。そして前記駆動回路基板９の駆動
回路１配設面上に例えばSiO2からなる絶縁層１
１ａ（層厚１〜2μm程度）を形成し、その絶縁層
１１ａ上に例えば層厚5000Å〜1μmのAl層から
なるシールド電極７を形成し、さらにシールド電
極７上には例えば層厚１〜2μmのSiO2からなる
絶縁層１１ｂが形成してある。またその絶縁層１
１ｂ上には表示部１０が一体的に積層して形成し
てある。そして各駆動回路１におけるFETQ2の
ドレインと各画素電極２とは絶縁層１１ａ，１１
ｂおよびシールド電極７に設けた接続孔８′を通
して接続してある。なお本実施例においては各駆
動回路１におけるFETQ2ならびに蓄積キヤパシ
タCsの接地側電極を絶縁層１１ａに設けた接続
孔８″を通してシールド電極７に接続して、シー
ルド電極７に接地用配線の機能を兼備させること
によつて配線数の軽減を図つている。 FIG. 3 is a schematic cross-sectional view of main parts for explaining the structure of the EL display device according to the present invention,
9 is a drive circuit board, and 10 is a display section. Here, the drive circuit board 9 is, for example, one in which drive circuits 1 are integrated on the surface of a Si wafer 9', and each drive circuit 1 is
It consists of FETQ 1 , Q 2 storage capacitor Cs, scan line and data lines S and D (see Figure 2). The display section 10 also includes a pixel electrode 2, dielectric layers 3a, 3b, an EL layer 4, and a transparent electrode 5. Then, an insulating layer 1 made of, for example, SiO 2 is formed on the surface of the drive circuit board 9 on which the drive circuit 1 is disposed.
1a (with a layer thickness of about 1 to 2 μm), and on the insulating layer 11a, a shield electrode 7 made of an Al layer with a layer thickness of 5000 Å to 1 μm, for example, is formed. An insulating layer 11b made of SiO 2 is formed. Also, the insulating layer 1
A display section 10 is integrally stacked and formed on 1b. The drain of FETQ 2 in each drive circuit 1 and each pixel electrode 2 are connected to insulating layers 11a and 11.
b and is connected through a connection hole 8' provided in the shield electrode 7. In this embodiment, the ground side electrodes of the FETQ 2 and the storage capacitor Cs in each drive circuit 1 are connected to the shield electrode 7 through the connection hole 8'' provided in the insulating layer 11a, and the shield electrode 7 has the function of a ground wiring. The number of wiring lines can be reduced by combining the two functions.
このように駆動回路基板９と表示部１０とを前
記シールド電極７を介して一体的に積層すること
により表示部１０と各駆動回路１とが電気的にも
光学的にもシールドされて、各駆動回路１を構成
するFETQ1，Q2の動作の安定化ができるのであ
る。 By integrally stacking the drive circuit board 9 and the display section 10 with the shield electrode 7 in between, the display section 10 and each drive circuit 1 are electrically and optically shielded, and each The operation of FETQ 1 and Q 2 that constitute the drive circuit 1 can be stabilized.
なお前記の実施例では各駆動回路１をFETQ1，
Q2および蓄積キヤパシタCsの組合せで構成した
場合について述べたが、FETQ2と並列に分圧用
キヤパシタを接続することもできるし、また蓄積
キヤパシタCsを省略してFETQ1の代りにメモリ
素子としてSCR素子を用いる等、種々の駆動回
路にも適用可能である。さらにまた表示媒体とし
てELに限らず液晶等のその他の表示媒体を用い
た表示装置に適用して同様の効果を得ることがで
きる。 Note that in the above embodiment, each drive circuit 1 is FETQ 1 ,
Although we have described the case where it is configured with a combination of Q 2 and storage capacitor Cs, it is also possible to connect a voltage dividing capacitor in parallel with FETQ 2 , or omit the storage capacitor Cs and use SCR as a memory element instead of FETQ 1 . It is also applicable to various drive circuits using elements. Furthermore, similar effects can be obtained by applying the present invention to display devices using not only EL but also other display media such as liquid crystal as a display medium.
以上の説明から明らかなように要するに本発明
は表示媒体に対面して複数の画素を定める画電極
を配設してなる表示部と、該表示部の各画素電極
を個別に駆動する駆動回路を集積化した駆動回路
基板とを一体的に積層してなる表示装置におい
て、前記表示部と駆動回路基板との間に、それら
の間を電気的ならびに光学的にシールドするシー
ルド電極を介在させることにより、表示部と駆動
回路を構成する能動素子との電気的ならびに光学
的結合を防止し、これら結合に起因して生じる駆
動回路の動作の不安定性を除去したもので、表示
装置の信頼性の向上に極めて有効である。 As is clear from the above description, in short, the present invention includes a display section having picture electrodes facing a display medium and defining a plurality of pixels, and a drive circuit that individually drives each pixel electrode of the display section. In a display device formed by integrally stacking an integrated drive circuit board, a shield electrode is interposed between the display portion and the drive circuit board to electrically and optically shield the gap between them. , which prevents electrical and optical coupling between the display section and the active elements that make up the drive circuit, and eliminates instability in the operation of the drive circuit caused by these couplings, improving the reliability of display devices. It is extremely effective.
第１図は従来の表示装置における一画素部分の
電気的等価回路を概略的に示す図、第２図は本発
明による表示装置における一画素部分の電気的等
価回路を概略的に示す図、第３図は本発明による
表示装置の一実施例の構造を説明するための模式
的に示した要部断面図である。
１：駆動回路、２：画素電極、３ａ，３ｂ：誘
電体層、４：EL層（表示媒体）、５：透明電極、
７：シールド電極、８，８′，８″：接続孔、９：
駆動回路基板、９′：Siウエハ、１０：表示部、
１１ａ，１１ｂ：絶縁層、Q1，Q2：FET、Cs：
蓄積キヤパシタ、Ｃ：浮遊容量、Ｄ：データライ
ン、Ｓ：走査ライン。
FIG. 1 is a diagram schematically showing an electrical equivalent circuit of one pixel portion in a conventional display device, and FIG. 2 is a diagram schematically showing an electrical equivalent circuit of one pixel portion in a display device according to the present invention. FIG. 3 is a schematic cross-sectional view of a main part for explaining the structure of an embodiment of a display device according to the present invention. 1: Drive circuit, 2: Pixel electrode, 3a, 3b: Dielectric layer, 4: EL layer (display medium), 5: Transparent electrode,
7: Shield electrode, 8, 8', 8'': Connection hole, 9:
Drive circuit board, 9': Si wafer, 10: display section,
11a, 11b: Insulating layer, Q 1 , Q 2 : FET, Cs:
Storage capacitor, C: Stray capacitance, D: Data line, S: Scanning line.
Claims (1)
画素電極２を配設してなる表示部１０と、該表示
部の各画素電極を個別に駆動する駆動回路１を集
積化した駆動回路基板９とを一体的に積層してな
る表示装置において、 前記表示部１０と駆動回路基板９との間に、そ
れらの間を電気的ならびに光学的にシールドする
シールド電極７を介在させ、 この接地されるシールド電極に前記駆動回路１
の接地側電極を接続し、 前記シールド電極に設けた接続孔８を通して前
記駆動回路の駆動出力と前記画素電極２とを接続
した ことを特徴とする表示装置。[Scope of Claims] 1. A display section 10 in which pixel electrodes 2 that define a plurality of display pixels are arranged facing a display medium, and a drive circuit 1 that individually drives each pixel electrode of the display section are integrated. In the display device formed by integrally stacking the display section 10 and the drive circuit board 9, a shield electrode 7 is interposed between the display section 10 and the drive circuit board 9 to electrically and optically shield the gap between them. and connect the drive circuit 1 to this grounded shield electrode.
A display device characterized in that: a ground-side electrode is connected to the pixel electrode 2, and a drive output of the drive circuit and the pixel electrode 2 are connected through a connection hole 8 provided in the shield electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12721781A JPS5828780A (en) | 1981-08-12 | 1981-08-12 | Display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12721781A JPS5828780A (en) | 1981-08-12 | 1981-08-12 | Display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5828780A JPS5828780A (en) | 1983-02-19 |
| JPH0155458B2 true JPH0155458B2 (en) | 1989-11-24 |
Family
ID=14954622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12721781A Granted JPS5828780A (en) | 1981-08-12 | 1981-08-12 | Display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828780A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5587329A (en) * | 1994-08-24 | 1996-12-24 | David Sarnoff Research Center, Inc. | Method for fabricating a switching transistor having a capacitive network proximate a drift region |
| JP6619622B2 (en) * | 2015-11-13 | 2019-12-11 | 株式会社Ｊｏｌｅｄ | Display panel, display device, and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235585A (en) * | 1975-08-29 | 1977-03-18 | Westinghouse Electric Corp | Thin film transistor |
| JPS5527326A (en) * | 1978-08-17 | 1980-02-27 | Ube Ind Ltd | Polyimide resin composition and its preparation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5391678U (en) * | 1976-12-27 | 1978-07-26 |
-
1981
- 1981-08-12 JP JP12721781A patent/JPS5828780A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235585A (en) * | 1975-08-29 | 1977-03-18 | Westinghouse Electric Corp | Thin film transistor |
| JPS5527326A (en) * | 1978-08-17 | 1980-02-27 | Ube Ind Ltd | Polyimide resin composition and its preparation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5828780A (en) | 1983-02-19 |
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