JPH01503827A - 半導体のフイールド酸化物形成方法 - Google Patents
半導体のフイールド酸化物形成方法Info
- Publication number
- JPH01503827A JPH01503827A JP50502788A JP50502788A JPH01503827A JP H01503827 A JPH01503827 A JP H01503827A JP 50502788 A JP50502788 A JP 50502788A JP 50502788 A JP50502788 A JP 50502788A JP H01503827 A JPH01503827 A JP H01503827A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- silicon nitride
- oxide
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Abstract
Description
Claims (5)
- 1.基板アクテイブ領域(5)の上にパッド酸化物層(2)を厚さ範囲50nm 又はそれ以上に形成し、前記パッド酸化物層(2)の上に第1の窒化シリコン層 を厚さ範囲100nm又はそれ以上に形成し、前記第1の窒化物層(3)と前記 パッド酸化物層(2)とを通して前記基板(1)に対しホトレジスト・マスク( 4)の存在下で異方性エッチングしてフイールド酸化物領域をほぼ垂直な側壁( 11)で規定し、前記パターン化された層及び基板の上に公称厚10〜13nm に正角な第2の窒化シリコン層(7)を形成し、前記第2の窒化シリコン層(7 )の水平面を異方性エッチングして前記ほぼ垂直な側壁(11)上に第2の窒化 シリコンを維持しなから前記基板の選ばれた水平面を露出し、前記露出した基板 (1)及び第2の窒化シリコンを酸化して維持されている側壁窒化シリコン(9 )のベンディング及びリフティングを伴う酸化を行い、前記酸化基板表面の上面 が前記パッド酸化物層(2)のレベルに近付くまで前記基板(1)の酸化を続行 し、残留窒化シリコンを除去する各工程を含む半導体基板(1)のアクティブ領 域(5)間にフィールド酸化物領域を形成する方法。
- 2.前記フィールド酸化物領域を規定する異方性エッチングは前記パッド酸化物 (2)の厚さより大きい深さまで前記半導体基板に延びるようにした請求の範囲 1項記載の方法。
- 3.前記深さは約120nmである請求の範囲2項記載の方法。
- 4.前記水平面の異方性エッチングに続くほぼ垂直な側壁(11)に保持されて いる前記窒化シリコン(9)の厚さは公称範囲9〜12nmである請求の範囲2 項記載の方法。
- 5.前記基板(1)はシリコンであり、前記側壁窒化シリコン(9)は前記基板 から成長した酸化物が前記パッド酸化物(2)に達したときに2醇化シリコンに 変換されるようにした請求の範囲3項又は4項記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6192387A | 1987-06-15 | 1987-06-15 | |
US61,923 | 1987-06-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01503827A true JPH01503827A (ja) | 1989-12-21 |
JP2747563B2 JP2747563B2 (ja) | 1998-05-06 |
Family
ID=22039026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63505027A Expired - Fee Related JP2747563B2 (ja) | 1987-06-15 | 1988-05-31 | 半導体のフイールド酸化物形成方法 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0318555B1 (ja) |
JP (1) | JP2747563B2 (ja) |
DE (1) | DE3884151T2 (ja) |
WO (1) | WO1988010510A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321194A (ja) * | 1993-11-23 | 1995-12-08 | Hyundai Electron Ind Co Ltd | 半導体装置の素子分離層の形成方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5248350A (en) * | 1990-11-30 | 1993-09-28 | Ncr Corporation | Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process |
FR2672731A1 (fr) * | 1991-02-07 | 1992-08-14 | France Telecom | Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant. |
EP0540157A1 (en) * | 1991-09-30 | 1993-05-05 | STMicroelectronics, Inc. | Method for submicron isolation for CMOS devices |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4333965A (en) * | 1980-09-15 | 1982-06-08 | General Electric Company | Method of making integrated circuits |
JPS59139643A (ja) * | 1983-01-31 | 1984-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
-
1988
- 1988-05-31 JP JP63505027A patent/JP2747563B2/ja not_active Expired - Fee Related
- 1988-05-31 EP EP88905313A patent/EP0318555B1/en not_active Expired - Lifetime
- 1988-05-31 WO PCT/US1988/001787 patent/WO1988010510A1/en active IP Right Grant
- 1988-05-31 DE DE88905313T patent/DE3884151T2/de not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321194A (ja) * | 1993-11-23 | 1995-12-08 | Hyundai Electron Ind Co Ltd | 半導体装置の素子分離層の形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2747563B2 (ja) | 1998-05-06 |
DE3884151T2 (de) | 1994-04-07 |
WO1988010510A1 (en) | 1988-12-29 |
EP0318555B1 (en) | 1993-09-15 |
EP0318555A1 (en) | 1989-06-07 |
DE3884151D1 (de) | 1993-10-21 |
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