JPH0147049B2 - - Google Patents
Info
- Publication number
- JPH0147049B2 JPH0147049B2 JP59086611A JP8661184A JPH0147049B2 JP H0147049 B2 JPH0147049 B2 JP H0147049B2 JP 59086611 A JP59086611 A JP 59086611A JP 8661184 A JP8661184 A JP 8661184A JP H0147049 B2 JPH0147049 B2 JP H0147049B2
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- slave
- master
- level
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59086611A JPS60230714A (ja) | 1984-04-28 | 1984-04-28 | マスタ・スレ−ブ・フリツプフロツプ回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59086611A JPS60230714A (ja) | 1984-04-28 | 1984-04-28 | マスタ・スレ−ブ・フリツプフロツプ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60230714A JPS60230714A (ja) | 1985-11-16 |
JPH0147049B2 true JPH0147049B2 (enrdf_load_stackoverflow) | 1989-10-12 |
Family
ID=13891810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59086611A Granted JPS60230714A (ja) | 1984-04-28 | 1984-04-28 | マスタ・スレ−ブ・フリツプフロツプ回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60230714A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4719366A (en) * | 1985-10-11 | 1988-01-12 | Advanced Micro Devices, Inc. | Output state protection network for D-type flip-flop |
EP0375247B1 (en) * | 1988-12-21 | 1996-02-28 | Texas Instruments Incorporated | Metastable tolerant latch |
-
1984
- 1984-04-28 JP JP59086611A patent/JPS60230714A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60230714A (ja) | 1985-11-16 |
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