JPH0145154B2 - - Google Patents

Description

[Detailed Description of the Invention] A recording and reproducing device using PCM signals has various characteristics such as being resistant to noise and distortion, and being able to easily remove time axis errors due to speed fluctuations of the recording medium by using digital memory. It has been a long time since attempts have been made to record and play back music signals with high fidelity, but in recent years consumer cassette-type
With the spread of TVR, it has become common practice to use consumer cassette-type VTRs to record and reproduce music signals using the PCM method as PCM signals in a signal format that conforms to the TV signal of the standard TV method.
Various standards related to signal formats and signal processing methods are also included in the technical file established by the Japan Electronics Industry Association in June 1979.
STC-007 “Consumer PCM encoder/decoder”
clarified by.

By the way, regarding signal processing of PCM signals,
It goes without saying that the synchronization signal inserted into the signal plays an important role, but as is well known,
In VTRs, signal dropouts and
The occurrence of skew is unavoidable, and therefore,
Unless the detection of the synchronization signal in the reproduced signal and the protection of the synchronization signal are properly performed, it will not be possible to achieve the desired results even when recording and reproducing using PCM signals. In particular, since the vertical synchronization signal is important as it has information on the starting point of data, a highly accurate circuit arrangement is required for detecting and protecting the signal.

FIG. 1 shows an example of a detection protection circuit for a vertical synchronization signal (hereinafter sometimes abbreviated as V synchronization signal), and FIGS. 2A and B show the operation of the detection protection circuit shown in FIG. 1. This is a time chart to explain. In Fig. 1, 1 is the input terminal of the composite synchronization signal, and this input terminal 1 is connected to a of Fig. 2A.
A composite sync signal as shown in the figure is supplied, and the composite sync signal supplied to input terminal 1 is the PCM signal reproduced from the VTR, that is,
Signal format compliant with standard TV system TV signal
The composite synchronization signal, which is synchronously separated from the PCM signal, is applied to the shift register 2 and the horizontal synchronization signal detection and protection circuit 6.

The horizontal synchronization signal detection protection circuit 6 detects the master clock CLKm supplied to the terminal 9 (for the PCM signal according to the signal format defined in the technical file STC-007 mentioned above, the master clock with a frequency value of 2.643MHZ is supplied to the terminal 9). By giving a horizontal synchronization signal (hereinafter sometimes referred to as an H synchronization signal) from the composite synchronization signal supplied from terminal 1, one horizontal synchronization period is 1H section (H is used as an abbreviation for horizontal synchronization) and protects the horizontal synchronization signal 6 as an output
a {Figure b of Figure 2A} is supplied to the H/2 pulse generation circuit 7.

The H/2 pulse generation circuit 7 is composed of a counter and a decoder, and the counter starts counting the master clock CLKm from the falling edge of the supplied horizontal synchronization signal 6a.
For example, the pulses at time intervals such as H/8 and 5H/8 are generated by the 2.643MHZ master clock CLKm.
Output by counting 21, 105 and H/2 pulse 7a
Output. (The length of the 1H section is expressed by the count value of the master clock CLKm of 2.643MHZ.
The 1H section corresponds to 1687 clocks. ) The H/2 pulse 7a {Figure c in Figure 2A} outputted from the H/2 pulse generation circuit 7 described above is as follows:
The signal is supplied as a shift pulse to the shift register 2 described above, and is also supplied to the supplementary V synchronization signal generation circuit 4. 3 is a coincidence detection circuit, and in this coincidence detection circuit 3, the stored content of the composite synchronization signal stored in the shift register 2 using the H/2 pulse 7a as a shift pulse is changed to a preset specific pattern (for example, "100000011"). ) when it matches,
Output signal 3a with a matching pulse of approximately H/2 pulse width
The above-mentioned output signal 3a given to the supplementary V synchronization signal generation circuit 4 and the continuous output prevention circuit 5 as shown in FIG. It is something that exists.

The supplementary V synchronization signal generation circuit 4 is composed of a 525-base counter and a decoder, and this circuit 4 receives the H/2 pulse 7a given to it.
By counting 525 pieces, the time span of 262.5H,
That is, it is possible to obtain a supplementary V synchronization signal with a signal having one vertical synchronization period, but if the above-mentioned 525-decimal counter is reset by the pattern V synchronization signal 3a described above, dropouts, etc. can be avoided, for example. Even if the pattern V synchronization signal 3a is not output from the coincidence detection circuit 3 due to the influence, a signal 4 having a pulse width of approximately H/2 is generated at the time position where the pattern V synchronization signal 3a should appear.
a can be output. In the following description, the signal 4a will be referred to as the supplementary V synchronization signal 4a.

The continuous output prevention circuit 5, which is supplied with the above-described two signals, the pattern V synchronization signal 3a and the supplementary V synchronization signal 4a, outputs only the signal present at the desired correct time position to the terminal 8 as the V synchronization signal.
That is, the pattern V synchronization signal 3a described above,
The supplementary V synchronization signal 4a is originally not deviated from each other in time position, and as shown in figures c and d in Figs. 5 to 8, which will be described later, However, if, for example, noise is mixed into the input signal or a drop-eye occurs in the signal, the pattern V synchronization signal will not be generated. In this case, as described later, the supplementary V synchronization signal generated by the counter will match the V required to generate the data acquisition start signal.
Used as a synchronization signal.

However, the time position of the supplementary V synchronization signal generated by the counter described above does not necessarily occur at the same time position as the pattern V synchronization signal, as is clear from the explanation example described later. If the time positions of the two signals described above are shifted, two V synchronization signals will be output, causing a problem. Therefore, by providing the continuous output prevention circuit 5 described above, In addition, this continuous output prevention circuit 5 uses the signal 4b supplied from the supplementary V synchronization signal generation circuit 4 to prevent errors in the composite synchronization signal except in the vicinity of the V synchronization signal. The matsuta signal is not output.

FIG. 3 is a block diagram showing a specific example of the configuration of the horizontal synchronizing signal detection protection circuit described above.
Figures a to p show the operation of the circuit arrangement shown in the third figure.
FIG. 3 is a waveform diagram for explaining what kind of protection operation is performed mainly against the loss of a horizontal synchronizing signal due to signal dropouts that generally occur frequently. In FIG. 3, 10 is a differentiating circuit, and this differentiating circuit 10 detects the falling edge (leading edge) of the pulse of the composite synchronizing signal {FIG. 4 a} supplied to the input terminal 1, as shown in FIG. 4 b. A differential pulse 10a as shown in the figure is generated. Although this differentiating circuit 10 is not required in an actual circuit layout, it is used here for the convenience of explaining the operation.

The basic concept of horizontal synchronizing signal detection, protection, and replenishment operations in the circuit arrangement shown in FIG. 3 is as follows. Differential pulse 1 due to the horizontal synchronization signal within the horizontal synchronization signal within the composite synchronization signal
If the next differential pulse 10a is detected within a short time of 2△H after the time (1H-△H) has elapsed since the detection of 0a, the detected differential pulse 10a is a composite pulse. It is determined that the signal is generated by a regular horizontal synchronizing signal among the synchronizing signals, and a horizontal synchronizing signal synchronized with this differential pulse is output.

Here, the above △H can be set to a value corresponding to the amount of time axis variation that occurs in the reproduced composite sync signal due to VTR speed fluctuations, for example, a few percent of 1H. .

Next, as mentioned above, 2
If no differential pulse is detected within the time of △H (=±△H), it is assumed that this is due to the skew peculiar to VTRs, and the first
output a supplementary horizontal sync signal, and measure from the time when the first supplementary horizontal sync signal is output (1H-
Detection of the next differential pulse 10a is started before the time ΔH) has elapsed.

Then, as mentioned above, if the next differential pulse is not detected within 2△H from the time (1H - △H) has elapsed, the operation of outputting the second supplementary horizontal synchronizing signal is repeated. Return, (1H−△
If the next differential pulse is detected within the time period H), the normal horizontal synchronizing signal generation state described above is restored from the next differential pulse following the detected differential pulse.

The basic operation of the circuit arrangement shown in FIG. 3 has been outlined above, but the above operation will be explained in more detail with reference to the waveform diagram shown in FIG. 4 as follows. In Figure 3, 11, 12
are the first and second gates formed by a logic AND circuit, and 13 to 15 are set reset flip-flops (hereinafter sometimes abbreviated as SR/FF13 to 15);
15 is assumed to operate with positive polarity pulses in the following explanation. Blocks 16 to 18 each include a counter having a reset terminal R that is reset by a positive pulse, and output pulses of positive polarity according to a specific count value in the counter. In the following explanation, blocks 16 to 18 are CNT16 to CNT
It is written as 18.

Now, a differential pulse 10a (Figure 4b) generated by the differentiating circuit 10 at time _t1 by the composite synchronizing signal (Figure 4a) supplied to the input terminal 1 being supplied to the differentiating circuit 10 (Figure 4b) #1 in Figure } is the first,
Pass through the second gates 11 and 12 {Fig. 4 h, K
}, further through the OR circuit 21 {Fig.
Figure}, the one-shot multivibrator 20 is triggered, and the one-shot multivibrator 20
From there, a horizontal synchronizing signal is generated at time _t1 as shown in FIG. 4m.

Also, the output pulse 1 from the first and second gates 11 and 12 generated by the #1 differential pulse 10a output from the differentiator circuit 10 at time _t1.
Since the SR/FFs 13 to 15 are reset by signals 1a and 12a, the first and second gates 11 and 12 are immediately closed at time _t1 . 1. This is a diagram displaying the open period of the second gates 11 and 12 at a high level, and FIG. 4 g shows the open period of the first gate 11, and FIG. Indicates the opening period of the gate 12}.

After that, at time t _2, the output of CNT 17 {Fig. 4 e
SR・FF14 is set according to
The output 14a of the FF 14 {FIG. 4 f} is given to the first gate 11 as one of the AND conditions, and at time t ₃ the SR FF 13 and The SR/FF 15 is set, the output 13a of the SR/FF 13 (Figure 4 d) is given to the first gate 11 as another AND condition, and the output 15a of the SR/FF 15 (Figure 4 j) is given to the first gate 11 as another AND condition.
} is given to the second gate 12 as an AND condition.

The #2 differential pulse 10a generated from the differentiator circuit 10 based on the horizontal synchronization signal of the composite synchronization signal at time _t4 is the same as the case of the # ₁ differential pulse 10a generated at time t1 described above. 1. Second gate 1
1, 12 and the OR circuit 21 as a trigger pulse to the one-shot multivibrator 20, and the one-shot multivibrator 20 sends out a horizontal synchronizing signal at time _t4 .

As has been made clear from the explanation so far,
CNT16 is a circuit that has the function of setting the time width of (1H−△H) as described above.
Reference numeral 17 denotes a circuit having a function of detecting and capturing a differential pulse earlier than the time (1H-ΔH) when a skew occurs.

As explained above, when successive horizontal synchronization signals in a composite synchronization signal exist without any omission, the differential pulse 10a generated based on the horizontal synchronization signal is generated by the output of CNT 16. occurs within a short time span from the point in time, which triggers the one-shot multivibrator 20 to generate successive horizontal synchronization signals.

However, if the horizontal synchronizing signal in the composite synchronizing signal is missing for some reason, the differential circuit 10 does not generate a differential pulse, and in this case, the circuit arrangement shown in Figure 3 performs the following operation. A supplementary horizontal synchronizing signal is then generated.Now, we will explain the case where, following the horizontal synchronizing signal that appeared at time _t4 in the composite synchronizing signal, the horizontal synchronizing signal that should have appeared at time _t7 is missing. Then, the result is as follows.

That is, after the horizontal synchronizing signal is generated by the one-shot multivibrator 20 at time _t4 , the output of CNT17 appears at time _t5 , and the SR/FF14 is set by that output, and the output 14a is output.
occurs, and at time _t6 , the output of CNT16 appears and SR・FF13 and SR・FF15 are set,
The first and second
However, since the horizontal synchronization signal that should exist at time _t7 is missing from the composite synchronization signal, the differentiation circuit 10 does not generate the differentiation pulse 10a.

Therefore, the output pulse 11a (Fig. 4h) does not appear on the output side of the first gate 11.
SR・FF13 continues to be set, and SR・FF13 continues to be set.
The FFs 14 and 15 are reset by the pulse outputted from the CNT 18 at time _t8 (Fig. 4 i), and
As a result, the first and second gates are closed at time _t8 , and the output of the CNT 18 passes through the OR circuit 21 to trigger the one-shot multivibrator 20, and the one-shot multivibrator 20
A first supplementary horizontal synchronization signal is generated and output at time _t8 . The CNT 18 described above operates as a counter that functions to measure the time of 2ΔH described above. In addition, SR・FF14 and SR・FF1
5 refers to the output pulse 12 of the second gate circuit 12.
CNT18 is also reset by the output 15b from the SR/FF15, and the number of master clocks CLKm supplied from the terminal 9 is set to a predetermined number. Outputs a pulse when counted, and OR circuit 2
1 to trigger the one-shot multivibrator 20 as described above, and the SR/FF1
4, 15 are reset.

Now, when a pulse is output from CNT17 at time _t9 and SR/FF14 is set by it,
At this point, the SR/FF 13 is set as shown in FIG. 4d, so the first gate 11 is set as shown in _FIG . It will be opened like this. In the example shown in Figure 4, it is assumed that the horizontal synchronization signal that should appear at time _t7 is completely missing, but the position of the horizontal synchronization signal in the composite synchronization signal is shifted back and forth due to skew, and the horizontal synchronization signal that should appear at time t7 is Even if a differential pulse is generated while the synchronization signal interval is expanding or contracting, the differential pulse will not be detected within the time width of 2ΔH mentioned above.
-ΔH) before the time elapses.
In the above case, the position of the #3 differential pulse 10a on the time axis is around the position of the #3 differential pulse in Figure 4b due to skew, so the first It is necessary to open the gate 11 before the time (1H-ΔH) has elapsed.

The # ₃ differential pulse 10a generated by the differentiating circuit 10 based on the horizontal synchronizing signal in the composite synchronizing signal that appeared at time t10 passes through the first gate 11, but the SR/FF 15 is reset at time _t10 . Since the AND condition of the second gate 12 is not satisfied, the above-mentioned #3 differential pulse 10
a cannot pass through the second gate 12. Also,
The CNT 18 is also in a reset state and has no output at time _t10 , so no trigger is applied to the one-shot multivibrator 20 via the OR circuit 21 at time _t10 .

Therefore, in this case, the output of the CNT 19, which is reset by the pulse 12a output from the second gate 12 and is running on its own while counting the master clock CLKm from the terminal 9, is
Figure n} is used as the second supplementary horizontal synchronizing signal.

After the differential pulse 10a of #3 is detected at time _t10 , the differential pulses 10a of #4 and #5 are detected by the circuit operation described above between time _t1 and time _t5 . Detection is performed.

A one-shot multivibrator 20 generates a horizontal synchronization signal or a first supplementary horizontal synchronization signal synchronized with the differential pulse 10a by the free running operation of the CNT 19 #2 in the CNT 19 described above, which is performed with the differential pulse 10a as a starting point. CNT that generates the output of and a second complementary horizontal synchronization signal.
The switching control signal generating circuit 22 that generates the switching control signal 22a used to control the switching operation of the switching circuit 23 that switches between the output of the signal generator 19 and the output of the switching circuit 19 will be explained.

The switching control signal generation circuit 22 uses the output 13a and the output 13a of the SR/FF 13 as switching judgment information.
The output of the CNT 17 {Figure 4 e} is used.
As shown in Fig. 4d, if the differential pulse 10a is not detected within the 2△H period, the SR/FF 13 remains set for a while, such as after time _t6 . Therefore, by taking advantage of this fact and storing the switching judgment contents using the output of the CNT 17, it is possible to obtain a desired switching control signal.

FIG. 4o is a waveform diagram of the switching control signal 22a, and when the switching control signal 22a is at a high level, the switching circuit 23 outputs the output of the one-shot multivibrator 20 as the horizontal synchronizing signal 6a, and also switches the switching control signal 22a. When the control signal 22a is at low level,
The switching operation is such that the output of the CNT 19 is output as the horizontal synchronizing signal 6a, and the horizontal synchronizing signal 6a output from the switching circuit 23 in this way is more stable than the horizontal synchronizing signal in the input composite synchronizing signal. It becomes something.

However, in the circuit arrangement shown in Figure 3, there are extremely special situations: (1) when a large skew (for example, 15 μsec or more) occurs near the V synchronization signal, (2) when a complex synchronization near the V synchronization signal occurs. If a certain pattern of nozzles is mixed into the signal, or if a synchronization signal is missing in a certain pattern, the horizontal synchronization signal will be output with a difference of H/2 period. Something like this happened.

In both cases (1) and (2) above, the problem occurs near the V synchronization signal, and the cause is:
Because equalization pulses are inserted at H/2 intervals near the V synchronization signal, if there is skew or noise, the equalization pulse next to the horizontal synchronization signal may be mistakenly detected. .

In other words, when detecting the horizontal synchronization signal, H/
If skew or noise occurs near the V synchronization signal where equalization pulses are present at intervals of 2, the horizontal synchronization signal will be detected and supplemented at a time position shifted by H/2 from the correct horizontal synchronization signal. Sometimes I put it away. In this case, when attempting to capture data past the V synchronization signal period, it is possible that one extra horizontal synchronization signal is being supplemented.

5 to 8 show this situation, and whether or not the horizontal synchronization signal is redundant depends on the position of the data acquisition start signal indicated by the dotted line in the figures. The data acquisition start signal is generated from the V synchronization signal, and this V synchronization signal is the pattern V synchronization signal shown in each c, g, k in FIGS. Each d, h, l in the figure
is generated by the supplemental V sync signal shown in FIG.

The pattern V synchronization signal and the supplementary V synchronization signal are usually detected or generated at the same time position on the time axis, as shown in figures c and d in Figs. 5 to 8. However, if the detected horizontal synchronization signal has a deviation of H/2, a deviation of H/2 also occurs between the pattern V synchronization signal and the supplementary V synchronization signal.

As the V synchronization signal in this case, the V synchronization signal that was generated earlier is used as explained with reference to FIG. It will be generated by the V synchronization signal.

The indications of "remove" and "as is" shown in each g, h, k, and l figure in Figures 5 to 8 are as follows:
The position of the data acquisition initiation signal indicates the appropriate method of processing the supplemental horizontal synchronization signal.

By the way, since the pattern V synchronization signal is detected and generated from the input composite synchronization signal, it may not be generated if the condition of the input signal is bad as described above.In this case, the V synchronization signal is supplementary V.
A synchronization signal is used, and the signal for starting data acquisition is also generated from the supplemental V synchronization signal.

The above points will be explained with reference to FIGS. 5 to 8 as follows. Figure 5 is a waveform diagram for explaining the operation near the V sync signal in the composite sync signal when switching from an odd field to an even field. An explanatory diagram of the case {6th
The same applies to figures a to d in Figs.
In addition, diagrams e to h in FIG. 5 are explanatory diagrams for the case where there is shrinkage due to skew in the composite synchronization signal {diagrams e to h in FIG. 6, which will be described later, are also the same}, and Figures 1 to 1 are explanatory diagrams in the case where the composite synchronization signal has an elongation due to skew (Figures 1 to 1 in Figure 6, which will be described later, are also the same).

FIG. 6 is a waveform diagram for explaining the operation in the portion where an even number field switches to an odd number field, and FIG. 7 is a waveform diagram for explaining the operation in a portion where the odd number field switches to an even number field.
Diagrams e to h in FIG. 7 are explanatory diagrams of the operation when a specific pattern of noise is mixed into the composite synchronization signal {diagrams e to h in FIG. 8, which will be described later, are also the same},
In addition, diagrams i to l in FIG. 7 are explanatory diagrams of operations when a synchronization signal is missing in a specific pattern from the composite synchronization signal {diagrams i to l in FIG. 8, which will be described later, are also the same}, and FIG. 8 is a waveform diagram for explaining the operation in the vicinity of the V synchronization signal when switching from an even field to an odd field.

In Figures 5 to 8, figures a, e, and i in each figure are composite synchronization signals, and figures b, f, and j in each figure are composite synchronization signals.
The figures show the generated horizontal synchronization signals, c, g, and K in each figure.
The figure shows a pattern V synchronization signal, and figures d, h, and l of each figure are supplementary V synchronization signals.

Each c, d, g, h in Fig. 5 to Fig. 8,
The pulses indicated by dotted lines in Figures K and l are pulses for preparing data acquisition, and these data acquisition start pulses are generated by the V synchronization signal (pattern V synchronization signal) output from terminal 8 in Figure 1. The PCM signal is generated a predetermined time after the data acquisition start pulse (or supplementary V synchronization signal), and the signal processing of the PCM signal is based on the horizontal synchronization signal that first appears after the data acquisition start pulse is generated. Data acquisition is started, and the data acquisition operation is stopped after counting the number of horizontal synchronization signals of a predetermined number {(number of control signal blocks 1) + (number of data words 245)}. Therefore, if the position of the data acquisition start pulse is shifted or the horizontal synchronization signal is incorrectly generated, the data arrangement and order will be out of order, resulting in abnormal noise. In each figure a of FIGS. 5 to 8, C indicates a control signal block, and 1, 2, . . . indicate data words.

In Fig. 5, Fig. e shows that a part of the composite synchronization signal is shrunk due to skew, and Fig. f shows the generation state of the horizontal synchronization signal in this case, and the pattern V synchronization signal The position of the V synchronization signal is shown in figure g, and the position of the supplementary V synchronization signal is shown in figure h. Note that in Figure e, the composite synchronization signal before the occurrence of skew is shifted to the right in the figure to facilitate comparison with the normal cases shown in Figures A to D.

When the composite synchronization signal is compressed due to skew, the generated horizontal synchronization signal becomes H/3 compared to the normal horizontal synchronization signal {Figure 5b}, as shown in Figure 5f. I will explain the fact that it shifts by 2. _The horizontal synchronization signal P ₁ in FIG. It turns out.

Next, an attempt is made to capture the equalization pulse indicated by _P3 , but it cannot be captured, and the second supplementary horizontal synchronization signal P _r2 is output. Then detect pulse P ₄ and pulse
When we measure the time up to P ₆ , it is exactly 1H, so pulse P ₆ is taken in, but since the second supplementary horizontal synchronization signal P _r21 has already been output slightly earlier, the falling edge of pulse 7 is taken in. A horizontal sync signal is output at this point. Figure 5 f generated in this way
Since the horizontal synchronization signal shown in the figure is delayed by H/2 compared to the horizontal synchronization signal shown in Figure 5b, normal synchronization occurs when the equalization pulse disappears after the vertical blanking period Naturally, the signal _P8 cannot be captured, and the first supplementary horizontal synchronizing signal P _r11 and the second supplementary horizontal synchronizing signal P _r22 are output.

Next, when pulse P ₉ is detected and the time until pulse P ₁₀ is measured while outputting the second supplementary horizontal synchronization signal P _r23 , the time width until pulse P ₁₀ is exactly 1H.
Since it is the time of , the pulse _P10 is taken in and the second supplementary horizontal synchronization signal _Pr24 synchronized with the pulse _P10 is output. After pulse _P11 , a horizontal synchronization signal synchronized with the horizontal synchronization signal of the composite synchronization signal is generated and output.

When the horizontal synchronization signal is generated in this way,
V output from the continuous output prevention circuit 5 in FIG.
If the synchronization signal is generated by the pattern V synchronization signal, the position of the data acquisition start pulse will be the same as in the normal case, but one extra horizontal synchronization signal will be generated after that point. If the V synchronization signal output from the continuous output prevention circuit 5 is generated by the supplementary V synchronization signal, the order of data acquisition will be out of order. Because the synchronization signal is delayed by H/2, the position of the data acquisition start pulse is output at a position delayed by H/2 compared to the normal case. Fortunately, in this case, the number of horizontal synchronization signals No deviation occurs.

Next, with reference to FIGS. 5I to 5I, a case will be described in which a part of the interval of the composite synchronization signal is elongated due to skew. Figure i is a waveform diagram of a composite synchronization signal where some signal intervals are elongated due to skew, diagram J is a waveform diagram showing the generation state of the horizontal synchronization signal in this case, and diagram K is a waveform diagram showing the generation state of the horizontal synchronization signal in this case. A supplementary V synchronization signal is shown in FIG. In Figure i, the composite synchronization signal before the occurrence of skew is shown slid to the left in order to facilitate comparison with the normal cases shown in Figures a to d.

If an elongation occurs in the composite synchronization signal due to skew, the generated horizontal synchronization signal is
This will be generated in the state shown in the figure, and this will be explained next.

The horizontal synchronizing signal P ₁ in FIG _. j Output as shown. Next, the equalization pulse P ₂ indicated by P ₂ in Figure i is detected and the second supplementary horizontal synchronization signal P _rj2 is output, and when the time until pulse P ₄ is measured, the pulse
Since the simultaneous width up to P ₄ is exactly 1H, the second supplementary horizontal synchronization signal P _rj21 synchronized with pulse P ₄
Output. Thereafter, horizontal synchronization signals synchronized with pulses P ₆ and P ₇ are output, but these generated horizontal synchronization signals are ahead of the normal horizontal synchronization signal by H/2. Then, after the vertical blanking period has passed and the equalization pulse disappears, horizontal synchronization is performed in the same way as in the case where skew exists in the composite synchronization signal as explained in Figures 5e to 5h. A signal is generated.

When the horizontal synchronization signal is generated as described above, if the V synchronization signal output from the continuous output prevention circuit 5 in FIG. 1 is generated by the pattern V synchronization signal, the data Although the position of the acquisition start pulse is the same as in the normal case, one extra horizontal synchronization signal is generated after that point, which causes an error in the order of data acquisition. If the V synchronization signal output from the continuous output prevention circuit 5 is generated by the supplementary V synchronization signal, the position of the data acquisition start pulse is The signal is output at a position H/2 ahead of the normal case, and even in this case, one extra horizontal synchronization signal is generated after that point, and the order of data acquisition is thrown out of order.

Figures 6a to 6 illustrate and explain problems when switching from an even field to an odd field.
In the case of figure l, as in the case of figure 5 mentioned above,
Although the horizontal synchronization signal is generated with a shift of H/2, the phenomenon of the data acquisition order being out of order due to the position of the data acquisition start pulse varies depending on the content of the skew. In FIG. 6, P _r1 indicates the first supplementary horizontal synchronizing signal, and P _r2 indicates the second supplementary horizontal synchronizing signal.

Next, a very special situation will be described in which a specific pattern of noise is mixed in the vicinity of the V synchronization signal, or a synchronization signal is dropped in a specific pattern.

First, in Figure 7 for the case of switching from an odd field to an even field, Figure e shows the waveform of the composite sync signal with a specific pattern of noise mixed in near the V sync signal in the composite sync signal. Figs. and f are waveform diagrams showing the generation status of the horizontal synchronization signal, g is the pattern V synchronization signal, and h
The figure shows the supplementary V synchronization signal.

If the horizontal _{synchronizing} signal _P1 in FIG.
is output, and then when the detection operation is started before the elapse of time (1H - △H) in an attempt to detect pulse P ₂ , if noise N ₁ is detected by chance, the second supplementary horizontal synchronization signal P While outputting _r2 ,
Furthermore, since the noise N ₂ located at approximately 1H intervals is detected, the second supplementary horizontal synchronization signal P _r21 synchronized with the noise is output. Then, as a matter of course, after about 1H has passed since the noise N ₂ , the pulse P ₄
cannot be detected, so when the first supplementary horizontal synchronizing signal P _r11 is output again and the detection operation is started before the elapse of the time (1H - △H), the pulse P ₅ happens to be detected.
, thereby detecting the second supplementary horizontal synchronization signal P _r
22 and detects the equalization pulse P ₆ shown by the pulse P ₆ at exactly 1H intervals, so from then on, as in the case due to the skew of elongation already mentioned in Fig. 5, compared to the normal case, A horizontal synchronization signal advanced by H/2 will be generated.

Next, in Figures i to l of Figure 7, Figure i shows a state in which the synchronization signal is dropped in a specific pattern near the V synchronization signal in the composite synchronization signal, and Figure J shows the horizontal synchronization signal at that time. It is a diagram showing a generation process. In this case, since pulse P ₁ in diagram i is missing and pulse P ₁ cannot be detected,
Output the first supplementary horizontal synchronization signal P _r1 , and then
Since pulse P ₂ is missing and pulse P ₂ cannot be detected, the second supplementary horizontal synchronization signal P _r2 is output.
Then, when pulse P ₃ is detected, while outputting the second supplementary horizontal synchronizing signal P _r21 , pulse P ₄ is output at exactly 1H intervals.
Detects the equalization pulse _P4 shown by and generates a second supplementary horizontal synchronization signal P _r22 synchronized with this equalization pulse _P4 .
Output. Thereafter, a horizontal synchronization signal shifted by H/2 is generated while being synchronized with the synchronization signal in Figure i.

By the way, in FIG. 7J, the second supplementary horizontal synchronization signal P _r22 synchronized with pulse P ₄ in FIG.
The second supplementary horizontal synchronization signal P _r outputted before it
Approximately H/2 interval for ₂₁ (H/2 to 5/8H)
Therefore, the H/2 pulse generation circuit 7 in FIG.
, the H/2 pulse is not generated. Therefore, the position where the supplementary V synchronization signal is generated is H/
2 delay, which results in the same result as in the case of shrinkage skew described above with respect to FIG.

Figures a to l of Figure 8 illustrate and explain the problems when switching from an even field to an odd field. Similarly, the generated horizontal synchronizing signal is shifted by H/2, and when the noise shown in Fig. 8 e to h is mixed, it is different from the case due to the elongation skew shown in Fig. 6 i to l. The same applies, and also, Fig. 8 i to l
In the case of synchronization signal loss due to noise as shown in the figure,
This is the same as in the case of shrinkage skew shown in FIGS. 6e to 6h. In addition, in Fig. 8, N is noise,
P ₁ and P ₂ are missing synchronization signals, P _r1 is a first supplementary horizontal synchronization signal, and P _r2 is a second supplementary horizontal synchronization signal.

As is clear from the above explanation, in the case of a horizontal synchronization signal generation circuit with the circuit configuration shown in Figure 3, there is a large skew in the vicinity of the vertical synchronization signal in the composite synchronization signal, or a specific pattern. If noise is mixed in or the synchronization signal is dropped, the order in which data is taken may be out of order, which may result in abnormal noise.

The present invention determines whether the composite synchronization signal is expanded or compressed due to skew or noise, and also determines whether the field is odd or even, and the control mode can be changed depending on the results of each determination. The present invention provides a horizontal synchronization signal control method that eliminates the above-mentioned conventional drawbacks by preventing the number of horizontal synchronization signals from being erroneously determined in the existing section. The contents will be explained in detail with reference to the attached drawings.

Due to skew or noise in the vicinity of the V sync signal in the composite sync signal, the position of the horizontal sync signal generated in the horizontal sync signal generation circuit deviates by H/2 from the predetermined position. As a result, the data acquisition order gets out of order, as explained with reference to Figures 5 to 8. However, in order to correctly regulate the data acquisition order, the generated horizontal synchronization signal , the processing of the second supplementary horizontal sync signal when the vertical blanking interval is completed, enters the supplement state, and then returns to the state synchronized with the horizontal sync signal in the input composite sync signal. It is necessary to do so.

Figure 9 shows the processing contents of the second supplementary horizontal synchronization signal described above. As for the judgment results, it is clear from the explanations in Figs. 5 to 8 that the processing contents are the same in the case of noise contamination or loss of synchronization signal as in the case of skew. Determination as to whether the expansion/contraction of the synchronization signal interval is due to noise or a lack of the synchronization signal can be made in the same manner as described later by a circuit for determining expansion/contraction of the horizontal synchronization signal interval due to skew.

Now, the difference between whether the horizontal sync signal interval has increased (or noise has been added) or has shortened (sync signal loss) is that the generated horizontal sync signal is This can be determined based on the generation status of the second supplementary horizontal synchronizing signal (the last second supplementary horizontal synchronizing signal) immediately before returning to a state of complete synchronization with the horizontal synchronizing signal among the synchronizing signals.

That is, when the horizontal synchronizing signal interval increases, the last second supplementary horizontal synchronizing signal is synchronized with the horizontal synchronizing signal in the input composite synchronizing signal, and when the horizontal synchronizing signal interval decreases, In this case, the last second supplementary horizontal sync signal is not synchronized with the horizontal sync signal in the input composite sync signal.

In FIGS. 3 and 4, the replenishment state of the horizontal synchronization signal is determined by the switching control signal 2 shown in FIG.
2a, the situation generating the final second complementary horizontal synchronization signal can be determined by the output 12 of the second gate 12 shown in FIG. 4k.
CNT1 when differential pulse 10a appears in a
This can be determined by determining the count value of 9.

Therefore, as a circuit arrangement for determining the expansion/contraction of the horizontal synchronizing signal interval by the expansion/contraction determination method as described above, a configuration example as shown by block J in FIG. 10 can be used. In FIG. 10, components corresponding to those in FIGS. 1 and 3 are given the same drawing symbols as those used in FIGS. 1 and 3.

Expansion/contraction determination circuit J indicated by block J in FIG.
are AND circuits 24 and 25, and a delay circuit 26 {this delay circuit 26 receives the determination reference signal 1 shown in FIG. 11d obtained by appropriately decoding the output of the CNT 19
This delay circuit uses the master clock CLKm as a clock signal. That is, the output 12 of the second gate 12
The differential pulse of a resets CNT19, so
A delay circuit 26 is used to temporarily hold the immediately preceding data, and is comprised of polarity inverting circuits 27, 28, and the like.

An output signal 22a from the switching control signal generating circuit 22 indicating whether or not the replenishment state is present is applied to the input of the polarity inverting circuit 28. Therefore, a pulse for determining elongation is generated at the output of the AND circuit 24, and a pulse for determining contraction is generated at the output of the AND circuit 25.

Next, a method for determining whether an odd number field or an even number field is determined will be explained. Various methods have been known for determining whether an odd field or an even field exists, but here, the determination pulse 7b output from the H/2 pulse generation circuit 7 shown in FIG. 11c, Odd and even fields are determined using the relationship with the pattern V synchronization signal shown in each of the diagrams c, g, and k in FIGS. 5 to 8.

That is, if the determination pulse 7b exists in the pattern V synchronization signal with a pulse width of H/2, it is an even field, and if the determination pulse 7b exists in the signal obtained by delaying the pattern V synchronization signal by H/2, it is an odd field. It is determined as follows. ODD and EVEN in the determination results of odd and even numbers in Figure 9
shows the determination result using the above-mentioned determination method, which is the opposite of the normal case. An example of the configuration of such an odd number/even number determination circuit is the first one.
This is indicated by block OEJ in Figure 0, and in block OEJ, 29 and 30 are AND circuits,
31 is a delay circuit. The delay circuit 31 is for delaying the pattern V synchronization signal 3a by H/2, and the delay operation is performed by supplying the H/2 pulse 7a as a clock input.

The AND circuit 29 outputs an odd field determination pulse, and the AND circuit 30 outputs an even field determination pulse.

Next, a description will be given of how the horizontal synchronizing signal 6a is processed based on the results of the expansion/contraction determination and the contents of the determination results of odd and even fields.
The processing described above is to enter the replenishment state after the vertical blanking period, and then to return to the state synchronized with the input composite synchronization signal by using the final second replenishment horizontal synchronization signal according to the determination result. remove or
The question is whether to output it as is. Therefore, since there is a time period of several hours to 10 hours from the time of judgment to the execution of processing, the judgment results are temporarily stored, and then the time of approximately H/2 shown in Figure 12a is used. The horizontal synchronization signal generated at the interval should be removed or output as is. In FIG. 10, 32 is a set/reset flip-flop (SR/FF32) that temporarily stores the determination results. It may also be reset by In this way, the final determination result required for processing is stored in the SR/FF 32.

Further, 34 is a circuit for generating a gate control signal 34a shown in FIG. 12b, and this circuit 3
4 consists of a counter and a decoder that are reset by the processed horizontal synchronizing signal and start counting the master clock CLKm, but in some cases, the H/2 pulse generation circuit 7 It is also possible to substitute.

35 is an AND circuit, and this AND circuit 35
is provided to prevent the horizontal synchronization signal that is not to be processed from being removed by the gate control signal 34a, and the delay circuit 36 is provided to prevent the horizontal synchronization signal that is not targeted for processing from being removed by the gate control signal 34a. The input signal shown in FIG.
The output is delayed according to the timing relationship shown in Figure F. This delay circuit 36 prevents the horizontal synchronizing signal immediately after the SR/FF 32 is set (determined to be removed) from being removed.

Gate control signal 34 obtained in this way
a and the output signal 36a from the delay circuit 36 are applied to the AND circuit 35, and the output signal 35a from the AND circuit 35 is given to the OR gate 33.
a (gate control signal 35a of OR gate 33) is
When a removal process is performed, it appears as shown in FIG. 12c, and when no removal is performed, it becomes 0 level.

As is clear from the above description, it is clear that a desired horizontal synchronization signal can be obtained with the circuit arrangement shown in FIG. Next, the deviation of the horizontal synchronization signal due to a certain pattern of noise can be prevented with a relatively simple circuit.
An example of the circuit configuration is shown in FIG. In Fig. 13, 37 is a VTR, and 38 is a
This is a data separation circuit for extracting digital signals from VTR playback signals. Further, 1, 2, and 6 correspond to the components with the same symbols in FIG.
Reference numerals 40 and 41 in FIG. 13 are low-pass filters, respectively. In FIG. Two low-pass filters 40 and 41 with a low-pass filter 41 provided in the signal transmission path.
Although it is shown that only one of the low-pass filters is used, in practice, only one of the low-pass filters may be used, and even in that case, the noise removal effect is very large.

In other words, noise becomes a problem when the noise is present in a specific pattern, that is, at approximately 1H intervals. By inserting a low-pass filter into the synchronization signal transmission path, a specific pattern of noise can be completely removed, and shifts in the horizontal synchronization signal due to noise can be effectively prevented.

As described above, in the horizontal synchronization signal control method of the present invention, even if skew, noise, or missing synchronization signals occur near the vertical synchronization signal in the composite synchronization signal, the expansion/contraction of the composite synchronization signal By determining whether the fields are odd or even, and controlling according to the results of the determination, it is possible to prevent the number of generated horizontal synchronization signals from becoming inconsistent. The occurrence of abnormal noise, which was a problem, was also completely prevented, and the above-mentioned conventional problems were successfully solved by the method of the present invention.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional V synchronization signal detection and protection circuit, Fig. 3 is a block diagram of a conventional horizontal synchronization signal generation circuit, Figs. FIG. 12 is a diagram for explaining the operation, FIG. 10 is a block diagram of one embodiment of the system of the present invention, and FIG. 13 is a block diagram of another embodiment of the same. 6...Horizontal synchronization signal generation circuit (horizontal synchronization signal detection protection circuit), 7...H/2 pulse generation circuit, J
...Expansion/contraction judgment circuit, OEJ...Odd number, even field judgment circuit, 32...SR/FF, 33...OR gate, 34...Gate control signal generation circuit, 35
...AND circuit, 36...delay circuit.

Claims (1)

[Claims] 1. A signal format that complies with the TV signal of the standard TV system by performing predetermined interleaving on a signal obtained by converting an analog signal into PCM and then mixing it with a composite synchronization signal that conforms to the scanning standard of the standard TV system. When recording and reproducing the PCM signal, the signal processing of the PCM signal is performed based on the signal obtained by synchronously separating the reproduced PCM signal in a signal format compliant with the standard TV signal. When detecting and protecting the synchronization signal synchronized with the TV horizontal synchronization signal required for Depending on the comparison result between the horizontal synchronization signal interval and a predetermined value at the time of returning to the synchronized state with the synchronization signal, and the result of determining whether it is an odd field or an even field,
A horizontal synchronization signal control method comprising means for controlling whether or not to remove the horizontal synchronization signal that first appears after the horizontal synchronization signal returns to a state synchronized with the horizontal synchronization signal in the reproduced TV signal. . 2. Both the transmission path of the signal obtained by synchronous separation from the PCM signal in the signal format compliant with the reproduced standard TV system TV signal and the transmission path of the signal subject to the above-mentioned synchronous separation, or either The horizontal synchronization signal control system according to claim 1, wherein one of the horizontal synchronization signal control systems is provided with low-pass filtering means.