JPH0144040B2 - - Google Patents

Info

Publication number
JPH0144040B2
JPH0144040B2 JP58239216A JP23921683A JPH0144040B2 JP H0144040 B2 JPH0144040 B2 JP H0144040B2 JP 58239216 A JP58239216 A JP 58239216A JP 23921683 A JP23921683 A JP 23921683A JP H0144040 B2 JPH0144040 B2 JP H0144040B2
Authority
JP
Japan
Prior art keywords
conductor
circuit board
marking
marking conductor
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58239216A
Other languages
Japanese (ja)
Other versions
JPS60130886A (en
Inventor
Haruji Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58239216A priority Critical patent/JPS60130886A/en
Publication of JPS60130886A publication Critical patent/JPS60130886A/en
Publication of JPH0144040B2 publication Critical patent/JPH0144040B2/ja
Granted legal-status Critical Current

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Landscapes

  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Structure Of Printed Boards (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子機器部品を量産する場合に用い
ることができるプリント基板あるいは混成集積回
路基板等の回路基板の組立方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for assembling a circuit board, such as a printed circuit board or a hybrid integrated circuit board, which can be used in the mass production of electronic device parts.

従来例の構成とその問題点 一般に、比較的小型の電子回路基板を組み立て
る場合は、基板材料費の引下げ、部品自動装着、
自動機の稼動率を高める等の目的で、第1図に示
すごとく、一枚の大型基板に小さい多数個の回路
基板を同時に形成し、組立て後に折つて割る等し
て分割し、完成する方式がとられる。
Conventional configurations and their problems In general, when assembling relatively small electronic circuit boards, it is necessary to reduce board material costs, automatically attach parts,
For the purpose of increasing the operating rate of automatic machines, etc., as shown in Figure 1, a method in which multiple small circuit boards are simultaneously formed on a single large board, and after assembly, it is divided into parts by folding, splitting, etc., to complete the process. is taken.

しかし、部品装着前に一個又はそれ以上の回路
基板が不良となつた場合には、全ての回路基板に
部品を装着すると部品材料費の増大となり、又自
動装着機の稼動率を下げるという問題点があつ
た。
However, if one or more circuit boards become defective before parts are installed, mounting the components on all circuit boards will increase component material costs and reduce the operating rate of the automatic mounting machine. It was hot.

このため、従来には、この不良になつた回路基
板に着色インキ等によつてマークをし、自動装着
機でこれを光学的に検出し、不良回路基板には部
品を装着しないという方式をとつていた。しかし
この方式では、設備が高価であり、又、ゴミ、外
光等の影響により不良基板を正確に検出できなく
なる等、信頼性が低かつた。
For this reason, the conventional method was to mark the defective circuit board with colored ink, detect this optically using an automatic placement machine, and then not place any components on the defective circuit board. It was on. However, in this method, the equipment is expensive, and the reliability is low because defective boards cannot be accurately detected due to the influence of dust, external light, etc.

発明の目的 本発明は、これらの従来の欠点を解消し、光学
式のものに比べて設備を安価に構成でき、しかも
信頼性の高い回路基板の組立方法を提供するもの
である。
OBJECTS OF THE INVENTION The present invention eliminates these conventional drawbacks, and provides a method for assembling a circuit board that allows equipment to be constructed at a lower cost than that of an optical type, and that is highly reliable.

発明の構成 本発明の回路基板の組立方法では、一方の面に
マーキング導体を備え、他の面に分離して第1の
導体を上記マーキング導体の一端と、第2の導体
を上記マーキング導体の他の端部とそれぞれ電気
的に接続するように構成した回路基板面上に形成
された抵抗体の抵抗値を検出して域外もしくは域
内値のいずれかの時上記マーキング導体をカツト
するようにし、上記マーキング導体の両端と接触
可能なピンを備え、マーキング導体両端の抵抗値
を検出して域外もしくは域内値のいづれかの時部
品の装着をスキツプするようにしており、これに
より、回路基板に部品を装着する前に回路基板の
良否を認別して不良回路基板に部品を装着しない
ようにした回路基板の組立方法で、回路基板の表
裏いづれかでも検出ができるようにしたものであ
る。
Structure of the Invention In the circuit board assembly method of the present invention, a marking conductor is provided on one surface, and the other surface is separated, and a first conductor is connected to one end of the marking conductor, and a second conductor is connected to one end of the marking conductor. Detecting the resistance value of a resistor formed on the surface of the circuit board configured to be electrically connected to the other end, and cutting the marking conductor when the resistance value is either outside the range or within the range, It is equipped with pins that can contact both ends of the marking conductor, detects the resistance value at both ends of the marking conductor, and skips mounting of components when the resistance value is either outside the range or within the range. This is a method of assembling a circuit board in which the quality of the circuit board is determined before mounting so that parts are not mounted on a defective circuit board, and it is possible to detect either the front or back of the circuit board.

実施例の説明 以下、本発明の一実施例を示す図面を参照して
説明する。
DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

まず、第1図に示すような大型基板1の各々の
回路基板2には不良検出用のマーキング導体3を
設ける。第2,3,4図にその詳細を示す。マー
キング導体3はスルーホール等の電気的接続手段
4及び5を介して裏面に設けられた第1の導体6
及び第2の導体7と電気的に導通されている。
First, a marking conductor 3 for defect detection is provided on each circuit board 2 of a large board 1 as shown in FIG. Details are shown in Figures 2, 3, and 4. The marking conductor 3 is connected to a first conductor 6 provided on the back side via electrical connection means 4 and 5 such as through holes.
and is electrically connected to the second conductor 7.

そして、いずれか一つの回路基板が不良と判定
された場合、混成集積回路においては印刷抵抗が
規格を逸脱したように場合等には、第5図に示す
ように、その回路基板のマーキング導体3を切断
する。混成集積回路においては、レーザー抵抗ト
リミング機等によるレーザー加工によつて切断す
る。
If one of the circuit boards is determined to be defective, such as when the printed resistance deviates from the standard in a hybrid integrated circuit, the marking conductor 3 of that circuit board should be removed as shown in Figure 5. cut. Hybrid integrated circuits are cut by laser processing using a laser resistance trimming machine or the like.

これを用い、第6,7図に示すように、後の工
程の部品装着機に取付けられた接触ピンを押し下
げて接触させ、このマーキング導体3の切断部8
の有無を抵抗計11にて検出する。このとき、不
良によりマーキング導体3が切断された回路基板
には、部品を装着せず、次の回路基板へスキツプ
して装着するように制御する。
Using this, as shown in FIGS. 6 and 7, the contact pin attached to the component mounting machine in the later process is pressed down and brought into contact with the cutting part 8 of the marking conductor 3.
The presence or absence of is detected by the resistance meter 11. At this time, control is performed so that components are not mounted on a circuit board whose marking conductor 3 has been cut due to a defect, but are skipped to the next circuit board for mounting.

また、回路基板が両面に部品を装着するもので
ある場合においても、第7図のごとく、同様の接
触ピンにて検出することが可能である。
Furthermore, even if the circuit board has components mounted on both sides, it is possible to detect it using similar contact pins as shown in FIG.

発明の効果 以上のように、本発明によれば、多数個の回路
基板を組立てる大型基板等における不良回路基板
の検出をマーキング導体のトリミング抵抗用のレ
ーザー加工機による切断の有無を電気的に行うこ
とにより、従来例の光学式のものに対して既存の
レーザー加工機を用いて設備として安価な設備
で、電気的な判別による高い信頼性で行うことが
できる。特に、両面部品装着の基板においても、
同一の方式でこれを実現することができ、きわめ
て有効なものである。
Effects of the Invention As described above, according to the present invention, a defective circuit board on a large board, etc., on which a large number of circuit boards are assembled, is electrically detected by checking whether or not the marking conductor is cut by a laser processing machine for trimming the resistor. Therefore, compared to the conventional optical type, the processing can be performed using an existing laser processing machine with inexpensive equipment and with high reliability based on electrical discrimination. In particular, even on boards with double-sided component mounting,
This can be achieved using the same method and is extremely effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路基板の組立方
法により組立てる基板を示す平面図、第2図はそ
の同マーキング導体を示す拡大平面図、第3図は
その断面図、第4図はその裏面図、第5図はその
不良時のマーキング導体の切断状態を示す平面
図、第6図、第7図はその検出部の一例を示す一
部断面側面図である。 1……大型基板、2……回路基板、3……マー
キング導体、4,5……電気的接続手段、6……
第1の導体、7……第2の導体、8……切断部、
9,10……接触ピン、11……抵抗計。
FIG. 1 is a plan view showing a circuit board assembled by the circuit board assembly method according to an embodiment of the present invention, FIG. 2 is an enlarged plan view showing the same marking conductor, FIG. 3 is a cross-sectional view thereof, and FIG. FIG. 5 is a plan view showing the cutting state of the marking conductor at the time of failure, and FIGS. 6 and 7 are partially sectional side views showing an example of the detection section. 1...Large board, 2...Circuit board, 3...Marking conductor, 4, 5...Electrical connection means, 6...
First conductor, 7... Second conductor, 8... Cutting part,
9, 10... Contact pin, 11... Resistance meter.

Claims (1)

【特許請求の範囲】[Claims] 1 一方の面にマーキング導体を備え、他の面に
分離して第1の導体を上記マーキング導体の一端
と、第2の導体を上記マーキング導体の他の端部
と、それぞれ電気的に接続するように構成した混
成集積回路基板面上に形成された印刷抵抗体の抵
抗値を検出して域外もしくは域内値のいずれかの
とき上記マーキング導体をレーザー抵抗トリミン
グ機によるレーザー加工によつて切断し、上記マ
ーキング導体の両端にマーキング導体抵抗検出用
のピンを接触させ、マーキング導体両端の抵抗値
を検出して域外もしくは域内値のいずれかのとき
部品の装着をスキツプするようにした回路基板の
組立方法。
1 A marking conductor is provided on one surface, and the first conductor is separated on the other surface and electrically connected to one end of the marking conductor, and the second conductor is electrically connected to the other end of the marking conductor. detecting the resistance value of the printed resistor formed on the surface of the hybrid integrated circuit board configured as above, and cutting the marking conductor by laser processing using a laser resistance trimming machine when the resistance value is either outside the range or within the range; A method for assembling a circuit board in which pins for detecting resistance of the marking conductor are brought into contact with both ends of the marking conductor, the resistance value at both ends of the marking conductor is detected, and component installation is skipped when the resistance value is either outside the range or within the range. .
JP58239216A 1983-12-19 1983-12-19 Method of assembling circuit board Granted JPS60130886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58239216A JPS60130886A (en) 1983-12-19 1983-12-19 Method of assembling circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58239216A JPS60130886A (en) 1983-12-19 1983-12-19 Method of assembling circuit board

Publications (2)

Publication Number Publication Date
JPS60130886A JPS60130886A (en) 1985-07-12
JPH0144040B2 true JPH0144040B2 (en) 1989-09-25

Family

ID=17041467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58239216A Granted JPS60130886A (en) 1983-12-19 1983-12-19 Method of assembling circuit board

Country Status (1)

Country Link
JP (1) JPS60130886A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7261952B2 (en) * 2019-02-06 2023-04-21 パナソニックIpマネジメント株式会社 Component mounting system and component mounting method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340457B2 (en) * 1973-04-13 1978-10-27
JPS5448077A (en) * 1977-09-22 1979-04-16 Tokyo Shibaura Electric Co Method of soldering parts to be added later

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56639Y2 (en) * 1976-09-13 1981-01-09

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340457B2 (en) * 1973-04-13 1978-10-27
JPS5448077A (en) * 1977-09-22 1979-04-16 Tokyo Shibaura Electric Co Method of soldering parts to be added later

Also Published As

Publication number Publication date
JPS60130886A (en) 1985-07-12

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