JPS628549A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS628549A JPS628549A JP60147220A JP14722085A JPS628549A JP S628549 A JPS628549 A JP S628549A JP 60147220 A JP60147220 A JP 60147220A JP 14722085 A JP14722085 A JP 14722085A JP S628549 A JPS628549 A JP S628549A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- dummy resistor
- dummy
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
この発明は混成集積回路に関し、さらに詳細にいえば、
自動検査ラインによる良否の自動選別を確実に行なうこ
とができる混成集積回路に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a hybrid integrated circuit, and more specifically,
The present invention relates to a hybrid integrated circuit that can be reliably automatically screened for pass/fail by an automatic inspection line.
〈従来の技術〉
従来から混成集積回路としては、第２図に示すように、
基板（１月の上に能動素子、受動素子等からなる集積回
路（１２）を搭載し、さらに基板（１１）の周縁部に形
成した一対の電極（１３）（１３）の間にダミー抵抗（
１４）を設けた構成が採用されている。<Conventional technology> Conventionally, as a hybrid integrated circuit, as shown in Fig. 2,
An integrated circuit (12) consisting of active elements, passive elements, etc. is mounted on a substrate (1), and a dummy resistor (12) is mounted between a pair of electrodes (13) formed on the periphery of the substrate (11).
14) is adopted.
そして、上記構成の混成集積回路では、基板（１１）の
上に集積回路を構成する回路部品を実装した後、素子の
ばらつきを補償するために、直流電流、信号投入時の諸
特性の検査を行ない、回路中の抵抗、コンデン９のレー
ザトリミングを行なうようにしている。また、この場合
に、混成集積回路の良否の判別を行なうために、マーキ
ングとしてダミー抵抗（１４）の切断を行なうようにし
ている。In the hybrid integrated circuit having the above configuration, after the circuit components constituting the integrated circuit are mounted on the substrate (11), in order to compensate for variations in the elements, various characteristics are tested when DC current and signals are applied. The resistor and capacitor 9 in the circuit are then laser trimmed. Further, in this case, in order to determine whether the hybrid integrated circuit is good or bad, the dummy resistor (14) is cut off as a marking.
〈発明が解決しようとする問題点〉
上記の構成の混成集積回路であれば、上記工程における
良否の判別を行なわず、さらに別の工程においてマーキ
ングを施し、良否の判別を行なうことが困難であるとい
う問題がある。即ち、従来の混成集積回路においては、
ダミー抵抗（１４）を切断した状態で、両電極（１３）
（１３）の間の抵抗値等を測定することにより、良否
の判別を行なうようにしているので、混成集積回路をモ
ールドした場合、或はケーシングに組込んだ場合等にお
いて混成集積回路の特性が変化することがあるにも拘わ
らず、マーキングとしてダミー抵抗（１４）の切断を行
なうことが困難であり、また、不良品をモールドし、或
はケーシングに組込んでしまった後に良否の自動判別を
行なうことは極めて困難である。<Problems to be Solved by the Invention> If the hybrid integrated circuit has the above configuration, it is difficult to judge whether it is good or bad because it is not judged whether it is good or bad in the above process and marking is applied in another process. There is a problem. That is, in the conventional hybrid integrated circuit,
Both electrodes (13) with the dummy resistor (14) cut off.
Since the quality of the hybrid integrated circuit is determined by measuring the resistance value etc. between Even though the dummy resistor (14) may change, it is difficult to cut it as a marking, and it is difficult to automatically determine whether it is good or bad after molding a defective product or incorporating it into a casing. It is extremely difficult to do so.
この発明は上記の問題点に鑑みてなされた−ものであり
、マーキングとしてのダミー抵抗の切断を高速で行なう
ことができ、しかも集積回路の部品を実装した後の完成
、未完成を問わず良否の自動判別を行なうことができる
混成集積回路を提供することを目的としている。This invention was made in view of the above-mentioned problems, and it is possible to cut dummy resistors as markings at high speed, and it is also possible to cut dummy resistors as markings at high speed, and also to detect defects regardless of whether the integrated circuit parts are completed or unfinished after being mounted. The object of the present invention is to provide a hybrid integrated circuit capable of automatically determining whether the
〈問題点を解決するための手段〉
上記の目的を達成するための、この発明の混成集積回路
は、能動素子、受動素子等からなる集積回路を搭載した
基板の所定位置に少なくとも電源供給用のリードピンと
グランド用のリードピンとを取付けているとともに、上
記各リードピンと集積回路との間を電気的に接続する導
体ラインを基板上に設け、さらに上記集積回路の電源−
グランド間抵抗より小さい抵抗値を有するダミー抵抗を
、トリミング可能に、かつ上記両リードピン間を直接電
気的に接続する状態で設けている。<Means for Solving the Problems> In order to achieve the above object, the hybrid integrated circuit of the present invention has at least a power supply circuit installed at a predetermined position of a substrate on which an integrated circuit consisting of active elements, passive elements, etc. is mounted. In addition to mounting lead pins and grounding lead pins, a conductor line is provided on the board to electrically connect each of the lead pins and the integrated circuit, and a power source for the integrated circuit is provided.
A dummy resistor having a resistance value smaller than the ground resistance is provided so as to be trimmable and directly electrically connected between both the lead pins.
但し、上記ダミー抵抗としては、混成集積回路のケーシ
ング上に設けられているものであってもよく、また、複
数個設けられていてもよい。However, the above dummy resistor may be provided on the casing of the hybrid integrated circuit, or a plurality of dummy resistors may be provided.
〈作用〉
上記の構成の混成集積回路であれば、電源供給用のリー
ドピンとグランド用のリードピンとの間における抵抗、
直流電流等を測定することにより、混成集積回路の良否
を判別することができ、良品であると判別された場合に
は、ダミー抵抗をトリミングすることにより、混成集積
回路を正常動作できる状態にするとともに、良品である
ことが目視判断できるようにすることができる。<Function> In the hybrid integrated circuit with the above configuration, the resistance between the power supply lead pin and the ground lead pin,
By measuring DC current, etc., it is possible to determine whether the hybrid integrated circuit is good or bad. If it is determined to be good, the hybrid integrated circuit is returned to a state where it can operate normally by trimming the dummy resistor. At the same time, it is possible to visually determine whether the product is a good product.
また、上記ダミー抵抗が混成集積回路のケーシング上に
設けられているものであれば、ケーシングに組込んだ状
態での判別結果に基いて簡単にマーキングとしてのダミ
ー抵抗の切断を行なうことができる。さらには、上記ダ
ミー抵抗が複数個設けられているものであれば、複数箇
所での検査を行ない、各検査工程に対応させてマーキン
グとしてのダミー抵抗の切断を行なうことができる。Further, if the dummy resistor is provided on the casing of the hybrid integrated circuit, the dummy resistor can be easily cut off as a marking based on the determination result while it is assembled in the casing. Furthermore, if a plurality of dummy resistors are provided, inspection can be performed at a plurality of locations, and the dummy resistors can be cut as markings in accordance with each inspection process.
〈実施例〉 以下、実施例を示す添付図面によって詳細に説明する。<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.
第１図はこの発明の混成集積回路の一実施例を示す斜視
図である。FIG. 1 is a perspective view showing an embodiment of the hybrid integrated circuit of the present invention.
基板（１）の所定位置に電源供給用のり−ドビン（２）
、およびグランド用のり−ドピン（３）を取付けている
とともに、能動素子、受動素子等からなる集積回路（４
）を搭載しており、さらに上記各リードピン（２）（３
）と集積回路（４）との間を電気的に接続する導体パッ
ド（５） （６１を形成している。そして、上記導体パ
ッド（５） （６）の間にダミー抵抗（７）が設けられ
ている。即ち、ダミー抵抗（７）は、上記集積回路（４
）と並列に接続された状態であり、ダミー抵抗（７）の
抵抗値は、上記集積回路（４）の電源−グランド間抵抗
より小さい抵抗値に設定されている。尚、上記ダミー抵
抗（７）は、基板（１）に直接形成されていてもよく、
図示しないケーシングの上に形成してもよい。Attach the power supply glue (2) to the specified position on the board (1).
, and a grounding pin (3), as well as an integrated circuit (4) consisting of active elements, passive elements, etc.
), and each of the above lead pins (2) (3).
) and the integrated circuit (4), forming a conductor pad (5) (61).A dummy resistor (7) is provided between the conductor pads (5) and (6). That is, the dummy resistor (7) is connected to the integrated circuit (4).
), and the resistance value of the dummy resistor (7) is set to be smaller than the power supply-ground resistance of the integrated circuit (4). Note that the dummy resistor (7) may be formed directly on the substrate (1),
It may also be formed on a casing (not shown).
以上の構成であれば、両リードピン（２） （３）の間
の抵抗値、直流電流等を測定することにより、簡単に混
成集積回路の良否を判別することができるので、良品で
あると判別された混成集積回路に対してのみ、トリミン
グとしてのダミー抵抗（７）の切断を行なって、混成集
積回路を正常動作可能な状態とし、しかもダミー抵抗（
刀の切断を目視判断可能なように行なうことにより、−
見して直ちに混成集積回路の良否を確認することができ
る状態とずることができる。With the above configuration, it is possible to easily determine whether the hybrid integrated circuit is good or bad by measuring the resistance value, DC current, etc. between both lead pins (2) and (3), so it is possible to determine whether it is a good product. The dummy resistor (7) is trimmed only for the hybrid integrated circuit that has been removed so that the hybrid integrated circuit can operate normally, and the dummy resistor (7) is
By making the cut with the sword so that it can be visually judged, -
This makes it possible to immediately check the quality of the hybrid integrated circuit by looking at it.
したがって、自動的に良品と不良品との選別を簡単に行
なうことができることになる。Therefore, it becomes possible to automatically and easily sort out good products and defective products.
また、ダミー抵抗（７）をケーシングの上に設けた場合
には、混成集積回路をケーシングに組込んだ状態におけ
る判別結果に基いて簡単にマーキングとしてのダミー抵
抗（′７）の切断を行なうことができる。In addition, when the dummy resistor (7) is provided on the casing, the dummy resistor ('7) can be easily cut off as a marking based on the discrimination result when the hybrid integrated circuit is assembled in the casing. I can do it.
さらに、ダミー抵抗（刀を複数個設けた場合には、複数
箇所での良否の判別に対応させて選択的に何れかのダミ
ー抵抗（力の切断を行なうことができる。Furthermore, if a plurality of dummy resistors (swords) are provided, it is possible to selectively cut off the force of any one of the dummy resistors (force) in accordance with the determination of pass/fail at multiple locations.
〈発明の効果〉
以上のようにこの発明は、工程の如何を問わず簡単に良
否の判別を行なうことができるとともに、マーキングを
も簡単に行なうことができるという特有の効果を奏する
。<Effects of the Invention> As described above, the present invention has the unique effect that it is possible to easily determine whether the product is good or bad regardless of the process, and it is also possible to easily mark the product.
第１図は混成集積回路の一実施例を示す斜視図、第２図
は従来例を示す斜視図。
（１）・・・基板、（２）・・・電源供給用のリードピ
ン、（３）・・・グランド用のリードピン、（４）・・
・集積回路、（５１，［６）・・・導体パッド、（７）
・・・ダミー抵抗
特許出願人 住友電気工業株式会社
代 理 人 弁理士 亀 井 弘 勝
（ばか２名）
第１図
第２図FIG. 1 is a perspective view showing an embodiment of a hybrid integrated circuit, and FIG. 2 is a perspective view showing a conventional example. (1)... Board, (2)... Lead pin for power supply, (3)... Lead pin for ground, (4)...
・Integrated circuit, (51, [6)...Conductor pad, (7)
... Dummy resistance patent applicant Sumitomo Electric Industries Co., Ltd. Representative Patent attorney Hiroshi Kamei (two idiots) Figure 1 Figure 2
Claims (1)
基板の所定位置に少なくとも電源供給用のリードピンと
グランド用のリードピンとを取付けているとともに、上
記各リードピンと集積回路との間を電気的に接続する導
体ラインを基板上に設け、さらに上記集積回路の電源−
グランド間抵抗より小さい抵抗値を有するダミー抵抗を
、トリミング可能に、かつ上記両リードピン間を直接電
気的に接続する状態で設けたことを特徴とする混成集積
回路。 ２、ダミー抵抗が混成集積回路のケーシング上に設けら
れている上記特許請求の範囲第１項記載の混成集積回路
。 ３、ダミー抵抗が複数個設けられている上記特許請求の
範囲第１項記載の混成集積回路。[Scope of Claims] 1. At least lead pins for power supply and lead pins for grounding are attached to predetermined positions of a substrate on which an integrated circuit consisting of active elements, passive elements, etc. is mounted, and each of the above lead pins and the integrated circuit are mounted. A conductor line is provided on the board for electrical connection between the integrated circuit and the integrated circuit.
1. A hybrid integrated circuit characterized in that a dummy resistor having a resistance value smaller than a ground resistance is provided in a trimmable manner and directly electrically connected between both the lead pins. 2. The hybrid integrated circuit according to claim 1, wherein the dummy resistor is provided on the casing of the hybrid integrated circuit. 3. The hybrid integrated circuit according to claim 1, wherein a plurality of dummy resistors are provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60147220A JPS628549A (en) | 1985-07-04 | 1985-07-04 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60147220A JPS628549A (en) | 1985-07-04 | 1985-07-04 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628549A true JPS628549A (en) | 1987-01-16 |
Family
ID=15425285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60147220A Pending JPS628549A (en) | 1985-07-04 | 1985-07-04 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628549A (en) |
-
1985
- 1985-07-04 JP JP60147220A patent/JPS628549A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3852073T2 (en) | Custom printed circuit. | |
| JPS628549A (en) | Hybrid integrated circuit | |
| US5708370A (en) | Depth sensor which detects grinding depth by means of change and resistance of resistor also ground during grinding | |
| CA2232963A1 (en) | Measuring method for detecting a short-circuit between the turns of a coil integrated on a chip, and integrated circuit structure adapted to such a measuring method | |
| JPS58172561A (en) | Inspection of printed circuit board and checker jig | |
| JPH05335117A (en) | Chip network resistor | |
| JPH08250897A (en) | Mounter with electric characteristic inspecting function | |
| JPH0144040B2 (en) | ||
| JP2002110268A (en) | Method of forming shunt resistor pattern for printed circuit board and method of fitting shunt resistor to printed circuit board | |
| JP2752942B2 (en) | IC evaluation board and IC evaluation method | |
| JPH0648898Y2 (en) | Printed wiring board | |
| JPH07218582A (en) | Connection defect detecting apparatus for ic pin | |
| KR920000400Y1 (en) | The detecting probe card of semiconductor i.c. | |
| JPS6222854Y2 (en) | ||
| JPH0611462Y2 (en) | Contact probe for board inspection | |
| JPH043831B2 (en) | ||
| JPH01211876A (en) | Connecting structure for board | |
| JPH0315765A (en) | Test board | |
| JPS634922B2 (en) | ||
| KR100663166B1 (en) | Flat type vibration motor and making method for circuit thereof | |
| JPH0961494A (en) | Pattern for testing printed circuit board | |
| JPH07202375A (en) | Manufacture of thick-film circuit board | |
| JPS61212779A (en) | Confirmation of accuracy of measuring system for trimming apparatus | |
| JPH1065301A (en) | Printed board with pattern for checking | |
| JPH04225545A (en) | Surface mounting type integrated circuit |