JPS6222854Y2 - - Google Patents

Info

Publication number
JPS6222854Y2
JPS6222854Y2 JP18925682U JP18925682U JPS6222854Y2 JP S6222854 Y2 JPS6222854 Y2 JP S6222854Y2 JP 18925682 U JP18925682 U JP 18925682U JP 18925682 U JP18925682 U JP 18925682U JP S6222854 Y2 JPS6222854 Y2 JP S6222854Y2
Authority
JP
Japan
Prior art keywords
electronic circuit
terminal
mounting
case
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18925682U
Other languages
Japanese (ja)
Other versions
JPS5992869U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18925682U priority Critical patent/JPS5992869U/en
Publication of JPS5992869U publication Critical patent/JPS5992869U/en
Application granted granted Critical
Publication of JPS6222854Y2 publication Critical patent/JPS6222854Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 〔考案の技術分野〕 本考案はチエツク端子を有する電子回路を備え
た電子回路装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electronic circuit device including an electronic circuit having a check terminal.

〔考案の技術的背景〕[Technical background of the invention]

従来より、IC等の電子回路を備えた電子回路
装置においては、電子回路を絶縁基板の導体パタ
ーンに接続した後電子回路のチエツク端子にジヤ
ンプ線を接続してその電子回路にプログラムされ
たテストモードを実行させ、これが正常に実行さ
れた場合に電子回路が正常としてチエツクを完了
し、前述のジヤンプ線を切断して絶縁基板をケー
スに組込むようにしている。
Conventionally, in electronic circuit devices equipped with electronic circuits such as ICs, a test mode is programmed into the electronic circuit by connecting the electronic circuit to a conductor pattern on an insulating substrate and then connecting a jump wire to the check terminal of the electronic circuit. If this is executed normally, the electronic circuit is judged to be normal and the check is completed, the aforementioned jump wire is cut and the insulating substrate is assembled into the case.

〔背景技術の問題点〕[Problems with background technology]

従来の構成では、テストモードのチエツク後は
ジヤンプ線を切断する必要があるので作業が面倒
であり、又、絶縁基板のケースへの組立て後に故
障等で再チエツクする必要のある場合には絶縁基
板をケースから取外した後電子回路のチエツク端
子に再びジヤンプ線を接続する必要があるのでや
はり作業が面倒であつた。
In the conventional configuration, it is necessary to cut the jump wire after checking in the test mode, which is cumbersome, and if it is necessary to check again due to a failure etc. after assembling the insulating board to the case, the insulating board After removing it from the case, it was necessary to reconnect the jump wire to the check terminal of the electronic circuit, which was still a tedious task.

〔考案の目的〕[Purpose of invention]

本考案は上記事情に鑑みてなされたもので、そ
の目的は、テストモードのチエツク及び再チエツ
クの作業が極めて簡単な電子回路装置を提供する
にある。
The present invention has been made in view of the above circumstances, and its purpose is to provide an electronic circuit device in which checking and re-checking of the test mode is extremely easy.

〔考案の概要〕[Summary of the idea]

本考案は、複数個の取付孔の内の一つたる第1
の取付孔が導体パターンを介して直流電源の負端
子に接続された絶縁基板を設け、この絶縁基板に
チエツク端子が導体パターンを介して前記複数個
の取付孔の内の他の一つたる第2の取付孔に接続
された電子回路を設け、この電子回路のチエツク
端子と前記直流電源の正端子との間に抵抗器を接
続し、そして、前記絶縁基板が前記複数個の取付
孔を介して取付ねじにより取付けられる金属製の
ケースを設ける構成とし、絶縁基板をケースに取
付ける前の電子回路のチエツク端子はハイレベル
となり、絶縁基板のケースへの取付時には該チエ
ツク端子はロウレベルとなるようにしたものであ
る。
In the present invention, the first mounting hole is one of the plurality of mounting holes.
An insulating board is provided, the mounting hole of which is connected to the negative terminal of the DC power supply through a conductor pattern, and a check terminal is connected to the other one of the plurality of mounting holes through the conductor pattern to this insulating board. An electronic circuit connected to the second mounting hole is provided, a resistor is connected between the check terminal of the electronic circuit and the positive terminal of the DC power supply, and the insulating substrate is connected to the plurality of mounting holes. The structure includes a metal case that can be mounted with mounting screws, and the check terminal of the electronic circuit is at high level before the insulating board is attached to the case, and the check terminal is at low level when the insulating board is attached to the case. This is what I did.

〔考案の実施例〕[Example of idea]

以下本考案の一実施例につき図面を参照して説
明する。
An embodiment of the present invention will be described below with reference to the drawings.

1は絶縁基板たるプリント基板であり、これに
は多数の導体パターンが形成されている。又、こ
のプリント基板1には複数個の取付孔(2及び3
の二個のみ図示)が形成されていて、その一つの
取付孔たる第1の取付孔2は導体パターン4を介
して直流電源5の負端子に接続されている。6は
電子回路たるCPUであり、その多数の端子は前
記多数の導体パターンに接続されている。又、こ
のCPU6の負電源入力端子6aは導体パターン
7を介して導体パターン4従つて直流電源5の負
端子に接続され、正電源入力端子6bは導体パタ
ーン8を介して直流電源5の正端子に接続されて
いる。そして、CPU6のチエツク端子6cは導
体パターン9を介して前記複数個の取付孔の内の
他の一つの取付孔たる第2の取付孔3に接続され
ている。10は抵抗器であり、その一端はCPU
6のチエツク端子6cに接続され、他端は直流電
源5の正端子に接続されている。11は金属製の
ケースであり、これには前記プリント基板1の複
数個の取付孔に対応して複数個のねじ止め孔(取
付孔2及び3に対応するねじ止め孔12及び13
のみ図示)が形成されている。而して、取付ねじ
14,15をプリント基板1の取付孔2,3に挿
通し円筒状のスペーサ部材16,17に挿通した
後ケース11のねじ止め孔12,13に螺挿する
とともに、他の取付ねじもプリント基板1の他の
取付孔に挿通し他のスペーサ部材に挿通した後ケ
ース11の他のねじ止め孔(以上いずれも図示せ
ず)に螺挿することによつて、プリント基板1が
ケース11に取付けて組立てられるようになつて
いる。
Reference numeral 1 denotes a printed circuit board which is an insulating substrate, on which a large number of conductor patterns are formed. Moreover, this printed circuit board 1 has a plurality of mounting holes (2 and 3).
(only two of them are shown) are formed, and one of the mounting holes, the first mounting hole 2, is connected to the negative terminal of the DC power supply 5 via the conductor pattern 4. 6 is a CPU which is an electronic circuit, and its many terminals are connected to the aforementioned many conductor patterns. Further, the negative power input terminal 6a of this CPU 6 is connected to the conductor pattern 4 and hence the negative terminal of the DC power supply 5 via the conductor pattern 7, and the positive power input terminal 6b is connected to the positive terminal of the DC power supply 5 through the conductor pattern 8. It is connected to the. A check terminal 6c of the CPU 6 is connected to a second mounting hole 3, which is another one of the plurality of mounting holes, via a conductive pattern 9. 10 is a resistor, one end of which is connected to the CPU
6, and the other end is connected to the positive terminal of the DC power supply 5. Reference numeral 11 denotes a metal case, which has a plurality of screw holes corresponding to the plurality of mounting holes of the printed circuit board 1 (screw holes 12 and 13 corresponding to the mounting holes 2 and 3).
(only shown) is formed. Then, the mounting screws 14 and 15 are inserted into the mounting holes 2 and 3 of the printed circuit board 1 and inserted into the cylindrical spacer members 16 and 17, and then screwed into the screw holes 12 and 13 of the case 11, and the other screws are inserted. The mounting screws are also inserted into other mounting holes of the printed circuit board 1, inserted into other spacer members, and then screwed into other screw holes (none of which are shown) of the case 11, so that the printed circuit board can be fixed. 1 is attached to a case 11 and assembled.

次に、本実施例の作用につき説明する。 Next, the operation of this embodiment will be explained.

プリント基板1をケース11に取付ける前に
CPU6のチエツクを行なう場合には、第2の取
付孔3は電気的に開放状態にあるので、CPU6
のチエツク端子6cは直流電源5により抵抗器1
0を介してハイレベルとなり、これによつて、
CPU6のテストモードが実行されて良,不良の
チエツクが行なわれる。
Before attaching the printed circuit board 1 to the case 11
When checking the CPU 6, the second mounting hole 3 is electrically open, so the CPU 6
The check terminal 6c is connected to the resistor 1 by the DC power supply 5.
becomes high level through 0, thereby
The test mode of the CPU 6 is executed to check whether it is good or bad.

このような、CPU6のテストモードのチエツ
クの終了後プリント基板1をケース11に取付け
ると、CPU6のチエツク端子6cは導体パター
ン9,取付ねじ15,ケース11、取付ねじ14
及び導体パターン4を介して直流電源5の負端子
に接続されて該チエツク端子6cはロウレベルと
なるものであり、これによつて、CPU6は通常
モードを実行することになる。
When the printed circuit board 1 is attached to the case 11 after completing the check in the test mode of the CPU 6, the check terminal 6c of the CPU 6 is connected to the conductor pattern 9, the mounting screw 15, the case 11, and the mounting screw 14.
The check terminal 6c is connected to the negative terminal of the DC power source 5 via the conductor pattern 4 and the check terminal 6c becomes a low level, thereby causing the CPU 6 to execute the normal mode.

一方、プリント基板1をケース11に取付けて
組立てた後にCPU6の再チエツクを行なう場合
には、取付ねじ15をケース11から取外すと、
取付孔3従つて導体パターン9とケース11との
電気的接続がしや断されることにより直流電源2
の正電位たるハイレベルが抵抗器10を介して
CPU6のチエツク端子6cに与えられるように
なり、CPU6は再びテストモードを実行するこ
とになる。
On the other hand, if you want to recheck the CPU 6 after installing and assembling the printed circuit board 1 in the case 11, remove the mounting screws 15 from the case 11.
When the electrical connection between the mounting hole 3 and the conductor pattern 9 and the case 11 is quickly cut off, the DC power supply 2
The high level, which is the positive potential of
The signal is now applied to the check terminal 6c of the CPU 6, and the CPU 6 executes the test mode again.

尚、本考案は上記し且つ図面に示す実施例にの
み限定されるものではなく、要旨を逸脱しない範
囲内で適宜変形して実施し得る。
It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but may be implemented with appropriate modifications within the scope of the gist.

〔考案の効果〕[Effect of idea]

本考案は以上説明した実施例から明らかなよう
に、複数個の取付孔の内の一つたる第1の取付孔
が導体パターンを介して直流電源の負端子に接続
された絶縁基板を設け、この絶縁基板の多数の導
体パターンに接続されチエツク端子が導体パター
ンを介して前記複数個の取付孔の内の他の一つた
る第2の取付孔に接続された電子回路を設け、こ
の電子回路のチエツク端子と前記直流電源の正端
子との間に抵抗器を接続し、そして、前記絶縁基
板が前記複数個の取付孔を介して取付ねじにより
取付けられる金属製のケースを設けるようにした
ので、絶縁基板をケースに取付ける前には直流電
源のハイレベルが抵抗器を介して電子回路のチエ
ツク端子に与えられることから従来とは異なりジ
ヤンプ線をチエツク端子に接続しなくてもテスト
モードを実行させることができ、又、絶縁基板を
ケースに取付ねじにより取付けることにより自動
的に電子回路のチエツク端子がロウレベルとなつ
て従来とは異なりジヤンプ線を切断する必要がな
く、従つて、電子回路のチエツク作業が極めて簡
単になり、更に、絶縁基板をケースに取付けて組
立てた後に前記電子回路を再チエツクする場合に
は、第2の取付孔に対応する取付ねじをケースか
ら取外すことにより電子回路のテストモードを実
行させることができ、従つて、従来とは異なり絶
縁基板をケースから取外した後電子回路のチエツ
ク端子にジヤンプ線を再接続するというような必
要がなくて、再チエツクの作業も極めて簡単にな
る等の実用的効果を奏するものである。
As is clear from the embodiments described above, the present invention provides an insulating substrate in which the first mounting hole, which is one of the plurality of mounting holes, is connected to the negative terminal of the DC power supply via a conductive pattern, An electronic circuit is provided which is connected to the plurality of conductor patterns of the insulating substrate and has a check terminal connected to a second mounting hole, which is another one of the plurality of mounting holes, through the conductor pattern. A resistor is connected between the check terminal of the DC power supply and the positive terminal of the DC power supply, and a metal case is provided to which the insulating board is mounted with mounting screws through the plurality of mounting holes. Before attaching the insulating board to the case, the high level of the DC power supply is applied to the check terminal of the electronic circuit through a resistor, so unlike conventional methods, test mode can be executed without connecting the jump wire to the check terminal. In addition, by attaching the insulating board to the case with the mounting screws, the check terminal of the electronic circuit automatically becomes low level, which eliminates the need to cut the jump wire unlike in the past. The checking work becomes extremely simple, and when the electronic circuit is to be checked again after the insulating board is attached to the case and assembled, the electronic circuit can be removed by removing the mounting screw corresponding to the second mounting hole from the case. The test mode can be executed, and therefore, unlike conventional methods, there is no need to reconnect the jump wire to the check terminal of the electronic circuit after removing the insulating board from the case, making re-checking extremely easy. This has practical effects such as simplicity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す分解斜視図、
第2図は同実施例のブロツク線図である。 図面中、1はプリント基板(絶縁基板)、2及
び3は第1及び第2の取付孔、4は導体パター
ン、5は直流電源、6はCPU(電子回路)、7乃
至9は導体パターン、10は抵抗器、11はケー
ス、14及び15は取付ねじを示す。
FIG. 1 is an exploded perspective view showing an embodiment of the present invention;
FIG. 2 is a block diagram of the same embodiment. In the drawing, 1 is a printed circuit board (insulating board), 2 and 3 are first and second mounting holes, 4 is a conductor pattern, 5 is a DC power supply, 6 is a CPU (electronic circuit), 7 to 9 are conductor patterns, 10 is a resistor, 11 is a case, and 14 and 15 are mounting screws.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多数の導体パターンが形成されているとともに
複数個の取付孔を有しこれらの取付孔の内の一つ
たる第1の取付孔が導体パターンを介して直流電
源の負端子に接続された絶縁基板と、この絶縁基
板の導体パターンに接続されチエツク端子が導体
パターンを介して前記複数個の取付孔の内の他の
一つたる第2の取付孔に接続された電子回路と、
この電子回路のチエツク端子と前記直流電源の正
端子との間に接続された抵抗器と、前記絶縁基板
が前記複数個の取付孔を介して取付ねじにより取
付けられる金属製のケースとを具備してなる電子
回路装置。
An insulating board on which a large number of conductive patterns are formed and a plurality of mounting holes, one of which is a first mounting hole, is connected to a negative terminal of a DC power supply via the conductive pattern. and an electronic circuit connected to the conductor pattern of the insulating substrate and having a check terminal connected to a second mounting hole, which is another one of the plurality of mounting holes, via the conductor pattern;
The circuit includes a resistor connected between a check terminal of the electronic circuit and a positive terminal of the DC power supply, and a metal case to which the insulating substrate is mounted with mounting screws through the plurality of mounting holes. An electronic circuit device.
JP18925682U 1982-12-15 1982-12-15 electronic circuit equipment Granted JPS5992869U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18925682U JPS5992869U (en) 1982-12-15 1982-12-15 electronic circuit equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18925682U JPS5992869U (en) 1982-12-15 1982-12-15 electronic circuit equipment

Publications (2)

Publication Number Publication Date
JPS5992869U JPS5992869U (en) 1984-06-23
JPS6222854Y2 true JPS6222854Y2 (en) 1987-06-10

Family

ID=30408082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18925682U Granted JPS5992869U (en) 1982-12-15 1982-12-15 electronic circuit equipment

Country Status (1)

Country Link
JP (1) JPS5992869U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI818976B (en) * 2019-04-12 2023-10-21 博計電子股份有限公司 Low voltage drop electronic load connections

Also Published As

Publication number Publication date
JPS5992869U (en) 1984-06-23

Similar Documents

Publication Publication Date Title
JPS6222854Y2 (en)
JPH0720940Y2 (en) Power type electronic circuit device
JPH0236310Y2 (en)
JPH03124088A (en) Printed board device
JPH021371B2 (en)
JPS645877Y2 (en)
JPH0132295Y2 (en)
JPS5841724Y2 (en) External connection terminal device for electrical equipment
JPH04137376A (en) Ic socket
JP2976469B2 (en) Electronic device inspection method
JPS5931261U (en) Connection structure between support terminal and printed circuit board
JPS5818231Y2 (en) Printed circuit board terminal block mounting device
JPS5846537Y2 (en) connection device
JPH0336061Y2 (en)
JP2000124587A (en) Fitting method and fitting structure of electronic circuit unit to printed board
JPH0347351Y2 (en)
JPS6011462U (en) Electronic component mounting structure
JPS5849474U (en) Mounting structure of electrical circuit components
JPH0140473B2 (en)
JPS6120498A (en) Conductive structure of piezoelectric buzzer
JPH0451776U (en)
JPS6124672U (en) Printed wiring board inspection equipment
JPS6246069B2 (en)
JPH0467584A (en) Board fitting connector
JPS59135628U (en) Blocked chip parts for electrical circuits