JPH0143872Y2 - - Google Patents
Info
- Publication number
- JPH0143872Y2 JPH0143872Y2 JP13931183U JP13931183U JPH0143872Y2 JP H0143872 Y2 JPH0143872 Y2 JP H0143872Y2 JP 13931183 U JP13931183 U JP 13931183U JP 13931183 U JP13931183 U JP 13931183U JP H0143872 Y2 JPH0143872 Y2 JP H0143872Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- external lead
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000005452 bending Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 206010040844 Skin exfoliation Diseases 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 150000004982 aromatic amines Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Description
【考案の詳細な説明】
産業上の利用分野
本考案は、可撓性絶縁基体上に半導体チツプ載
置部ならびに外部リード部を形成するための金属
層が設けられた構造のリードフレームに関する。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a lead frame having a structure in which a metal layer for forming a semiconductor chip mounting part and an external lead part is provided on a flexible insulating base.
ポリイミドフイルムあるいはポリエステルフイ
ルム等の可撓性をもつ絶縁基体上に、所定の厚み
の金属層を設け、この金属層で半導体チツプ載置
部ならびに外部リード部を形成した構造のリード
フレームとして、従来、第１図で示す構造を具備
するものが知られている。 Conventionally, a lead frame has a structure in which a metal layer of a predetermined thickness is provided on a flexible insulating substrate such as polyimide film or polyester film, and this metal layer forms a semiconductor chip mounting part and an external lead part. A device having the structure shown in FIG. 1 is known.
第１図で示すリードフレームは、例えば、ポリ
イミドフイルム１の片面に銅箔を貼着し、これに
選択エツチング処理を施して半導体チツプ載置部
２、外部リード部３および４を形成するととも
に、半導体チツプ載置部２および外部リード部
３，４のワイヤボンデイング部分となる各一方の
端部に、半導体チツプの接着ならびにワイヤボン
デイングを容易にする金属めつき層５を形成した
構造となつている。そして、このリードフレーム
を用いた半導体装置の組み立ては、図示するよう
に半導体チツプ６を接着したのち、半導体チツプ
上の電極と外部リード部３および４との間を金属
細線７で接続することによつてなされる。 The lead frame shown in FIG. 1 is made by, for example, pasting a copper foil on one side of a polyimide film 1 and subjecting it to a selective etching process to form a semiconductor chip mounting part 2 and external lead parts 3 and 4. It has a structure in which a metal plating layer 5 is formed on one end of each of the semiconductor chip mounting part 2 and the external lead parts 3 and 4, which will be the wire bonding part, to facilitate adhesion of the semiconductor chip and wire bonding. . Assembling a semiconductor device using this lead frame consists of bonding the semiconductor chip 6 as shown in the figure and then connecting the electrodes on the semiconductor chip and the external lead parts 3 and 4 with thin metal wires 7. It is done by hand.
このようにして形成された半導体装置では、外
部リード部の各他方の端部が被接続基板への取り
付け用端子として用いられる。すなわち、図示す
るように、被接続基板８の導体層９および１０と
外部リード部３と４とを対向させ、両者間を鑞材
を用いて接続することにより半導体装置の取りつ
けがなされる。 In the semiconductor device formed in this manner, each other end of the external lead portion is used as a terminal for attachment to a substrate to be connected. That is, as shown in the figure, the semiconductor device is mounted by arranging the conductor layers 9 and 10 of the connected substrate 8 and the external lead parts 3 and 4 and connecting them using a solder material.
ところで、従来の可撓性リードフレームでは、
半導体チツプの接着およびワイヤボンデイングを
行い半導体装置を完成させると、金属細線がリー
ドフレームの外部リード部の面よりも上部（第１
図では下部）に位置するところとなる。したがつ
て、被接続基板８へ半導体装置を取りつけるに際
してはこの高さを考慮し、リードフレーム面と被
接着基板面との間に所定の間隙ｌを付与する配慮
を払わねばならなかつた。また、間隙ｌを付与し
て被接続基板８へ半導体装置を取り付けるために
は、両者間にスペーサを介装すること、あるい
は、被接続基板８に特別な加工を施すことなどの
対策を講じる必要があり、取り付け作業の煩雑化
あるいは被接着基板のコストの高騰などの問題が
派生するところとなる。 By the way, in the conventional flexible lead frame,
When the semiconductor device is completed by adhering the semiconductor chip and wire bonding, the thin metal wires are placed above the surface of the external lead part of the lead frame (the first
In the figure, it is located at the bottom). Therefore, when attaching the semiconductor device to the substrate to be connected 8, consideration must be given to this height and to provide a predetermined gap l between the surface of the lead frame and the surface of the substrate to be bonded. In addition, in order to attach the semiconductor device to the connected substrate 8 with a gap l, it is necessary to take measures such as interposing a spacer between the two or performing special processing on the connected substrate 8. This results in problems such as complicated installation work and a rise in the cost of the substrate to be bonded.
考案の目的
本考案は、可撓性リードフレームそのものによ
つて、被接続基板への取り付け時に必要とされる
間隙を付与することができる可撓性リードフレー
ムの構造の提供を目的とするものである。Purpose of the invention The purpose of the invention is to provide a structure of a flexible lead frame that can provide the necessary clearance when attaching to a connected board by the flexible lead frame itself. be.
考案の構成
本考案にかかるリードフレームは、半導体チツ
プ載置部および外部リード部形成用の金属層が一
方の面上に設けられた可撓性絶縁基体の、前記外
部リード部形成用金属層の形成面部分に、90゜以
下の２重折り返し曲げ加工が施されて構成された
ものであり、これにより、半導体チツプならびに
金属細線の周囲に所定の間隙が付与される状態を
成立させて、半導体装置を被接続基板へ取り付け
ることのできるリードフレームが実現される。Structure of the Invention The lead frame according to the present invention includes a flexible insulating base having a semiconductor chip mounting portion and a metal layer for forming an external lead portion on one side thereof. The forming surface is double-folded by 90 degrees or less, thereby creating a condition in which a predetermined gap is provided around the semiconductor chip and the thin metal wire, and the semiconductor A lead frame is realized that allows the device to be attached to a connected board.
実施例の説明
第２図は、本考案のリードフレームとこれを用
いて形成した半導体装置の構造を示す断面図であ
り、構成要素の全ては、第１図で示した従来のも
のと同じであり、同一構成要素には同一の番号を
付与している。このように、構成要素面では同じ
であるが、本考案のリードフレームでは、外部リ
ード部３と４が形成された可撓性絶縁基体、たと
えばポリイミドフイルム１の部分１１と１２に対
して、90゜以下の第１の折り曲げ加工が施され、
さらに、これらの部分よりも外方に位置する部分
１３と１４に対して、第１の折り曲げ加工による
折り曲げ方向とは逆の方向に向う90゜以下の第２
の折り曲げ加工が施されている。DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a cross-sectional view showing the structure of the lead frame of the present invention and a semiconductor device formed using the lead frame, and all of the components are the same as those of the conventional lead frame shown in FIG. Identical components are given the same numbers. As described above, although the components are the same, the lead frame of the present invention has a 90° The first bending process of ゜ or less is performed,
Furthermore, for the parts 13 and 14 located outward from these parts, a second bending angle of 90 degrees or less is made in the opposite direction to the bending direction by the first bending process.
The folding process has been applied.
ところで、リードフレーム面から金属細線の最
高点までの高さは、通常、0.1〜0.5mm程度であ
る。したがつて、上記の２重折り返し曲げ加工に
より、外部リード部３および４の各他方の端部面
が金属細線の最高点を越えるところに位置し、図
示するように半導体チツプ６および金属細線７の
すべてが確実に収納される凹部１５を得るには、
曲げ半径を0.1mm以上に設定する必要がある。こ
のような値に曲げ半径を設定するならば、折り返
えされたリードフレームの厚みが加わり所期の目
的が達成される。なお、曲げ半径を必要以上に大
きくすることは、凹所１５を必要以上に深くする
ことにつながり、リードフレーム素材の使用量の
増加あるいは半導体装置の大型化などの不都合が
生じる。このような不都合は、上記の曲げ半径を
0.5mm以下にとどめることにより殆んど回避する
ことができる。 By the way, the height from the lead frame surface to the highest point of the thin metal wire is usually about 0.1 to 0.5 mm. Therefore, by the double folding process described above, the other end surfaces of the external lead parts 3 and 4 are located beyond the highest point of the thin metal wire, and as shown in the figure, the semiconductor chip 6 and the thin metal wire 7 are In order to obtain a recess 15 in which all of the above are reliably accommodated,
It is necessary to set the bending radius to 0.1mm or more. If the bending radius is set to such a value, the thickness of the folded lead frame will be added to achieve the desired purpose. Incidentally, making the bending radius larger than necessary leads to making the recess 15 deeper than necessary, resulting in disadvantages such as an increase in the amount of lead frame material used or an increase in the size of the semiconductor device. This inconvenience can be avoided by changing the bending radius above.
Most of these can be avoided by keeping the thickness to 0.5 mm or less.
本考案のリードフレームでは、上記のように折
り返し曲げ加工を施すことが不可欠であるが、使
用するフイルム基材としては、その厚さが、
105μｍ，75μｍ，50μｍ，25μｍおよび12.5μｍの
標準グレードのものの全てを使用することが可能
である。一方、フイルム基材に貼着する銅箔等の
金属層および接着剤の標準的な厚みは10〜70μｍ
程度であるが、通常のものでは折り返し曲げ加工
により剥離などの不都合をきたすおそれがある
が、硫酸銅浴あるいはシアン化銅浴を用いて形成
される比較的延展性のよい銅箔に1μｍ程度の厚
さの裏面亜鉛めつきを施したものを用いるととも
に、接着剤として芳香族アミンアダクト化合物を
硬化剤として配合したエポキシ樹脂を用いること
により、折り返し曲げ加工による剥離などの不都
合を排除することができる。この接着剤は、単に
可撓性の面ですぐれているばかりでなく、耐熱性
の面でもすぐれており、リードフレームの耐熱特
性を向上させる点からみても好ましいものであ
る。 In the lead frame of the present invention, it is essential to perform the folding and bending process as described above, but the thickness of the film base material used is
All standard grades of 105 μm, 75 μm, 50 μm, 25 μm and 12.5 μm can be used. On the other hand, the standard thickness of the metal layer such as copper foil and adhesive that is attached to the film base material is 10 to 70 μm.
However, with ordinary foils, there is a risk of peeling or other inconveniences due to the folding process. By using a material with a thick galvanized back surface and using an epoxy resin containing an aromatic amine adduct compound as a hardening agent as an adhesive, inconveniences such as peeling due to folding and bending can be eliminated. . This adhesive is not only excellent in terms of flexibility but also in terms of heat resistance, and is preferable from the viewpoint of improving the heat resistance characteristics of the lead frame.
以上のような配慮の下で形成した本考案のリー
ドフレームを使用して形成した半導体装置を被接
続基板８へ取り付けるに際しては、その導体層９
および１０とリードフレームの外部リード部３お
よび４の各一端とを必要最少限度の鑞材を用いて
接着すればよく、この取り付けにより、半導体チ
ツプ６および金属細線７は被接続基板８によつて
塞がれた凹所１５の中に位置するところとなる。 When attaching a semiconductor device formed using the lead frame of the present invention formed with the above considerations to the connected substrate 8, the conductor layer 9
and 10 and one end of each of the external lead portions 3 and 4 of the lead frame may be bonded using the minimum necessary amount of solder. It will be located in the closed recess 15.
考案の効果
本考案のリードフレームは、これ自体が凹所を
もち、この内部で半導体チツプの接着ならびにワ
イヤボンデイングをなしうるものであり、従来の
もののように被接続基板への取り付けに際して、
特別な配慮を払う必要がない。このため、取り付
け作業の高能率化あるいは被接続基板のコストの
低減などの効果が奏される。Effects of the Invention The lead frame of the present invention has a concave part within which adhesion of semiconductor chips and wire bonding can be performed.
No special consideration is required. Therefore, effects such as higher efficiency of the mounting work and reduction of the cost of the connected board can be achieved.
なお、リードフレームの凹所の開口部の大きさ
が半導体チツプの大きさを考慮するとともにワイ
ヤボンデイング位置を考慮して決定されること
は、あえて詳しく説明するまでもない。 It is needless to explain in detail that the size of the opening of the recess in the lead frame is determined by taking into consideration the size of the semiconductor chip and the wire bonding position.
第１図は、従来のリードフレームとこれを用い
て形成した半導体装置の構造を示す断面図、第２
図は、本考案のリードフレームとこれを用いて形
成した半導体装置の構造を示す断面図である。
１……ポリイミドフイルム、２……半導体チツ
プ載置部、３，４……外部リード部、５……金属
めつき層、６……半導体チツプ、７……金属細
線、８……被接続基板、９，１０……導体層、１
１〜１４……折り曲げ加工部、１５……凹所。
FIG. 1 is a cross-sectional view showing the structure of a conventional lead frame and a semiconductor device formed using the lead frame.
The figure is a sectional view showing the structure of a lead frame of the present invention and a semiconductor device formed using the lead frame. DESCRIPTION OF SYMBOLS 1...Polyimide film, 2...Semiconductor chip mounting part, 3, 4...External lead part, 5...Metal plating layer, 6...Semiconductor chip, 7...Metal thin wire, 8...Substrate to be connected , 9, 10... conductor layer, 1
1 to 14...bending portion, 15...recess.
Claims (1)
の金属層が一方の面上に形成された可撓性絶縁基
体の、前記外部リード部形成用金属層の形成面部
分に、90゜以下の２重折り返し曲げ加工が施され
ていることを特徴とするリードフレーム。 A double layer of 90° or less is formed on the surface where the metal layer for forming the external lead part is formed on the flexible insulating base, on which the metal layer for forming the semiconductor chip mounting part and the external lead part is formed. A lead frame characterized by being folded and bent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983139311U JPS6048252U (en) | 1983-09-08 | 1983-09-08 | lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983139311U JPS6048252U (en) | 1983-09-08 | 1983-09-08 | lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6048252U JPS6048252U (en) | 1985-04-04 |
| JPH0143872Y2 true JPH0143872Y2 (en) | 1989-12-19 |
Family
ID=30312289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983139311U Granted JPS6048252U (en) | 1983-09-08 | 1983-09-08 | lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6048252U (en) |
-
1983
- 1983-09-08 JP JP1983139311U patent/JPS6048252U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6048252U (en) | 1985-04-04 |
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