JPH0143490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time pulse generation circuit.

Conventionally, the circuit configuration shown in FIG. 1 has been generally used as a method for arbitrarily controlling the pulse generation interval. In FIG. 1, a reference time generating circuit 1 that generates a predetermined time pulse is composed of a binary counter consisting of master-slave flip-flops F ₁ , F ₂ . . . F _o , a NAND gate G ₁ and
_Each time a trigger pulse is input to the reset input of the binary counter, only one pulse with a predetermined time width can be generated. Fall detection circuit 2 is reference time generation circuit 1
The monostable multivibrator 3 is composed of, for example, a differentiating circuit or the like, which detects the falling edge of a pulse generated by the falling edge of the pulse. The fall detection circuit 4 detects the fall of the pulse output of the monostable multivibrator 3. For example,
It consists of a differentiating circuit and the like and outputs a trigger pulse to the reset terminal of the binary counter of the reference time generating circuit 1. Here, the pulse interval of the reference time generating circuit 1 is determined by the pulse width of the monostable multivibrator 3, so to arbitrarily change the pulse interval, change the time constant CR that determines the pulse width of the monostable multivibrator 3. Just let it happen. However, such a method of varying the pulse interval using a monostable multivibrator is not very suitable in cases where accurate pulse intervals are required. This is because the pulse width of a monostable multivibrator is greatly affected by changes in power supply voltage and deviations in circuit elements. Furthermore, if the pulse width is long, such as from several seconds to several tens of seconds, a large capacitance is required, making it difficult to integrate into an IC.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time pulse generating circuit which is completely unaffected by changes in power supply voltage and does not require any capacitance.

The present invention provides a counter for counting N, a decoder that detects when the counter reaches a count value N and outputs a trigger signal, a comparison voltage generation circuit that is provided between power supplies and generates a comparison voltage, and a reference voltage generation circuit having a resistance division network connected between power supplies and generating a voltage at a corresponding resistance division point according to the count value of the counter; a comparison voltage from the comparison voltage generation circuit and the reference voltage; a comparison circuit that compares a reference voltage taken out from a generation circuit according to the count value of the counter; and a comparison circuit that responds to the trigger signal from the decoder and outputs a pulse signal of a predetermined width each time the trigger signal is input. a flip-flop in which the reference voltage is set for a period in which the comparison voltage is smaller than the reference voltage in response to the output of the comparison circuit, and reset in a period in which the comparison voltage is larger than the reference voltage; A high-speed pulse is selected within a period in which a pulse signal of a predetermined width is output and during the setting period of the flip-flop, and a low-speed pulse is selected after a pulse signal of a predetermined width is output from the reference time generation circuit. a count pulse selection circuit having a selection gate; during a period when the pulse selection circuit selects the high speed pulse, the high speed pulse controls the counting operation of the counter, and during a period when the low speed pulse is selected. By controlling the counting operation of the counter with this low-speed pulse, by changing the comparison voltage, the number of high-speed pulses input to the counter during a period in which this comparison voltage is greater than the reference voltage is increased. The present invention is characterized in that the number of pulse signals is changed, thereby making variable the generation interval of the pulse signal of the predetermined width outputted from the reference time generation circuit.

Next, an embodiment of the present invention will be described with reference to FIG.

This embodiment shows an example in which 0.8 second pulses can be generated at arbitrary integer second intervals from 1 second to 14 seconds. In FIG. 2, the binary counter 5 has a hexadecimal configuration with reset consisting of four master-slave flip-flops, and a decoder 6
The code of counter 5 is "1111" indicating count N (the code is written in the flip-flop F/F
Q output from 1 to F/F4, the order is F/F4, F/F
3, F/F2, and F/F1, and the high level is written as 1 and the low level as 0. The same applies below. ), a trigger output pulse is generated.
The reference voltage generation circuit 7 generates a predetermined voltage based on the count state of the binary counter 5. The voltage comparison circuit 8 compares the output of the reference voltage generation circuit 7 and the comparison voltage applied from the comparison voltage input. The reference time generating circuit 9 consists of four master-slave flip-flops, etc., and generates a 0.8 second time pulse when a trigger pulse is input to the set input. The count pulse selection circuit 10 selects either a 1 Hz count pulse or a 32 Hz count pulse and supplies it to the clock input of the counter 5.

Now, when the counter 5 code reaches "1111" indicating count N, the NAND gate G3 of decoder 6
changes from "1" to "0" and becomes NOR gate G by delay flip-flop DFF and NOR gate G4.
The output of 4 generates a trigger pulse as shown in FIG. 3a. (The state in which this trigger pulse is generated will be referred to as the initial state.) This trigger pulse resets the counter 5 to ``0000'' and also triggers the reference time generating circuit 9 to generate the output signal as shown in Fig. 3b.
(represents the output of NAND gate G6)
Generates a 0.8 second pulse. By the way, the reference voltage generation circuit 7 is composed of resistors R ₁ , ..., R ₁₄ and P-type MOS transistors T ₁₁ , ..., T ₁₅₄ whose gates are selectively inputted with the output of the counter 5. Correspondingly, one of the voltage levels divided by the resistors R ₁ , . . . , R ₁₄ appears at point A.
For example, when the code of counter 5 is "0011", transistors T ₄₁ , T ₄₂ , T ₄₃ , and T ₄₄ are all conductive, and the voltage at _three points C (R ₄ +R ₅ +...+R ₁₄ )V/R ₁ +R ₂
+...+ _R14 appears at point A and is applied to one input of the voltage comparator circuit 8. Further, the other input B of the voltage comparison circuit 8 is given a voltage level of (r+r ₂ )V/r+r ₁ +r ₂ divided by resistors r ₁ , r ₂ , and r.

Therefore, in the initial state, the code of counter 5 is "0000", so the voltage of point _C0 is given to point A, but since this is always higher than the voltage of point B, the output of voltage comparison circuit 8 is It becomes "0". (The output of the voltage comparator circuit in this example is assumed to be "0" when the voltage at point A is greater than the voltage at point B, and "1" when the voltage is opposite.) Also, the NOR gate G
4 trigger pulse is the count pulse selection circuit 10
Since it is also given to the input of NOR gate G7 of
Consists of NOR gate G7 and NOR gate G8
The output of the NOR gate G8 of the RS flip-flop becomes "1" and the AND gate G11 becomes conductive. on the other hand
Since the output of NAND gate G6 is "1", AND gate G10 is rendered non-conductive through inverter G9. Therefore, after the initial state, the count pulse selection circuit 10 outputs 32Hz.
The count pulses are given to the clock input of the counter 5 through the AND gate 11 and the NOR gate G12, so the counter 5 counts up every time the 32Hz clock is input, and the A point receives C ₀ , C 1 , C ₁ , The voltage at point C ₂ is given. By the way, if the voltage at point B is between the voltages at _two points C, when the codes of counter 5 are "0000", "0001", and "0010", the voltage at point A > the voltage at point B. Therefore, the output of the voltage comparator circuit 8 remains "0", but when the code of the counter 5 becomes "0011" indicating count i, the voltage at point A < the voltage at point B, so the output of the voltage comparator circuit 8 becomes "1" and NOR gate G7 and NOR gate G8
NOR gate G of RS flip-flop consisting of
The output of 8 is inverted and becomes "0", and the AND gate G
11 becomes non-conductive. Also, AND gate G10 is
The output of NAND gate G6 is "1"
Since there is no conduction for 0.8 seconds, after the code of the counter 5 becomes "0011", neither the 1 Hz count pulse nor the 32 Hz count pulse is applied to the clock input of the counter 5 from the count pulse selection circuit 10. The code of counter 5 remains at "0011". Then, when NAND gate G6 becomes "0" after 0.8 seconds from the initial state, AND gate G10 becomes conductive, and this time the 1Hz count pulse is applied to AND gate G10 and NOR gate G1.
The code is given to counter 5 through 2, and the counter counts up every second until the code becomes ``0011.''
When 12 seconds elapse from 1111 to 1111, the decoder 6 detects 1111 and generates a trigger pulse, returning to the initial state and repeating the same operation.

In addition, the output of the voltage comparison circuit 8 and the NOR gate G
The outputs of 12 are shown in FIGS. 3c and d, respectively.

In this way, in this embodiment, by counting up the counter 5 using a 32 Hz count pulse while a 0.8 second pulse is being generated, the voltage at point B is changed to the reference voltage point C ₀ of the reference voltage generation circuit 7. _C1 ,
..., C The time interval until the next 0.8 second pulse is generated is controlled by the counter 5 memorizing where it is established among the ₁₄ points. Specifically, by changing the resistance r, the interval between pulses of 0.8 seconds can be changed stepwise from 1 second to 14 seconds. In other words, the pulse generation interval is B
If the voltage at point C is between the voltage at point C ₀ and the voltage at point C ₁ , it will take 14 seconds, if it is between the voltage at point C ₁ and the voltage at point C ₂ , it will take ₁₃ seconds. C If the voltage is between _{the 14} points, it will be 1 second. Therefore, the resistance r ₁ , r ₂ , R ₁ ...
For example, if _R14 is selected appropriately, the resistance r
The pulse generation interval can be changed by changing . Furthermore, in this embodiment, the pulse generation interval is changed every second using a 1 Hz count pulse, but if a count pulse of another frequency is used, the pulse generation interval can be changed at another time interval. Of course it is possible.

As described above, according to this configuration method, what physically determines the pulse generation interval is the voltage level applied to the two inputs of the voltage comparator circuit; Since only the relative magnitude matters, not the absolute magnitude, the pulse interval is ultimately determined only by the resistor division ratio and is unrelated to the magnitude of the power supply voltage. . Furthermore, since the size of the resistance does not require an absolute value, it is suitable for integration.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional time pulse generation circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a time chart for explaining the operation of the embodiment, and Fig. 4 is an example of an output diagram of the same embodiment. DESCRIPTION OF SYMBOLS 1... Reference time generation circuit, 2... Fall detection circuit, 3... Monostable multivibrator, 5... Counter, 6... Decoder, 7... Voltage ratio load circuit,
8... Voltage comparison circuit, 9... Reference time generation circuit.

Claims (1)

[Claims] 1 A counter for counting N, a decoder that detects that the counter has reached the count value N and outputs a trigger signal, a comparison voltage generation circuit that is installed between the power supplies and generates a comparison voltage, and a a reference voltage generation circuit having a resistor division network connected thereto and generating a voltage at a corresponding resistance division point according to the count value of the counter; and a comparison voltage from the comparison voltage generation circuit and the reference voltage generation circuit. a comparison circuit that compares a reference voltage taken out according to the count value of the counter; and a reference time that responds to the trigger signal from the decoder and outputs a pulse signal of a predetermined width each time the trigger signal is input. a generation circuit, a flip-flop in which the comparison voltage is set for a period when the comparison voltage is smaller than the reference voltage in response to the output of the comparison circuit, and is reset for a period when the comparison voltage is larger than the reference voltage; a selection gate that selects a high-speed pulse within a period in which a pulse signal is output and during the setting period of the flip-flop, and selects a low-speed pulse after the pulse signal of the predetermined width is output from the reference time generating circuit; a count pulse selection circuit having a count pulse selection circuit, during a period when the pulse selection circuit selects the high speed pulse, the high speed pulse controls the counting operation of the counter, and during a period when the low speed pulse is selected, the counting operation of the counter is controlled by the high speed pulse. By controlling the counting operation of the counter with pulses, by changing the comparison voltage, the number of fast pulses input to the counter during a period in which this comparison voltage is greater than the reference voltage is varied. , thereby making variable the generation interval of the pulse signal of the predetermined width outputted from the reference time generation circuit.