KR910006576Y1 - Tracking control circuit using push swiching for vtr - Google Patents

Tracking control circuit using push swiching for vtr Download PDF

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Publication number
KR910006576Y1
KR910006576Y1 KR2019880011437U KR880011437U KR910006576Y1 KR 910006576 Y1 KR910006576 Y1 KR 910006576Y1 KR 2019880011437 U KR2019880011437 U KR 2019880011437U KR 880011437 U KR880011437 U KR 880011437U KR 910006576 Y1 KR910006576 Y1 KR 910006576Y1
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KR
South Korea
Prior art keywords
binary counter
vtr
preset
control circuit
tracking
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KR2019880011437U
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Korean (ko)
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KR900003558U (en
Inventor
한형덕
문태원
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삼성전자 주식회사
안시환
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Priority to KR2019880011437U priority Critical patent/KR910006576Y1/en
Priority to JP1989082131U priority patent/JPH0284136U/ja
Priority to DE3923194A priority patent/DE3923194A1/en
Priority to GB8916108A priority patent/GB2222008B/en
Publication of KR900003558U publication Critical patent/KR900003558U/en
Application granted granted Critical
Publication of KR910006576Y1 publication Critical patent/KR910006576Y1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/584—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on tapes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
    • G11B15/46—Controlling, regulating, or indicating speed
    • G11B15/467—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven
    • G11B15/4673—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven by controlling the speed of the tape while the head is rotating
    • G11B15/4675—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven by controlling the speed of the tape while the head is rotating with provision for information tracking
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
    • G11B15/46—Controlling, regulating, or indicating speed
    • G11B15/467—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven
    • G11B15/4673—Controlling, regulating, or indicating speed in arrangements for recording or reproducing wherein both record carriers and heads are driven by controlling the speed of the tape while the head is rotating

Abstract

내용 없음.No content.

Description

푸쉬스위치 방식을 채용한 VTR에서의 트래킹 제어회로Tracking control circuit in VTR using push switch method

제1도는 종래의 회로도.1 is a conventional circuit diagram.

제2도는 종래의 단안정 멀티 바이브레이터의 입, 출력 파형도.2 is an input and output waveform diagram of a conventional monostable multivibrator.

제3도는 본 고안의 회로도.3 is a circuit diagram of the present invention.

제4도는 본 고안에서의 프리세트 2진 카운터의 동작설명을 위한 파형도.Figure 4 is a waveform diagram for explaining the operation of the preset binary counter in the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

가 : 제1발진기(OSC1) 나 : 제2발진기(OSC2)A: Oscillator 1 (OSC 1 ) B: Oscillator 2 (OSC 2 )

다 : 프레세트 2진 카운터 라 :분주기Preset binary counter Divider

마 : 가산기(Adder)E: Adder

바 : EEP ROM (Electrically Erasable Programmable ROM)Bar: EEP ROM (Electrically Erasable Programmable ROM)

사 : 업/다운 2진 카운터 Su : 업스위치4: Up / Down Binary counter Su: Up switch

SD: 다운스위치 S : 리세트스위치S D : Down switch S: Reset switch

Ssub : 서브스위치Ssub: Subswitch

본 고안은 VTR에서의 트래킹 제어를 위한 회로에 관한 것으로서, 특히 푸쉬스위치 방식을 채용하고 있는 VTR에 가장 적합한 것이다.The present invention relates to a circuit for tracking control in a VTR, and is particularly suitable for a VTR employing a push switch method.

종래의 VTR의 캡스턴 또는 드럼모우터의 정속 및 정위상 제어회로에는 트래킹 조절회로를 구비하고 있으며, 이는 제1도에 나타낸 바와같이 단안정 멀티 바이브레이터(M. M)와 가변저항(VR1)(VR2), 콘덴서(C)에 의한 것으로서, 트래킹 조정은 가변저항(VR1), 트래킹 프리세트 조정은 가변저항(VR2)을 각각 조정하도록 되어 있다.The constant speed and phase control circuit of the capstan or drum motor of the conventional VTR includes a tracking control circuit, which is a monostable multivibrator (M. M) and a variable resistor (VR 1 ) (as shown in FIG. VR 2 ) and the capacitor C, the tracking adjustment is made of the variable resistor VR 1 , and the tracking preset adjustment is made of the variable resistor VR 2 .

그러나, 이와 같은 종래의 회로는 트래킹 가변저항 및 제조 공정상에서 조정용 가변저항을 별도로 설치할 필요가 있고, 또한 콘덴서 용량값의 온도변화 특성에 의하여 온도가 변화함에 따라 지연시간이 변경되므로 VTR의 내열, 내습, 내한 등 주위의 영향으로 성능 열화의 문제점이 있엇다.However, in such a conventional circuit, it is necessary to separately install the adjusting variable resistor in the tracking variable resistor and the manufacturing process, and the delay time is changed according to the temperature change characteristic of the capacitor capacitance value, so that the heat resistance and moisture resistance of the VTR are changed. There is a problem of performance deterioration due to the influence of ambient temperature such as cold weather and cold weather.

본 고안은 이러한 종래의 문제점을 개선하고자 하여 트래킹 프리세트 회로에서 일정시간 지연을 위한 회로를 종래와 같이 R. C 직렬회로에 의존하지 않고, 프리세트가 가능한 업/다운(UP/Down) 카운터를 이용하여 일정시간 동안의 지연기능을 주파수가 일정한 클럭펄스를 정해진 수만큼 계수할때 일정시간 기능을 행하며, 이와같은 계수회로를 이용한 지연기능으로서 보다 안정된 지연 동작을 유지할 수 있도록 한것으로, 이를 첨부한 도면에 의하여 상술하면 다음과 같다.The present invention aims to improve such a conventional problem, and it is not necessary to rely on the R / C series circuits for a predetermined time delay in the tracking preset circuit, and to provide an UP / Down counter that can be preset. Delay function for a certain period of time by using a constant time function when the frequency counts a fixed number of clock pulses, and as a delay function using such a counting circuit to maintain a more stable delay operation, attached drawings When described in detail as follows.

제3도에서와 같이 30HZ 기준 주파수를 발진하는 제1발진기(OSC1) 및 클럭펄스를 발진하는 제2발진기(OSC2)에 프리세트 2진 카운터(다)와 상기 제2발진기(OSC2)와 프리세트 2진카운터(다) 사이에분주기(라)와 상기분주기(라)에는 업, 다운 스위치(Su), (SD)가 접속된 업/다운 2진 카운터 (사)를 통하여 EEP ROM(바) 및 가산기(마)를 각각 연결 구성하고, 상기 가산기(마)는 프리세트 2진 카운터(다)를 통하여 통상의 캡스턴 모우터 위상 비교회로에 연결하여 구성된 것이다.Third Degree 30HZ reference frequency first oscillator for oscillating a (OSC 1) and a second oscillator (OSC 2) preset binary counter for oscillating a clock pulse as shown in (C) and the second oscillator (OSC 2) And the preset binary counter (C) Divider and d) In the divider D , an EEP ROM (bar) and an adder (e) are connected to each other through an up / down binary counter (4) to which up, down switches (Su) and (S D ) are connected. (E) is configured by connecting to a normal capstan motor phase comparison circuit through a preset binary counter (C).

미설명 부호 SR은 리세트 스위치, Ssub는 서브스위치이다.Reference numeral SR denotes a reset switch and Ssub denotes a sub switch.

이와같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.

우선, 제1발진기(OSC1)로 부터 30HZ 프리세트 입력(상승에지 프리세트 기능임)으로 프리세트 2진 카운터(다)가 받으면 가산기(마)의 출력은 프리세트 되어 클럭 입력단자로부터의 클럭입력을 카운트 다운(본 고안에서는 카운트 다운 기능으로만 설정됨)한다.First, when a preset binary counter (C) is received from the first oscillator (OSC 1 ) with a 30HZ preset input (rising edge preset function), the output of the adder (E) is preset and clocked from the clock input terminal. Count down the input (in this design, set only to the countdown function).

이때에 출력은 제로 크로스 출력을 활용하여 0값이 되면 하이상태가 된다.At this time, the output becomes high when the value is 0 by utilizing the zero cross output.

이는 제4도에 나타낸 파형을 참조하면 쉽게 이해될수가 있다. 제4도에서 △T의 가변은 업/다운 2진 카운터(사)의 계수치의 증감에 따라 △T의 길이의 증감이 가능하다.This can be easily understood with reference to the waveform shown in FIG. In FIG. 4, the variable of? T can be increased or decreased in accordance with the increase / decrease of the count value of the up / down binary counter.

따라서, EEP ROM(바)의 메모지가 없을때에는 업/다운 2진 카운터(사)의 계수를 업/다운 2진 카운터(사)의 계수지를 업, 다운 스위치(Su)(SD)로서 가감하여 기준 펄스의 상승에서 타이밍을 △T 만큼 지연 시키게 된다.Therefore, when there is no memo of the EEP ROM (bar), the count of the up / down binary counter (sa) is added or subtracted by the up / down binary counter (sa) as the down switch Su (S D ). At the rising of the reference pulse, the timing is delayed by ΔT.

이는 결국, 캡스턴 모우터의 위상제어회로의 기준 위상을 가변시키는 것이므로 VTR 재생시의 화면의 트래킹을 조정하는 것과 동일하다.This is, after all, varying the reference phase of the phase control circuit of the capstan motor, which is equivalent to adjusting the tracking of the screen during VTR reproduction.

즉, 업, 다운(Su)(SD) 스위치를 온.오프하여 드럼 스위치 펄스 및 콘트롤펄스의 상대위상을 일정하게 조정한 후 EEP ROM(바)에 기억시키기 위하여 서보스위치(Ssub)를 온하면 조정이 완료된다.That is, when up, turns on the down (Su) (S D), the servo switch (Ssub) in order to memory on the switch After the off by constantly adjusting the relative phase of the drum switch pulse and the control pulse to the EEP ROM (bar) Adjustment is complete.

즉, 업/다운 2진 카운터(사)의 내용이 EEP ROM(바)에 메모리됨과 동시에 업/다운 2진 카운터(사)의 내용은 리세트되며 이때부터 업, 다운 스위치(Su)(SD)는 조작자의 조정용 트래킹 스위치 역할을 행한다.That is, the contents of the up / down binary counter (sa) are stored in the EEP ROM (bar) and the contents of the up / down binary counter (sa) are reset. From this time, the up / down binary counter (S D ) is reset. ) Serves as an adjustment tracking switch for the operator.

한편, 업/다운 2진 카운터(사)의 동작은 클럭 입력단에 입력되는 클럭펄스를 계수하는데 이때 업스위치(Su)가 온일때에는 카운트 업, 다운 스위치(SD)가 온일 때에는 업/다운 2진 카운트 (사)는 다운된다.On the other hand, the operation of the up / down binary counter (g) counts the clock pulses input to the clock input stage, wherein the up / down binary counter counts up when the up switch Su is on and up / down binary when the down switch S D is on. The count is down.

이때 입력되는 클럭주파수는 조정단계에 의하여 카운터의 데이타 비트수가 결정되는데 예를들어 N비트라고 되면 2N단계의 조정이 가능하다.At this time, the input clock frequency determines the number of data bits of the counter by the adjusting step. For example, if the number of bits is N bits, the clock frequency can be adjusted in 2N steps.

상기의 N=8 비트이면 28=256단계로서 충분하므로 이를 예로서 설명하면 다음과 같다.If N = 8 bits, 2 8 = 256 steps are sufficient.

상기의 업/다운 2진 카운터(사)의 전계수 시간을 약 10초라고 가정하면 이때의 입력 클럭주파수는 28/1025.6HZ가 된다.When the jeongyesu time of up / down binary counter (G) of the assumption that about 10 seconds and the input clock frequency at this time is 2 8/10 25.6HZ.

트래킹의 조정은 제조 공정시의 서보조정과 조작자의 조정으로 구분되며, 상기한 서보조정(제조 공정시의 조정)은 EEP ROM(바)의 리세트 스위치(SR)을 온하여 EEP ROM(바)의 내용을 소거하고, 업/다운 2진 카운터(사)의 업/다운 스위치(Su)(SD)를 온하여 8비트 데이타 출력을 가산기(마)(N+2비트 이상)에 보내면 이때 다른 한쪽의 입력(EEP ROM의 출력)은 0입력이므로 이 출력은 가산기(마)에 출력되어 상술한 프리세트 2진 카운터(다)의 프리세트 입력단자에 공급되는 것이다.Tracking adjustment is divided into servo adjustment at the manufacturing process and operator's adjustment. The above servo adjustment (adjustment at the manufacturing process) is performed by turning on the reset switch S R of the EEP ROM (bar). ), And turn on the up / down switch Su (S D ) of the up / down binary counter to send an 8-bit data output to the adder (N + 2 bits or more). Since the other input (output of EEP ROM) is 0 input, this output is output to the adder (e) and is supplied to the preset input terminal of the above-mentioned preset binary counter (C).

이상에서와 같이 동작되는 본 고안은 트래킹 조정용 가변저항을 사용하지 않기 때문에 서어보 IC 내에 IC 화가 가능하여 소형 경량화가 가능할 뿐만 아니라, 내열, 내습, 내한등 주위 환경에 대하여서도 트래킹이 변화하지 않는 안정된 제어기능을 발휘할 수가 있는 것이다.The present invention, which operates as described above, does not use the variable resistor for tracking adjustment, so it is possible to IC in the servo IC, which makes it possible to reduce the size and weight of the servo IC. It can be used to control.

Claims (1)

30HZ 기준 주파수를 발진하는 제1발진기(OSC1) 및 클럭펄스를 발진하는 제2발진기(OSC2)에 프리세트 2진 카운터(다)와 상기 제2발진기(OSC2)와 프리세트 2진 카운터(다) 사이에분주기(라)와 상기분주기(라)에는 업, 다운 스위치(Su), (SD)가 접속된 업/다운 2진 카운터(사)를 통하여 EEP ROM(바) 및 가산기(마)를 각각 연결 구성하고, 상기 가산기(마)는 프리세트 2진 카운터(다)를 통하여 통상의 캡스턴 모우터 위상 비교회로에 연결하여 트래킹이 변화하지 않는 안정된 제어동작을 유지할수 있도록 함을 특징으로 하는 푸쉬 스위치 방식을 채용한 VTR에서의 트래킹 제어회로.A preset binary counter (C), the second oscillator (OSC 2 ), and a preset binary counter ( 1 ) at the first oscillator (OSC1) oscillating the 30HZ reference frequency and the second oscillator (OSC 2 ) oscillating the clock pulse. Between) Divider and d) In the divider D, an EEP ROM (bar) and an adder (e) are connected to each other through an up / down binary counter (4) to which up, down switches (Su) and (SD) are connected. E) is connected to a normal capstan motor phase comparison circuit through a preset binary counter (c) to maintain a stable control operation with no change in tracking. Tracking control circuit.
KR2019880011437U 1988-07-13 1988-07-13 Tracking control circuit using push swiching for vtr KR910006576Y1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR2019880011437U KR910006576Y1 (en) 1988-07-13 1988-07-13 Tracking control circuit using push swiching for vtr
JP1989082131U JPH0284136U (en) 1988-07-13 1989-07-12
DE3923194A DE3923194A1 (en) 1988-07-13 1989-07-13 Synchronism control circuit arrangement for a video cassette recorder
GB8916108A GB2222008B (en) 1988-07-13 1989-07-13 Tracking control circuit for a video cassette recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880011437U KR910006576Y1 (en) 1988-07-13 1988-07-13 Tracking control circuit using push swiching for vtr

Publications (2)

Publication Number Publication Date
KR900003558U KR900003558U (en) 1990-02-07
KR910006576Y1 true KR910006576Y1 (en) 1991-08-26

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JP (1) JPH0284136U (en)
KR (1) KR910006576Y1 (en)
DE (1) DE3923194A1 (en)
GB (1) GB2222008B (en)

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JPS6126955A (en) * 1984-07-17 1986-02-06 Hitachi Ltd Auto-tracking device for magnetic recording and reproducing device
JPH0664790B2 (en) * 1985-08-28 1994-08-22 株式会社日立製作所 Automatic tracking device for magnetic reproducing device
JPH0782364B2 (en) * 1985-09-25 1995-09-06 日本電気株式会社 Error signal generator
JP2695830B2 (en) * 1988-03-31 1998-01-14 株式会社東芝 Tracking control device

Also Published As

Publication number Publication date
KR900003558U (en) 1990-02-07
GB8916108D0 (en) 1989-08-31
JPH0284136U (en) 1990-06-29
DE3923194C2 (en) 1993-09-09
GB2222008A (en) 1990-02-21
DE3923194A1 (en) 1990-01-18
GB2222008B (en) 1992-11-04

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