JPH0139248B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a successive approximation type AD converter.

[Conventional technology]

Conventionally, in measurement devices using multi-channel analyzers (MCAs), such as radiation measurement devices and single-photon fluorescence lifetime measurement devices, integral type AD converters have been mainly used, and successive approximation type AD converters have been used. The vessel was not used much.

This is because although successive approximation type AD converters are superior to integral type AD converters in terms of conversion speed,
This is because it is inferior in terms of differential nonlinearity (DNL).

Figure 1 is a schematic representation of the DNL pattern of a successive approximation type AD converter. Large non-linear errors (shaded areas in the figure) occur in modes where the bit pattern changes significantly (for example, 01111→
10000 part A). Furthermore, in this case, if a certain code (01111) has a negative nonlinear error, the code adjacent to this code (10000) often has approximately the same amount of positive nonlinear error.

Such nonlinear errors are mainly caused by external noise that enters the analog section of the converter during conversion, but in this type of converter that uses an IC, the IC
It can also be caused by internal clock noise.

Therefore, when processing speed is required, the integral type
A successive approximation type AD converter is used instead of an AD converter, but in order to eliminate the above-mentioned drawbacks, an IC with a number of bits greater than the number of data bits is used, and the lower bits are not used to match the required precision. The precision is improved by dropping the lower bits.

In other words, this dropping of lower bits means that DNL
If you want to keep the value below ±1%, use a 14-bit IC to capture 8-bit data, and
This is a method that does not use bits.

Figure 2 shows the code symmetry diagram obtained by this method,
In the illustrated example, the lower 1 bit is not used.

[Problem to be solved by the invention]

However, simply dropping the lower bits as described above has the same result as sequentially grouping two adjacent codes together, but in such grouping, the bits are dropped as in part A in Figure 1. There is still a part (part B) where the pattern changes significantly, and the DNL of the successive approximation type AD converter
It cannot be said that the characteristics have been improved.

The present invention is designed to detect two adjacent signals in a mode in which the bit pattern of a successive approximation type AD converter changes significantly.
This type of AD has two codes with opposite signs and approximately equal amounts of nonlinear errors.
Focusing on the DNL characteristics unique to converters, when grouping codes, we create pairs of combinations that have large bit pattern changes, and improve the performance of AD converters.
The purpose is to significantly improve DNL characteristics.

[Means to solve the problem]

In order to achieve the above object, the successive approximation type AD converter according to the present invention connects a digital memory to the output side of the AD converter, and sets the number of bits of the AD converter to be larger than the number of bits of the data output. In addition, in the digital memory, the
First, the code output from the AD converter is 2 ⁿ (however,
By shifting the codes in the positive direction by the number of codes excluding n (where n is the number of unused bits) and then dropping the lower bits, it is possible to ensure that there are pairs of codes that are grouped together that have significantly different bit patterns. The digital memory is characterized in that the data output having a predetermined number of bits is outputted from the digital memory.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 3, reference numeral 1 denotes an M-bit AD converter, to which an adder circuit 2 is connected to its input side, and a digital memory 3 such as a ROM is connected to its output side.

The adder circuit 2 adds the analog input V _IN and an offset voltage corresponding to the shift amount obtained by digitally shifting this analog input V _IN, and outputs an AD signal.
It is input to converter 1. The offset voltage is set as follows, for example. That is, when shifting the output of the M-bit AD converter 1 by p codes, the offset voltage E _OS when the full scale value of the analog input V _IN is V _FS is:
It is expressed as E _OS = p/2 ^M × V _FS .

The digital memory 3 converts the code output p of the AD converter 1 into 2 ⁿ (where n is the number of unused bits)
After shifting the code by the number of codes excluding
). Note that the code shift here refers to shifting the code in the direction in which the natural number increases, that is, in the positive direction.

For example, in this digital memory 3, of the M-bit code output p of the AD converter 1, the lower several bits are reduced and the necessary bits (for example, N bits) are stored.
This is a conversion table written such that the data output q has .

FIG. 4 shows a conversion table when the lower 1 bit is dropped after shifting by 1 code, and for comparison, a conventional code by simply dropping the lower bit is also shown.

That is, the numbers at the left end of this figure are decimal numbers from 0 to 31, and the columns are 5-bit binary codes corresponding to the decimal numbers. The columns are obtained by shifting the codes in the columns one code at a time in the positive direction. In the column, the code in the column is further lowered by 1.
The code after dropping the bits is shown. The column shows the code after two adjacent codes are grouped into one group. In other words, by shifting the code in the column by one code and then dropping the lower 1 bit,
The code shown in the column is obtained.

As can be seen from this figure, in the present invention, the number of bits used is reduced (dropping the lower bits) after shifting one code, so among the codes that are grouped together, there are always combinations in which the bit pattern changes significantly. (section C in the diagram). Therefore, the positive and negative nonlinear errors in this part cancel each other out, and the DNL characteristics are greatly improved.

Figures 5 to 7 each show the digital memory 3.
This shows an example of the conversion table written in the fifth page.
The figure shows the result after shifting 1 code and then dropping the lower 2 bits. Figure 6 shows the result after shifting 2 codes and dropping the lower 2 bits. Figure 7 shows the result after shifting 3 codes and dropping the lower 2 bits. It goes without saying that the procedures are the same as those shown in FIG. 4.

Also, in Figure 8, after 4 code shifts, the lower 2
This is a bad example, as it is the same as simply dropping the lower two bits.

Figure 9 shows the MCA output DNL characteristics measured using a 10-bit AD converter, and a in the same figure shows the 10-bit AD converter.
When the AD converter is used as it is, Figure b shows the case where the lower two bits are simply dropped and only the upper eight bits are used, and Figure c shows the case according to the present invention.

As is clear from this figure, the successive approximation type AD converter according to the present invention has significantly improved accuracy compared to conventional devices of this type.

FIG. 10 shows another embodiment of the present invention,
In this embodiment, an M-bit AD converter 1
The output of 1 is stored as it is in the M-bit MCA 12, and the data after the storage is added by the arithmetic unit 13 by grouping each adjacent channel (each adjacent code of the AD converter 11) into one group. ing. In this figure, 14 is an N-bit digital memory, 15 is an adder circuit, 16 is a data bus, and 17 is an address bus.

〔Effect of the invention〕

As explained above, according to the present invention, the number of bits of the AD converter is set larger than the number of bits of the data output, and the code output from the AD converter is first set to 2 ⁿ (where n is an integer). number of bits used)
Shift the code in the positive direction by the number of codes excluding
Next, by dropping the lower bits, we ensure that the codes that are grouped together include pairs of bit patterns that change significantly, which improves the DNL characteristics of the successive approximation type AD converter. The accuracy can be greatly improved. Therefore, the field of application of this type of AD converter can be expected to expand.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the DNL pattern of a conventional successive approximation type AD converter, and FIG. 2 is a code symmetry diagram when the lower bits are simply dropped. 3 to 9 show an embodiment of the present invention, FIG. 3 is a block diagram showing a configuration example of a successive approximation type AD converter according to the present invention, and FIGS. 4 to 8 are code shift diagrams, respectively. An explanatory diagram showing the conversion when lower bits are dropped after that. Figure 9 is the MCA output of a successive approximation type AD converter.
It is a DNL characteristic diagram. FIG. 10 is a block diagram showing another embodiment of the present invention. 1, 11...AD converter, 3, 14...digital memory, p...code output, q...data output.

Claims (1)

[Claims] 1. A digital memory is connected to the output side of the AD converter, the number of bits of the AD converter is set to be larger than the number of bits of the data output, and the code output from the AD converter is first read in the digital memory. 2 By shifting the code in the positive direction by the number of codes excluding ⁿ (where n is the number of unused bits) and then dropping the lower bits, 1
The sequential method is characterized in that the codes that are grouped together always include pairs of combinations of bit patterns that vary greatly, and the digital memory outputs data having a predetermined number of bits. Comparative AD
converter.