JPS6051332A - Ad converter of successive comparison type - Google Patents

Abstract

PURPOSE:To improve DNL characteristics and precision by shifting the code output of an AD converter and dropping lower bits of the code output to obtain a prescribed data output. CONSTITUTION:An analog input VIN and an offset voltage EOS are inputted to an adding circuit 2, and the output is outputted to an M-bit AD converter 1. A digital memory 3 shifts a code output (p) of the AD converter 1 by number of codes except 2<n> (n is the number of unused bits) and converts the shifted code output to data consisting of a prescribed number N of bits and outputs this data as a data output (q) (M=N+n). Data outputs whose lower one bits are dropped after one code shift are shown in a table. Since the number of used bits is reduced (lower bits are dropped) after one code shift, there are certainly a pair of data outputs having a reat difference in bit pattern in one group. Consequently, positive and negative nonlinear errors in this part are cancelled by each other to improve DNL characteristics.

Description

[Detailed description of the invention] The present invention relates to a successive approximation type AD converter.

Traditionally, multi-channel analyzers (M
In measuring devices using CA), a 1-minute ADf converter was mainly used, and a successive approximation AD converter was rarely used.

This means that the successive L1; comparison type A11 converter is the converter 7i
This is because although it is superior to the converter in point (7), it is inferior in terms of differential nonlinearity (DNL).

Figure 1 shows the successive approximation tlI'HA I) Converter D N
1. The pattern is schematically expressed as [, but a large nonlinear error (in the figure, thread 1 and 814) occurs in a mode where the bit pattern changes greatly] (for example, 0
1111-10000 A1 police 1<). In addition, in this case, if there is a non-linear error of the mouth at a certain code (Ollll), the code (10000
) often has a curvature error of 1 [of approximately the same M.

Such a non-linear fA difference is mainly caused by foreign noise introduced into the analog section of the converter during conversion.
In this type of Y converter using an IC, the noise is also generated by clock noise inside the IC.

Therefore, when lL processing speed is required, the integral type ADf
In place of the converter, a successive IL comparison type A I) converter is used, but in order to eliminate the above-mentioned drawbacks, an IC with a data pitch of 1 or higher is used, and the lower bits are converted to the required precision. In order to improve the accuracy, so-called lower bits are removed so that they are not used.

That is, when trying to suppress D N L to ±1% or less,
A 14-bit IC is used to capture 8-bit data,
The method is to use the lower 6 bits [7].

FIG. 2 shows a code table according to this method, and the lower 1 bit is not used in the example shown.

This simple omission of lower bits] 7 has the same result as sequentially grouping two adjacent codes together, but in such grouping, A
There still exists a part (part B) in which the bit pattern changes significantly as in the part B, and it cannot be said that the DNL characteristics of the successive approximation 41 AD converter have been improved.

The present invention is an AD converter of this type in which two adjacent codes in a mode in which the bit pattern of a successive approximation AD converter changes greatly have opposite signs and nonlinear errors of approximately the same amount. * Unique r) NI characteristic: 17. When grouping codes, 1. Al
The purpose is to significantly improve the DNL characteristics of the l' converter.

The following is an example of the 1111 fire b case based on the drawings.
'11 In the 3rd figure, 1 is M-Pill-(7) A
I) Addition circuit 2 on input side with f converter, output 1111J
A digital memory 3 such as ROM is connected to each.

The adder circuit 2 adds the analog human power VHN and the offset voltage corresponding to the shift value obtained by digitally shifting the analog human power VAN and inputs the result to the A, Dfl back unit 1. The offset voltage is set, for example, as follows. That is, when shifting the output of the M-bit ADi converter l by p code, the offset voltage Eos when the full scale value of the analog human input VIN is VFS is: p
is code-shifted by the number of codes excluding 2 (where n is the number of unused bits), and then converted as data of predetermined bits &N, and this is output as data LJi force q. (M=N+n.) For example, in this digital memory 3, out of the M-bit output p of the ADf converter 1,
A conversion table is written in which the number of bits is reduced by using the lower bits (one or more bits) as unused bits, and the data output q has the necessary bits (for example, N bits).

FIG. 4 shows l code shift 1. After that, the conversion table for dropping the lower one bit is shown, and the conventional code for simply dropping the lower bit for row comparison is also shown.

As can be seen from this figure, in the present invention, the number of bits used is reduced after shifting one code (the lower bits are dropped), so there are always combinations of bit patterns that change significantly in the codes that are grouped together. They will come in pairs (C in the diagram). Therefore, the positive and negative nonlinear errors in this part cancel each other out, and the DNL characteristic is large 1]
will be improved.

Figures 5 to 7 show examples of conversion tables hidden in the digital memory 3, respectively. Figure 5 is a table in which the lower two bits are dropped after shifting one code, and Figure 6 is a table in which the lower two bits are dropped after shifting one code. is shifted by 2 codes and then the lower 2 bits are dropped, while FIG. 7 is shifted by 3 codes and then the lower 2 bits are dropped.

Furthermore, although FIG. 8 shows a case in which the lower two bits are dropped after a four-code shift, this is the same as simply dropping the lower two bits, which is a bad example.

@9 Figure shows M measured using a lO bit AI) converter.
In the CA output DNL characteristic diagram, (a) is when a 10-bit AD converter is used as is, (b) is when the lower 2 bits are simply dropped and only the 1-1 upper 8 bits are used, (C ) respectively indicate cases according to the present invention.

As is clear from this figure, successive approximation 1 according to the present invention
9! The accuracy of the AD converter is greatly improved compared to conventional devices of this type.

FIG. 10 shows another embodiment of the present invention, in which the output of the M-bit AD converter 11 is directly accumulated in the M-bit MCA12, and the accumulated data is processed by the arithmetic unit 13. Adjacent channels (adjacent codes of the AD converter 11) are grouped and added together.

In the figure, 14 is an N-bit digital memory;
15 is an adder circuit, 16 is a data bus, and 17 is an address bus.

As described in detail below, the present invention connects a digital memory to the output side of the ADf converter, and this digital memory first code-shifts the code output of the AD converter, and then shifts the code output to the lower bits. 1+1j I- so as to output a predetermined data output.

Therefore, the DNL characteristics of the successive approximation type AD converter can be improved, and its accuracy can be greatly improved. Therefore, it is expected that the applications of this type of An converter47) will be expanded.

[Brief explanation of drawings]

Figure 1 shows the conventional successive approximation type AI) switching device.
The theory 51 column diagram showing the pattern, Figure 2 is a code table when the lower r17 bits are dropped to q[ [7, Figure 3 is the successive approximation according to the present invention, ! +,! Block diagrams showing configuration examples of I A D conversion 2:4, @Figure 4 to Figure 8 1. ．． The conversion table when the tens bit is dropped after one code shift, Figure 9 shows the MCA output DNI-characteristic diagram of the AD converter for successive approximation, and Figure 10 shows the other structure 1+V, I! It is a block diagram showing A'. 1.11...AI) Converter, 3, 14 ・Digital memory, p・Code output, q ・Data output 0- to F) <
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-0t-fginv1-v-('lF) Figure 5 31 1 11 1 1 Honryo A Figure 6 Figure 7 Figure 8 6 51NrlOJ 51NrlOJ Procedural amendment (method) □ 1. Indication of the case 1988 Patent Application No. 160023 2 Title of the invention Successive approximation type AD converter 3 Relationship with the case of the person making the amendment Patent applicant 4, agent 5, date of amendment order November 29, 1980 (shipment date) 6. Number of inventions increased by amendment 7. Column for brief explanation of drawings of specification subject to amendment (1) Akedomari fl-L! ! No. 800: Change the 3-line 1-code table to 17 t1 in code symmetry diagram 1. Ba TiEI, size.

Claims (1)

[Claims] A digital memory is connected to the output side of the AD converter, and the
The number of bits of the converter is set larger than the number of bits of the data output, and the digital memory
A successive approximation device characterized in that the code output from the converter is code-shifted by the code excluding 2 (where n is an unused bit &) and then output as data output having a predetermined number of bits. type AD converter.