JP3151992B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D (analog / digital) converter for converting an analog signal into a digital signal, and more particularly to a noise shaping type A / D converter using a .DELTA..SIGMA. (Delta sigma) modulation technique. It is about.

[0002]

2. Description of the Related Art A noise-shaping A / D converter has been reported as one type of A / D converter. FIG. 11 shows an A / D converter of this type which has been reported conventionally.
This will be described with reference to FIG. This technology is described in "IEICE Technical Report CS83-198".

FIG. 11 is a block diagram showing an example of a conventional A / D converter. In FIG. 11, reference numeral 10 denotes a subtractor;
It outputs the difference between two input analog signals. An analog input from the outside is input to the addition terminal of the subtractor 10. An integrator 11 accumulates and outputs analog signals output from the subtractor 10.
Reference numeral 12 denotes a quantizer which converts an analog signal output from the integrator 11 into a digital signal and outputs the digital signal. Here, it is assumed that 2-bit (p = 4) quantization is performed, and the correspondence between input and output is shown in (Table 1).

[0004]

[Table 1]

Reference numeral 110 denotes a D / A converter, which is a quantizer 1
2 is converted to an analog signal. D / A converter 11
The output of 0 is input to the subtraction terminal of the subtractor 10.

The A / D converter shown in FIG. 11 is known as a noise-shaping A / D converter having a primary characteristic, and an output Y with respect to an input X is represented by (Equation 1).

[0007]

(Equation 1)

In the A / D converter shown in FIG. 11, the sampling frequency (FS) is 64 fs and the input signal frequency is about 0.02.
FIG. 12 shows a result obtained by computer simulation of an output signal spectrum when fs and an input signal level are set to 0 dB. For simplicity, the band from 0 to 2 fs is shown here. As shown in FIG. 12, a dynamic range (DR) of about 58 dB in a signal band of 0 to fs / 2.
Is obtained.

[0009]

However, in the configuration shown in FIG. 11, it is considered that the D / A converter 110 requires at least the accuracy of the digital signal to be obtained. For example, assume that the output of the D / A converter 110 has a 2% error as shown in (Table 2).

[0010]

[Table 2]

FIG. 13 shows a result obtained by computer simulation of the output signal spectrum at this time. For simplicity, the band from 0 to 2 fs is shown here. As shown in FIG. 13, generation of large harmonic distortion is observed, and the dynamic range is significantly deteriorated to about 45 dB in the signal band of 0 to fs / 2.

This is because the output of the D / A converter 110 has non-linearity. Therefore, there is a problem that a high-precision device must be used for the D / A converter 110 in order to obtain a high dynamic range.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an A / D converter that does not require a highly accurate D / A converter 110.

[0014]

In order to achieve this object, the present invention has the following arrangement. (1) A subtractor that receives two analog signals and outputs the difference between the two, an integrator that integrates the analog output of the subtractor, and a quantizer that converts the output of the integrator into a digital signal. A decoder for converting the digital output of the quantizer into a 1-bit signal sequence corresponding to the value, a 1-bit D / A converter sequence for converting the output of the decoder to an analog signal, and the 1-bit D / A converter. An analog adder that integrates the output of the A converter string and outputs the result to the subtraction terminal of the subtractor, inputs an analog input to the addition terminal of the subtractor, outputs a digital output from the quantizer,
An A / D conversion device is provided in which the output of the decoder is an output such that the number of 1-bit signals corresponding to the output value of the quantizer circulates.

Also, the present invention provides: (2) at least (p−1) 1 outputs corresponding to signals having p values (p is an integer) output from the quantizer, Outputting the bit signal sequence, and allocating the 1-bit signal sequence cyclically so that the allocation start position is the position next to the final allocation position of the 1-bit signal sequence one sample data before. The A / D converter of (1) is used.

Also, the present invention provides: (3) The decoder outputs at least (p-1) ones corresponding to signals having p values (p is an integer) output from the quantizer. (1) wherein a bit signal sequence is output, and the allocation start position of the 1-bit signal sequence is cycled by a predetermined number for each sample data.
A / D converter.

The present invention also provides: (4) at least 2 (p-1) outputs of the decoder corresponding to signals having p values (p is an integer) output from the quantizer. A 1-bit signal sequence is output, the assignment of the 1-bit signal circulates, and
The A / D of (1) above, wherein none of the signals of the bit signal sequence is continuously assigned to two sample data.
Conversion device.

The present invention also provides: (5) a first subtractor that receives two analog signals and outputs a difference between the two, and a first integrator that integrates an analog output of the first subtractor. A second subtractor that uses an analog output of the first integrator as an input to an addition terminal, a second integrator that integrates an analog output of the second subtractor, and a second integrator. A quantizer for converting an output to a digital signal, a decoder for converting a digital output of the quantizer to a 1-bit signal sequence corresponding to the value of the signal,
A 1-bit D / A converter train for converting the output of the decoder into an analog signal, respectively, and an output of the 1-bit D / A converter train is integrated and output to the subtraction terminals of the first and second subtractors. An analog input to an input terminal of the first subtractor, a digital output from the quantizer, an output of the decoder,
The A / D converter is configured to output such that the number of 1-bit signals corresponding to the output value of the quantizer circulates.

The present invention also provides: (6) at least (p−1) 1 outputs of the decoder corresponding to signals having p values (p is an integer) output from the quantizer. Outputting the bit signal sequence, and allocating the 1-bit signal sequence cyclically so that the allocation start position is the position next to the final allocation position of the 1-bit signal sequence one sample data before. The A / D converter of (5) is used.

The present invention also provides: (7) at least (p−1) 1 outputs of the decoder corresponding to signals having p values (p is an integer) output from the quantizer. (5) wherein a bit signal sequence is output, and the allocation start position of the one bit signal sequence is cycled by a predetermined number for each sample data.
A / D converter.

According to the present invention, (8) the decoder outputs at least 2 (p-1) signals corresponding to signals having p values (p is an integer) output from the quantizer. A 1-bit signal sequence is output, the assignment of the 1-bit signal circulates, and
The A / D of (5) above, wherein none of the signals of the bit signal sequence is allocated continuously for two sample data.
Conversion device.

[0022]

According to the present invention, according to the present invention, the output of the quantizer is allocated so that the decoder circulates to a plurality of 1-bit D / A converters. By performing the conversion, the correlation between the output value of the quantizer and a specific 1-bit D / A converter is eliminated.
As a result, even when the output between the 1-bit D / A converters varies, generation of distortion and noise in the signal band can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an A / D converter according to the present invention. In FIG. 1, 10 is a subtractor,
11 is an integrator and 12 is a quantizer.
Has the same configuration and function as those shown in FIG. 13 is D /
It is an A converter, and converts the output of the quantizer 12 into an analog signal. The output of the D / A converter 13 is input to the subtraction terminal of the subtractor 10.

A decoder 14 outputs three (= p-1) 1-bit signals corresponding to the digital signals output from the quantizer 12. Reference numeral 15 denotes a 1-bit D / A converter train, which includes all the uniform 3 bits from the first D / A converter (DAC-1) to the third D / A converter (DAC-3).
(= P-1) 1-bit D / A converters.
Reference numeral 16 denotes an analog adder, which synthesizes three analog signals output from the 1-bit D / A converter train 15 and outputs the result as an analog signal.

The A / D converter shown in FIG. 1 is a noise-shaping A / D converter having a primary characteristic, and an output Y with respect to an input X is represented by (Equation 1) as in FIG.

FIG. 2 shows an example of a specific circuit of the D / A converter 13 shown in FIG. In FIG. 2, a D / A converter 13, a decoder 14, a 1-bit D / A converter train 15, and an analog adder 16 correspond to FIG. An inverter 20 inverts a 1-bit input signal and outputs the inverted signal. 21,
22, a resistor; and 23, an operational amplifier (operational amplifier). 2, the non-inverting input terminal of the operational amplifier 23 is grounded, and the inverting input terminal is a virtual ground point. The one-bit input signal is connected to the inverting input terminal of the operational amplifier 23 via the inverter 20 and the resistor 21, and further connected to the output terminal of the operational amplifier 23 via the resistor 22. That is, a current adding circuit is constituted by the resistors 21 and 22.
Now, assume that the resistance value of the resistor 21 of the DAC-1 is R1,
When the resistance value of the resistor 21 of R-2 is R2, the resistance value of the resistor 21 of DAC-3 is R3, and the resistance value of the resistor 22 is Rf, the analog output voltage Eo is obtained by (Equation 2). .

[0028]

(Equation 2)

Here, since all the 1-bit D / A converters 15 have a uniform configuration, the resistance value of the resistor 21 is also R1 = R2 =
R3, the output of the operational amplifier 23, that is, the analog output is "0" of the 1-bit signal output from the decoder 14.
(That is, a voltage value proportional to the number of signals in which the output of the inverter 20 is "1").

In an actual circuit, the 1-bit D / A converter 15
Cannot be manufactured completely uniformly, and there is some relative error. In this case, (Equation 2)
As is clear from FIG. 7, a voltage value depending on the position as well as the number of "0" signals among the output signals of the decoder 14 is output.

FIG. 3 shows an example of the decoder 14 shown in FIG.
In FIG. 3, reference numeral 30 denotes a pointer for outputting the remainder of the accumulated value of the input signal. Reference numeral 31 denotes a ROM (read-only memory) which outputs 3-bit data corresponding to an address where the input signal is at the lower level and the output of the pointer 30 is at the upper level.

The operation of FIG. 3 will be described.
0 accumulates the input signal, that is, the 2-bit signal ("00" to "11") output from the quantizer 12 in FIG. 1, obtains the remainder of 3, and outputs the remainder. Therefore, there are three types of output, 0 to 2. Next, an address where the input signal is lower and the output signal of the pointer 30 is higher is input to the ROM 31 to obtain 3-bit data. The 3-bit data is a 1-bit signal 3
It represents an individual. The relationship between the address (decimal number) and the data (binary number) at this time is shown in (Table 3).

[0033]

[Table 3]

Referring to Table 3, 3-bit data is "1" in the lower order of the address, that is, the number indicated by the numerical value of the input signal, and the sum of each bit is equal to the input signal. In addition, the upper part of the address, that is, the value of the output signal of the pointer 30 is shifted to the left by the amount indicated, and the overflowing digits are circulated so as to appear from the right. By defining the ROM 31 as shown in (Table 3), data is output as shown in (Table 4), for example.

[0035]

[Table 4]

As can be seen from (Table 4), "1" as indicated by the numerical value of the input signal is output so as to go around the 3-bit data, which means that the numerical value of the input signal and the 3-bit data are output. This indicates that there is no correlation with the particular bit. For this reason, even when the output of the 1-bit D / A converter 15 to which the 3-bit data is connected varies, the generation of distortion and noise in the signal band can be reduced.

In the A / D converter shown in FIG. 1, 1-bit D / A
The output of the converter train 15 is, for example, ± 2 as shown in (Table 5).
FIG. 4 shows a result obtained by simulation of an output signal spectrum in the case of having a% variation. For simplicity, signals from 0 to 2 fs are shown here.

[0038]

[Table 5]

As shown in FIG. 12, the D / A converter 1
In the case where 3 is ideal (no error), a dynamic range of about 58 dB is obtained in the signal band of 0 to fs / 2, but the dynamic range in FIG. It can be seen that although the output of the bit D / A converter array 15 has a variation of ± 2%, the performance degradation is slight. On the other hand, in the case of an output in which data does not circulate, for example, when the output of the pointer 30 is fixed to 0 regardless of the input, the output of the D / A converter 13 is equivalent to (Table 2). In this case, as shown in FIG. 13, a large harmonic distortion is generated as compared with FIG. 4, and the dynamic range is greatly deteriorated.

In this case, the operation of the pointer 30 is changed to a 2-bit signal ("0") output from the quantizer 12 in FIG.
0 "to" 11 "), and the remainder of 3 is obtained and output. However, as another embodiment of the present invention, the operation of the pointer 30 is set to 0 to 2 regardless of the output of the quantizer 12. May be repeatedly output in order. The result of simulation of the output signal spectrum in this case is shown in FIG.
Shown in As shown in FIG. 5, although there is an increase in noise as compared to FIG. 4, the harmonic distortion that has occurred in the case of FIG. 13 is no longer seen, and the dynamic range is improved to about 54 dB. . In particular, in this method, the operation of the pointer 30 only needs to repeatedly output the signals of 0 to 2 in order, and the operation of the pointer 3
0 can be reduced in circuit scale.

Next, still another embodiment of the present invention will be described. Generally, when the 1-bit D / A converter outputs "1", the output value differs slightly between when the immediately preceding data is "1" and when it is "0". This is because the previous value affects the output value at the data change point. In order to avoid this, the data immediately before "1" must be always "0", that is, "1" should not be output from the 1-bit D / A converter for two consecutive sample data. I just need.

By applying this principle to the A / D converter of FIG. 1, the A / D converter is constructed as follows. Note that D
Blocks other than the / A converter 13 are the same as those in the configuration and operation described above, and a description thereof will be omitted.

First, with respect to the decoder 14, the operation of the pointer 30 in FIG. 3 is such that the 2-bit signal output from the quantizer 12 is accumulated, the remainder of 6 is obtained and output. Therefore, there are six types of outputs, 0 to 5. Next, an address in which the input signal is lower and the output signal of the pointer 30 is higher is input to the ROM 31 to obtain 6 (= 2 (p-1))-bit data. The 6-bit data represents six 1-bit signals, and the address (1
(Table 6) shows the relationship between 0 (base number) and data (binary number).

[0044]

[Table 6]

To explain Table 6, the 6-bit data is "1" as indicated by the lower order of the address, that is, the value of the input signal, and the sum of each bit is equal to the input signal. Also, the lower part of the address, that is, the value of the output signal of the pointer 30 is shifted to the left by the amount indicated, and the overflowing digits are circulated so as to appear from the right. As shown in Table 6, R
By defining the OM 31, data is output as shown in, for example, (Table 7).

[0046]

[Table 7]

As can be seen from (Table 7), "1" as indicated by the numerical value of the input signal is output so as to circulate through the 6-bit data. Indicates that there is no correlation with the particular bit of Further, since the maximum value of the input signal is 3, 6-bit data, that is, all six 1-bit signals do not output "1" continuously for two sample data.

The 6-bit signal obtained in this way is input to the 1-bit D / A converter train 15 and is output as an analog output via the analog adder 16. However, 1-bit D /
The A converter row 15 has 6 (= 2 (p−1)) 1-bit D bits.
/ A converter.

Next, still another embodiment of the present invention will be described. FIG. 6 is a block diagram showing another embodiment of the A / D converter according to the present invention. In FIG. 6, 10 is a subtractor,
Reference numeral 11 denotes an integrator, 12 denotes a quantizer, and 13 denotes a D / A converter, each having the same configuration and function as those shown in FIG. A subtractor 60 and an integrator 61 have the same configuration and function as the subtractor 10 and the integrator 11, respectively.

The operation of FIG. 6 will be described. First, an analog input from the outside is input to an addition terminal of a subtractor 60, and an analog signal output from the subtracter 60 is accumulated by an integrator 61 and output. The signal is input to the addition terminal of the subtractor 10. Subsequently, the analog signal output from the subtracter 10 is accumulated and output by the integrator 11, and the output is converted from an analog signal to a digital signal by the quantizer 12 to become a digital output. The digital output is D /
The signal is also input to the A converter 13, converted to an analog signal, and input to the subtraction terminals of the subtractor 60 and the subtractor 10.

The A / D converter shown in FIG. 6 is a noise-shaping A / D converter having a secondary characteristic, and the output Y with respect to the input X is represented by the following equation (3).

[0052]

(Equation 3)

In the A / D converter shown in FIG. 6, the sampling frequency (FS) is 64 fs and the input signal frequency is about 0.02 f.
FIG. 7 shows the results obtained by computer simulation of the output signal spectrum when s and the input signal level were set to 0 dB. For simplicity, the band from 0 to 2 fs is shown here. As shown in FIG. 7, a dynamic range (DR) of about 84 dB is obtained in a signal band of 0 to fs / 2.

Now, the D / A converter 13 in FIG.
Assuming that the output signal spectrum at this time has a 2% error as shown in (Table 2) as in the case of / A converter 110, the output signal spectrum at this time is obtained by computer simulation as shown in FIG.
become that way. For simplicity, the band from 0 to 2 fs is shown here. As shown in FIG. 8, generation of large harmonic distortion is observed, and the dynamic range is significantly degraded to about 48 dB in the signal band of 0 to fs / 2.

On the other hand, the D / A converter 13 operates as shown in FIG.
/ A converter 13 and the RO of decoder 14
The input / output relationship of M31 is shown in (Table 3), and the output of the 1-bit D / A converter array 15 is ± 30% as shown in (Table 5).
When there is a variation of 2%, the output signal spectrum is as shown in FIG. For simplicity, signals from 0 to 2 fs are shown here. As shown in FIG. 9, the dynamic range is about 83 dB, and it can be seen that the performance degradation is slight despite the variation of ± 2% in the output of the D / A converter array 15.

As still another embodiment of the present invention,
In the D / A converter 13 of FIG. 6, similarly to the D / A converter 13 of FIG. 1, the operation of the pointer 30 of FIG. It may be output. FIG. 10 shows the result of simulation of the output signal spectrum in this case. FIG.
As can be seen from FIG. 9, although there is an increase in noise as compared to FIG. 9, the harmonic distortion that has occurred in the case of FIG. 8 is no longer seen, and the dynamic range is improved to about 56 dB.

Further, as another embodiment of the present invention, RO
If the input / output relationship of M31 is shown in (Table 6),
As can be seen from (Table 7), "1" as indicated by the numerical value of the input signal is output so as to circulate through the 6-bit data, and the correlation between the numerical value of the input signal and a specific bit of the 6-bit data is eliminated. In addition, since the maximum value of the input signal is 3, 6-bit data, that is, all six 1-bit signals can be prevented from outputting "1" continuously for two sample data.

With the above-described configuration, an A / D conversion apparatus with little distortion or noise in the signal band can be realized even when the outputs of the 1-bit D / A converter rows 15 vary as described above. . Further, since the 1-bit data string output from the decoder 14 does not output "1" continuously for two data, the output of the 1-bit D / A converter 15 is not affected by the immediately preceding data, and the high-precision data is output. D / A conversion can be performed, and therefore, an A / D converter in which generation of distortion and noise in a signal band is small can be realized.

As described above, the A / D converter is constituted. Here, the A / D converter has been described with reference to FIGS. 1 and 6. However, the A / D converter may have a different configuration as long as it has the same functions and characteristics. Such a device may be used.
Further, the configuration of the decoder 14 shown in FIG.
The OM data and the like are examples for explanation, and are not limited to this. Further, for the p outputs of the quantizer 12, the number of output bits of the decoder 14 (that is, the number of 1-bit D / A converters 15) is (p-1),
Although described as (p-1), these are the minimum cases, and may be more than this depending on the circuit configuration and the like.

[0060]

As described above, in the A / D converter of the present invention, the decoder 14 outputs the output of the quantizer 12 to a plurality of 1
Since the data is allocated to the bit D / A converters 15 in a cyclic manner, there is no correlation between the output value of the quantizer 12 and the specific 1-bit D / A converter 15, and each 1-bit D / A converter has Even if the output varies, the generation of distortion and noise in the signal band can be reduced, so that a high-precision A / D converter 13 is not required for the D / A converter 13 and is easy to manufacture. It has an excellent feature that a D conversion device can be realized.

The A / D converter of the present invention is a noise-shaping type A / D converter having a secondary characteristic, so that the A / D conversion precision can be further improved. The effect of reducing the occurrence of distortion and noise in the signal band with respect to the variation existing in the output of the bit D / A converter 15 becomes more remarkable. Further, in order to obtain A / D conversion accuracy equivalent to that of the primary noise shaping type A / D converter, a lower sampling frequency is required, so that a device having a low operation speed can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an A / D converter according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of a D / A conversion circuit 13 in FIG.

FIG. 3 is a block diagram illustrating an example of a decoder 14 in FIG.

4 is an output signal spectrum of the A / D converter of FIG. 1 obtained by computer simulation.

FIG. 5 is an output signal spectrum when the operation of the pointer 30 in the A / D converter of FIG. 1 is such that signals 0 to 2 are repeatedly output in order regardless of the output of the quantizer 12;

FIG. 6 is a block diagram showing another embodiment of the A / D converter according to the present invention.

7 is an output signal spectrum of the A / D converter of FIG. 6, which is obtained by computer simulation.

8 is an output signal spectrum when the D / A converter 13 has an error of 2% as shown in (Table 2) in the A / D converter of FIG.

FIG. 9 shows a D / A converter 13 in the A / D converter of FIG.
Shows the input / output relationship of the ROM 31 of the decoder 14 (Table 3).
And the output signal spectrum when the output of the 1-bit D / A converter array 15 has a variation of ± 2% as shown in (Table 5)

FIG. 10 shows a D / A converter 13 in the A / D converter of FIG.
Operates the pointer 30 of the decoder 14 with the quantizer 12
Output signal spectrum when signals 0 to 2 are repeatedly output in order regardless of the output

FIG. 11 is a block diagram showing an example of a conventional A / D converter.

FIG. 12 is obtained by computer simulation.
Output signal spectrum of the A / D converter of FIG.

FIG. 13 is obtained by computer simulation.
Output signal spectrum of A / D converter in FIG. 11 when output of D / A converter 110 has an error of 2%

[Explanation of symbols]

 10, 60 Subtractor 11, 61 Integrator 12 Quantizer 13 D / A converter 14 Decoder 15 1-bit D / A converter (column) 16 Analog adder 20 Inverter 21, 22, Resistor 23 Operational amplifier (Operational amplifier) 30 pointer 31 ROM (read only memory)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-335963 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-3/00

Claims (5)

(57) [Claims] 1. A subtractor that receives two analog signals and outputs a difference between the two, an integrator that integrates an analog output of the subtractor, and a quantizer that converts an output of the integrator into a digital signal. A decoder for converting a digital output of the quantizer into a 1-bit signal sequence corresponding to the value of the signal; a 1-bit D / A converter sequence for respectively converting the output of the decoder into an analog signal; An analog adder that integrates the output of the D / A converter train and outputs the result to the subtraction terminal of the subtractor, wherein an analog input is input to the addition terminal of the subtractor, and a digital output is output from the quantizer. The output of the decoder is an A / D output such that a number of 1-bit signals corresponding to the output value of the quantizer circulates.
Conversion device. 2. A first subtractor that receives two analog signals and outputs a difference between the two, a first integrator that integrates an analog output of the first subtractor, and the first integrator. A second subtractor having an analog output of the second input to an addition terminal, a second integrator for integrating an analog output of the second subtractor, and converting an output of the second integrator into a digital signal A decoder for converting the digital output of the quantizer into a 1-bit signal sequence corresponding to the value of the signal; and a 1-bit D / A converter sequence for converting the output of the decoder to an analog signal, respectively. And the output of the 1-bit D / A converter train is integrated into the first
And an analog adder for outputting to a subtraction terminal of the second subtractor, wherein an analog input is inputted to an addition terminal of the first subtractor,
A / D which outputs a digital output from the quantizer, and sets an output of the decoder as an output such that a 1-bit signal of a number corresponding to the output value of the quantizer circulates.
Conversion device. 3. The decoder outputs at least (p-1) 1-bit signal sequences corresponding to signals having p values (p is an integer) output from the quantizer. 3. A / C according to claim 1, wherein the allocation is cyclically performed so that the allocation start position of the one-bit signal sequence is the position next to the final allocation position of the one-bit signal sequence one sample data before. D conversion device. 4. The decoder outputs at least (p-1) 1-bit signal strings corresponding to signals having p values (p is an integer) output from the quantizer. 3. The A / D converter according to claim 1, wherein the allocation start position of the one-bit signal sequence is cycled by a predetermined number for each sample data. 5. The decoder outputs at least 2 (p−1) 1-bit signal strings corresponding to signals having p values (p is an integer) output from a quantizer. 3. The A / D conversion apparatus according to claim 1, wherein the 1-bit signal allocation is cyclic, and none of the signals of the 1-bit signal sequence are continuously allocated to two sample data.