JPH0138370B2 - - Google Patents
Info
- Publication number
- JPH0138370B2 JPH0138370B2 JP57141367A JP14136782A JPH0138370B2 JP H0138370 B2 JPH0138370 B2 JP H0138370B2 JP 57141367 A JP57141367 A JP 57141367A JP 14136782 A JP14136782 A JP 14136782A JP H0138370 B2 JPH0138370 B2 JP H0138370B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polyimide resin
- film
- etching
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000002952 polymeric resin Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229920003002 synthetic resin Polymers 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 description 27
- 239000009719 polyimide resin Substances 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 239000011521 glass Substances 0.000 description 17
- 238000001259 photo etching Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に多
層配線構造を有する半導体装置の層間絶縁膜とし
て少なくとも高分子樹脂膜と無機絶縁膜からなる
多層絶縁膜を用いた際のスルーホール形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly when a multilayer insulating film consisting of at least a polymer resin film and an inorganic insulating film is used as an interlayer insulating film of a semiconductor device having a multilayer wiring structure. The present invention relates to a hole forming method.
一般に、半導体装置が高密度化されるのに伴つ
て、電極配線の多層化、パターン幅の微少化が要
求される。その為、例えばMOS−ICに於いて、
第１図に横断面図で示すように、シリコン基板１
上に設けられたMOSトランジスタ２の電極に接
続される１層目メタル３と、その上層部の２層目
メタル４との間にポリイミド樹脂５を介在させ層
間絶縁膜を形成し、多層配線構造にすることによ
つて高密度化を計ることが考えられる。なお、こ
こで６はSiO2である。このポリイミド樹脂等の
高分子樹脂を、多層配線の層間絶縁膜として使用
することは従来から知られており、ポリイミド樹
脂等の樹脂は、無機絶縁膜、例えばSiO2膜、
PSG膜、SiN膜等のガラス系絶縁膜に比べ、ステ
ツプカバリツジが良い、クラツクが起こりにくい
等の長所がある反面、ガラス系の絶縁膜に比して
吸湿性が大きく、樹脂材料でるが故に不純物を含
有しており、更に分極率が大きい為２層目メタル
の電位関係によつては、シリコン基板の表面反転
を引き起こしMOSトランジスタのスレツシユホ
ールド電圧を変化させる等、ICとしての信頼性
が悪くなるという欠点があつて、特にMOS−IC
に使用することはできないとされている。 Generally, as semiconductor devices become more densely packed, there is a demand for multi-layered electrode wiring and smaller pattern widths. Therefore, for example, in MOS-IC,
As shown in the cross-sectional view in FIG.
A polyimide resin 5 is interposed between the first layer metal 3 connected to the electrode of the MOS transistor 2 provided above and the second layer metal 4 on the upper layer to form an interlayer insulating film, thereby creating a multilayer wiring structure. It is conceivable to increase the density by increasing the density. Note that 6 is SiO 2 here. It has been known for a long time to use polymer resins such as polyimide resins as interlayer insulating films for multilayer interconnections.
Compared to glass-based insulating films such as PSG films and SiN films, it has advantages such as better step coverage and less chance of cracking. Contains impurities and has a high polarizability, so depending on the potential relationship of the second layer metal, it may cause surface inversion of the silicon substrate and change the threshold voltage of the MOS transistor, reducing the reliability of the IC. It has the disadvantage that it deteriorates, especially in MOS-IC.
It is said that it cannot be used for.
また、最近、パツケージが低価格の樹脂封止型
となつて、なおその形状が小型化するにつれて、
この本質的に水を透過するパツケージでも、耐湿
性のある多層配線構造であることが強く要望され
るに至つている。 In addition, recently, as packages have become low-cost resin-sealed types and their shapes have become smaller,
Even in this essentially water-permeable package, there is a strong demand for a moisture-resistant multilayer wiring structure.
そこで、層間絶縁膜を、第２図にその横断面図
を示す如く、ガラス系絶縁膜７とポリイミド樹脂
５を重ねて２層構造にすれば、上述の欠点を克服
しまたニーズに応えることができる。すなわち、
ガラス系絶縁膜を下層に使用することによつ
て、ポリイミド樹脂の吸湿による水分および樹脂
に含まれている不純物がシリコン基板に到達する
ことを防ぐことができる。ポリイミド樹脂の分
極による影響を、下層のガラス系絶縁膜によつて
半減することができる。ガラス系絶縁膜のステ
ツプカバリツジの悪さおよびクラツク等は上層の
ポリイミド樹脂によつて平坦化し、又、クラツク
を埋めることにより、層間絶縁膜の完全性を飛躍
的に向上することができる。又、一般に絶縁膜の
欠陥率の減少には、多層構造が有効であることが
知られており、従つて、この第２図に示す如く構
成すれば、LSIの歩留の向上に対して有効であ
る。 Therefore, if the interlayer insulating film is made into a two-layer structure by stacking the glass-based insulating film 7 and the polyimide resin 5, as shown in the cross-sectional view of FIG. 2, the above-mentioned drawbacks can be overcome and the needs can be met. can. That is,
By using a glass-based insulating film as the lower layer, it is possible to prevent moisture due to moisture absorption of the polyimide resin and impurities contained in the resin from reaching the silicon substrate. The influence of polarization of polyimide resin can be halved by the lower glass-based insulating film. Poor step coverage and cracks in the glass-based insulating film are flattened by the upper layer of polyimide resin, and by filling the cracks, the integrity of the interlayer insulating film can be dramatically improved. In addition, it is generally known that a multilayer structure is effective in reducing the defect rate of insulating films. Therefore, if the structure is as shown in Figure 2, it is effective in improving the yield of LSI. It is.
しかるに、この様な構造、特に１層目メタル３
と２層目メタル４とを接合する為のスルーホール
１０を形成する方法としては、従来、下記に示す
２つの方法が採られており、それぞれ問題点を有
している。すなわち、第１の方法は、第３図にそ
の完成品の断面側面図を示す如く、まず１層目メ
タル３を形成した後ガラス系絶縁膜７を塗布し、
ガラス系絶縁膜７にフオトエツチング法で孔８を
形成した後、ポリイミド樹脂５を塗布し、次いで
ポリイミド樹脂５にフオトエツチング法で孔９を
形成して上述の孔８とともにスルーホール１０を
形成し、２層目メタル４を形成する方法である。
しかし、この様な方法によつては、下層のガラス
系絶縁膜７と上層のポリイミド樹脂５を全く別個
にフオトエツチング法で穿孔する為、第３図の如
く必然的にミスアラインメントが生じ、従つてス
ルーホール１０の径を小さくすることができな
い。これに対し、第２の方法は、１層目メタル３
を形成後ガラス系絶縁膜７およびポリイミド樹脂
５を塗布した後、フオトエツチング法により上層
のポリイミド樹脂５を蝕刻するエツチングで孔９
を形成し、位置をずらさずに、ポリイミド樹脂５
をマスクとしてガラス系絶縁膜７を蝕刻するエツ
チングを施して孔８を形成してスルーホール１０
とし、最後に２層目メタル４を形成する。この第
２の方法によれば、孔８と孔９との間にミスアラ
インメントが生じず、従つて、スルーホール１０
の径を小さくすることができ、高密度の半導体装
置を製作することができるが、第４図にこの第２
の方法によつて形成した半導体装置の断面側面図
を示す如く、１層目メタル３と２層目メタル４が
良好に接続されにくい。すなわち、ガラス系絶縁
膜７をエツチングする際、ポリイミド樹脂５をマ
スクする為、どうしてもポリイミド樹脂５に第４
図の如きオーバーハング部５aが形成され、この
状態で２層目メタルを形成するので、１層目メタ
ル３と２層目メタル４がオーバーハング部５aに
よつて分断され、いわゆる段切れ状態となつてし
まう。この段切れは半導体装置の歩留を著しく低
下させる原因となつている。 However, such a structure, especially the first layer metal 3
Conventionally, the following two methods have been adopted as a method for forming the through hole 10 for joining the second layer metal 4 and the second layer metal 4, and each method has its own problems. That is, in the first method, as shown in a cross-sectional side view of the finished product, first, the first layer metal 3 is formed, and then a glass-based insulating film 7 is applied.
After forming holes 8 in the glass-based insulating film 7 by photo-etching, polyimide resin 5 is applied, and then holes 9 are formed in the polyimide resin 5 by photo-etching to form through-holes 10 together with the holes 8 described above. This is a method of forming the second layer metal 4.
However, in this method, since the lower glass insulating film 7 and the upper polyimide resin 5 are perforated completely separately by photo-etching, misalignment inevitably occurs as shown in FIG. Therefore, the diameter of the through hole 10 cannot be reduced. On the other hand, the second method uses the first layer metal 3
After forming the glass-based insulating film 7 and the polyimide resin 5, the holes 9 are formed by etching the upper layer of the polyimide resin 5 using a photo-etching method.
without shifting the position of the polyimide resin 5.
Using the mask as a mask, etching is performed on the glass insulating film 7 to form a hole 8 and a through hole 10.
Finally, the second layer metal 4 is formed. According to this second method, no misalignment occurs between the holes 8 and 9, and therefore the through hole 10
It is possible to reduce the diameter of the
As shown in the cross-sectional side view of a semiconductor device formed by the method described above, it is difficult to connect the first layer metal 3 and the second layer metal 4 well. That is, when etching the glass-based insulating film 7, in order to mask the polyimide resin 5, it is necessary to add a fourth layer to the polyimide resin 5.
An overhang portion 5 a as shown in the figure is formed, and since the second layer metal is formed in this state, the first layer metal 3 and the second layer metal 4 are separated by the overhang portion 5 a , so-called step separation. It becomes a state. This disconnection is a cause of a significant decrease in the yield of semiconductor devices.
本発明は上記に鑑みなされたもので、スルーホ
ールの径が小さく、かつ、２層目メタルの段切れ
を生じない半導体装置の製造方法を提供すること
を目的とする。 The present invention has been made in view of the above, and it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the diameter of a through hole is small and no breakage occurs in the second layer metal.
本発明の特徴とするところは、多層配線構造を
有する半導体装置の層間絶縁膜にスルーホールを
形成する方法において、少なくとも上層が高分子
樹脂膜、下層が無機絶縁膜からなる層間絶縁膜を
形成し、この層間絶縁膜の上方に形成したフオト
レジストをマスクとして上層の高分子樹脂膜をエ
ツチングにより孔を穿ち、上記フオトレジストお
よび上層の高分子樹脂膜をマスクとして下層の無
機絶縁膜をエツチングした後、上層の高分子樹脂
膜を再度上記フオトレジストをマスクとしてエツ
チングし、高分子樹脂膜の孔の側面部を所定量除
去することにある。 The present invention is characterized in that a method for forming through holes in an interlayer insulating film of a semiconductor device having a multilayer wiring structure includes forming an interlayer insulating film consisting of at least an upper layer of a polymer resin film and a lower layer of an inorganic insulating film. Using the photoresist formed above the interlayer insulating film as a mask, a hole is formed in the upper polymer resin film by etching, and the lower inorganic insulating film is etched using the photoresist and the upper polymer resin film as a mask. First, the upper polymer resin film is etched again using the photoresist as a mask, and a predetermined amount of the side surface of the hole in the polymer resin film is removed.
以下、図面に基づいて本発明実施例を説明す
る。 Embodiments of the present invention will be described below based on the drawings.
第５図ａ〜ｆは、本発明実施例を経時的に説明
する為の断面図である。 FIGS. 5a to 5f are cross-sectional views for explaining the embodiments of the present invention over time.
第５図ａは一層目メタル３が完成した段階を示
す。次に、CVD法によつてガラス系絶縁膜７
（例えばSiO2膜、SiN膜、PSG膜、その他）を1μ
ｍの膜厚にデポジシヨンする。次にポリイミド樹
脂５等の高分子樹脂を同じく1μｍの膜厚で形成
する。この状態を第５図ｂに示す。なお、膜の形
成法はプラズマ法、スパツタ法、その他によつて
も行なうことができ、膜厚も上記以任意に選択す
ることができる。次に、ポリイミド樹脂５の穿孔
用フオトレジスト膜１１を4μｍの厚さで形成し、
そのフオトレジスト膜１１をマスクとしてポリイ
ミド樹脂をO2プラズマでエツチングして孔９を
穿つ。このO2プラズマではガラス系絶縁膜７は
エツチングされず、又、ポリイミド樹脂５とフオ
トレジスト１１のエツチング速度はほぼ等しく、
従つてフオトレジスト１１も同時にエツチングさ
れて、ポリイミド樹脂５に穿たれた孔９は約45゜
の傾斜が付く。この状態を第５図ｃに示す。な
お、この様なエツチングはO2プラズマの他に、
リアクテイブスパツタエツチングあるいはウエツ
トエツチングでも同様である。次に、ポリイミド
樹脂５とその上方に形成されたフオトレジスト１
１をマスクとして、下層のSiO2等ガラス系絶縁
膜７をフツ酸系のエツチヤートでエツチングして
孔８を形成する。このとき、ポリイミド樹脂５に
は前述した如くオーバーハング部５aが形成され
る。この状態を第５図ｄに示す。次いで、フオト
レジスト１１をマスクとして、再度ポリイミド樹
脂５をO2プラズマで約1μｍエツチングする。そ
うすれば、孔９は側壁部からエツチングされて径
が大きな孔９′となり、ポリイミド樹脂５のオー
バーハング部５aが除去される。この状態を第５
図ｅに示す。次に、フオトレジスト１１を除去し
た後、２層目メタル４を約1μｍ形成してその２
層目メタル４をフオトエツチングすれば、第５図
ｆに示す如く、多層配線構造が完成する。 FIG. 5a shows the stage when the first layer of metal 3 has been completed. Next, a glass-based insulating film 7 is formed using the CVD method.
(e.g. SiO 2 film, SiN film, PSG film, etc.) at 1μ
Deposit to a film thickness of m. Next, a polymer resin such as polyimide resin 5 is formed with a film thickness of 1 μm. This state is shown in FIG. 5b. Note that the film can be formed by a plasma method, a sputtering method, or other methods, and the film thickness can also be arbitrarily selected from those mentioned above. Next, a perforation photoresist film 11 of polyimide resin 5 is formed with a thickness of 4 μm,
Using the photoresist film 11 as a mask, the polyimide resin is etched with O2 plasma to form holes 9. The glass-based insulating film 7 is not etched by this O 2 plasma, and the etching speeds of the polyimide resin 5 and the photoresist 11 are almost equal.
Therefore, the photoresist 11 is also etched at the same time, and the holes 9 made in the polyimide resin 5 are inclined at about 45 degrees. This state is shown in FIG. 5c. In addition to O 2 plasma, this kind of etching can be done using
The same applies to reactive sputter etching or wet etching. Next, polyimide resin 5 and photoresist 1 formed above it
1 as a mask, the lower glass-based insulating film 7 such as SiO 2 is etched with a hydrofluoric acid-based etchant to form holes 8. At this time, the overhang portion 5 a is formed in the polyimide resin 5 as described above. This state is shown in FIG. 5d. Next, using the photoresist 11 as a mask, the polyimide resin 5 is etched again by about 1 μm using O 2 plasma. Then, the hole 9 is etched from the side wall to become a hole 9' with a large diameter, and the overhang portion 5a of the polyimide resin 5 is removed. This state is the fifth
Shown in Figure e. Next, after removing the photoresist 11, a second layer metal 4 with a thickness of about 1 μm is formed.
By photoetching the metal layer 4, a multilayer wiring structure is completed as shown in FIG. 5f.
なお、１層目および２層目メタルは、一般には
アルムニウムが用いられるが、多結晶Si、Mo等
の金属又はそれらの化合物であつてもよいことは
言うまでもない。 Although aluminum is generally used as the first and second layer metals, it goes without saying that metals such as polycrystalline Si and Mo or compounds thereof may also be used.
以上説明したように、本発明によれば、ポリイ
ミド樹脂等の高分子樹脂のステツプカバリツジの
良好な性質およびクラツクが起りにくい等の長所
と、ガラス系絶縁膜等の無機絶縁膜の耐湿性およ
び不純物が少いという長所とを兼ねそなえた信頼
性の高い半導体装置を、メタル配線の段切れ等の
不良品を生ずることなく高い歩留のもとに製造す
ることができる。 As explained above, according to the present invention, the advantages of polymer resins such as polyimide resins such as good step coverage and less cracking, and the moisture resistance and resistance of inorganic insulating films such as glass-based insulating films A highly reliable semiconductor device having the advantage of having a small amount of impurities can be manufactured at a high yield without producing defective products such as broken metal wiring.
なお、本発明による多層配線構造は、実施例の
如く２層でなく、３層またはそれ以上のものであ
つても同様なる手法によつて形成し得ることは勿
論である。 It goes without saying that the multilayer wiring structure according to the present invention can be formed by the same method even if it has three or more layers instead of two layers as in the embodiment.
第１図はポリイミド樹脂を層間絶縁膜とした多
層配線構造の半導体装置の断面図、第２図はポリ
イミド樹脂およびガラス系絶縁膜を重ねて層間絶
縁膜を形成した多層配線構造の半導体装置の断面
図、第３図および第４図は従来法によつて第２図
の構造を形成した場合のスルーホール部形状を示
す断面図、第５図ａ，ｂ，ｃ，ｄ，ｅ，ｆはそれ
ぞれ本発明実施例を経時的に説明する為の断面図
である。
１……シリコン基板、２……MoSトランジス
タ、３……１層目メタル、４……２層目メタル、
５……ポリイミド樹脂、５a……オーバーハング
部、７……ガラス系絶縁膜、１０……スルーホー
ル部、１１……フオトレジスト。
Figure 1 is a cross-sectional view of a semiconductor device with a multilayer wiring structure using polyimide resin as an interlayer insulating film, and Figure 2 is a cross-sectional view of a semiconductor device with a multilayer wiring structure in which polyimide resin and glass-based insulating films are stacked to form an interlayer insulation film. Figures 3 and 4 are cross-sectional views showing the shape of the through hole when the structure shown in Figure 2 is formed by the conventional method, and Figures a, b, c, d, e, and f are respectively FIG. 3 is a cross-sectional view for explaining an embodiment of the present invention over time. 1...Silicon substrate, 2...MoS transistor, 3...1st layer metal, 4...2nd layer metal,
5...Polyimide resin, 5a ...Overhang part, 7...Glass-based insulating film, 10...Through hole part, 11...Photoresist.
Claims (1)
であつて層間絶縁膜にスルーホールを形成する方
法において、少なくとも上層が高分子樹脂膜、下
層が無機絶縁膜からなる層間絶縁膜を形成し、上
記層間絶縁膜の上方に形成したフオトレジストを
マスクとして上記上層の高分子樹脂膜をエツチン
グにより孔を穿ち、上記フオトレジストおよび上
記上層の高分子樹脂膜をマスクとして上記下層の
無機絶縁膜をエツチングした後、上記上層の高分
子樹脂膜を再度上記フオトレジストをマスクとし
てエツチングし、上記孔の側面部を所定量除去す
ることを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device having a multilayer wiring structure, in which a through hole is formed in an interlayer insulating film, in which an interlayer insulating film is formed in which at least an upper layer is a polymer resin film and a lower layer is an inorganic insulating film, and the interlayer insulating film is After etching holes in the upper polymer resin film using the photoresist formed above the insulating film as a mask, and etching the lower inorganic insulating film using the photoresist and the upper polymer resin film as masks. . A method of manufacturing a semiconductor device, comprising etching the upper polymer resin film again using the photoresist as a mask to remove a predetermined amount of the side surface of the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14136782A JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14136782A JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5931028A JPS5931028A (en) | 1984-02-18 |
| JPH0138370B2 true JPH0138370B2 (en) | 1989-08-14 |
Family
ID=15290331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14136782A Granted JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931028A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
-
1982
- 1982-08-13 JP JP14136782A patent/JPS5931028A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5931028A (en) | 1984-02-18 |
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