JPS5931028A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5931028A JPS5931028A JP14136782A JP14136782A JPS5931028A JP S5931028 A JPS5931028 A JP S5931028A JP 14136782 A JP14136782 A JP 14136782A JP 14136782 A JP14136782 A JP 14136782A JP S5931028 A JPS5931028 A JP S5931028A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- hole
- mask
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010410 layer Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 25
- 239000002184 metal Substances 0.000 abstract description 25
- 239000011347 resin Substances 0.000 abstract description 10
- 229920005989 resin Polymers 0.000 abstract description 10
- 239000002952 polymeric resin Substances 0.000 abstract description 6
- 229920003002 synthetic resin Polymers 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000002349 favourable effect Effects 0.000 abstract 1
- 229920001721 polyimide Polymers 0.000 description 29
- 239000009719 polyimide resin Substances 0.000 description 29
- 239000011521 glass Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- ZFXYFBGIUFBOJW-UHFFFAOYSA-N theophylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC=N2 ZFXYFBGIUFBOJW-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、更に詳しくは、
多層配線構造を有する半導体装置のＷＩＡ間絶間膜縁膜
成方法番こ関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically,
The present invention relates to a method for forming an insulating film between WIAs in a semiconductor device having a multilayer wiring structure.
一般に、半導体装置が高密度化されるのに伴って、電極
配線の多層化、パターン幅の微少化が要求される。その
為、例えばＭＯＳ−ＩＣに於いて、第１図：こ横断面図
で示すように、シリコン基板１上に設けられたＭＯＳ）
ランジスタ２の電極に接続される１層目メタル３と、そ
の上層部の２層目メタル４との間にポリイミド樹脂６を
介在させ層間絶縁膜を形成し、多層配線構造にすること
によって高密度化を計ることが考えられる。なお、ここ
で６はＳｉＯ□である。このポリイミド樹脂等の高分子
樹脂を、多層配線の層間絶縁膜として使用することは従
来から知られており、ポリイミド樹脂等の樹脂は、無機
絶縁膜、例えば５ｉ０２膜、ＰＳＧ膜、ＳｉＮ膜等のガ
ラス系絶縁膜に比べ、ステップカバリッジが良い、クラ
ックが起りにくい等の長所がある反面、ガラス系の絶縁
膜に比して吸湿性が大きく、樹脂材料であるが故に不純
物を含有しており、更に分極率が大きい為２層目メタル
の電位関係によっては、シリコン基板の表面反転を引！
起こしＭＯＳ）ランジスタのスレッシュホールド電圧を
変化させる等、ＩＣとしての信頼性が悪くなるという欠
点があって、特にＭＯＳ−ＩＣに使用することはできな
いとされている。Generally, as semiconductor devices become more densely packed, there is a demand for multi-layered electrode wiring and smaller pattern widths. Therefore, for example, in a MOS-IC, as shown in FIG.
A polyimide resin 6 is interposed between the first layer metal 3 connected to the electrode of the transistor 2 and the second layer metal 4 above it to form an interlayer insulating film, resulting in a multilayer wiring structure with high density. It is conceivable to measure the Note that 6 is SiO□ here. It has been known for a long time that polymer resins such as polyimide resins are used as interlayer insulating films for multilayer interconnections. Compared to glass-based insulating films, it has advantages such as better step coverage and less cracking, but on the other hand, it is more hygroscopic than glass-based insulating films, and because it is a resin material, it contains impurities. Furthermore, since the polarizability is large, depending on the potential relationship of the second layer metal, the surface of the silicon substrate may be inverted!
It has the disadvantage that reliability as an IC deteriorates, such as by changing the threshold voltage of a transistor (MOS-IC), and it is said that it cannot be used particularly in a MOS-IC.
また、最近、パッケージが低価格の樹脂封止型となって
、なおその形状が小型化するにつれて、この本質的に水
を透過するパッケージでも、耐湿性のある多層配線構造
であることが強く要望されるに至っている。In addition, recently, as packages have become low-cost resin-sealed types and their shapes have become smaller, there is a strong demand for moisture-resistant multilayer wiring structures even for packages that are essentially water permeable. It has come to be.
そこで、眉間絶縁膜を、第２図にその横断面図を示す如
く、ガラス系絶縁膜７とポリイミド樹脂５を重ねて２層
構造にすれば、上述の欠点を克服しまたニーズに応える
ことができる。すなわち、■ガラス系絶縁膜を下層に使
用することによって、ポリイミド樹脂の吸湿による水分
および樹脂に含まれている不純物がシリコン基板に到達
することを防ぐことができる。■ポリイミド樹脂の分極
に（３）
よる影響を、下層のガラス系絶縁膜によって半減するこ
とができる。■ガラス系絶縁膜のステップカバリッジの
悪さおよびクラック等は上層のポリイミド樹脂によって
平坦化し、又、クラックを埋めることにより、層間絶縁
膜の完全性を飛躍的に向上することができる。又、一般
に絶縁膜の欠陥率の減少には、多層構造が有効であるこ
とが知られており、従って、この第２図に示す如く構成
すれば、ＬＳＩの歩留の向上に対して有効である。Therefore, if the glabella insulating film is made into a two-layer structure by overlapping the glass-based insulating film 7 and the polyimide resin 5, as shown in the cross-sectional view of FIG. 2, the above-mentioned drawbacks can be overcome and the needs can be met. can. That is, (1) By using a glass-based insulating film as the lower layer, it is possible to prevent moisture due to moisture absorption of the polyimide resin and impurities contained in the resin from reaching the silicon substrate. (3) The influence of polarization of polyimide resin (3) can be halved by the underlying glass-based insulating film. (2) Poor step coverage and cracks in the glass-based insulating film can be flattened by the upper layer of polyimide resin, and the integrity of the interlayer insulating film can be dramatically improved by filling the cracks. Furthermore, it is generally known that a multilayer structure is effective in reducing the defect rate of insulating films, and therefore, the structure shown in FIG. 2 is effective in improving the yield of LSI. be.
しかるに、この様な構造、特に１層目メタル３と２層目
メタル４とを接合する為のスルーホール１０を形成する
方法としては、従来、下記に示す２つの方法が採られて
おり、それぞれ問題点を有している。すなわち、第１の
方法は、第８図にその完成品の断面側面図を示す如く、
まず１層目メタル３を形成した後ガラス系絶縁膜７を塗
布し、ガラス系絶縁膜７にフォトエツチング法で孔８を
形成した後、ポリイミド樹脂６を塗布し、次いでポリイ
ミド樹脂５にフォトエツチング法で孔Ｂを形成して上述
の孔８とともにスルーホール１０を形成（４）。However, as a method for forming a through hole 10 for joining such a structure, particularly the first layer metal 3 and the second layer metal 4, the following two methods have been conventionally adopted, and each method is as follows. There are problems. That is, the first method is as shown in the cross-sectional side view of the finished product in FIG.
First, after forming the first layer metal 3, a glass-based insulating film 7 is applied, holes 8 are formed in the glass-based insulating film 7 by photo-etching, a polyimide resin 6 is applied, and then a polyimide resin 5 is photo-etched. A through hole 10 is formed together with the above-mentioned hole 8 by forming a hole B using a method (4).
し、２層目メタル４を形成する方法である。しかし、こ
の様な方法によっては、下層のガラス系絶縁膜７と上層
のポリイミド樹脂５を全く別個にフォトエツチング法で
穿孔する為、第８図の如く必然的にミスアラインメント
が生じ、従ってスルーホール１０の径を小さくすること
ができない。これに対し、第２の方法は、１ｒｍ目メタ
ル３を形成後ガラス系絶ｗ膜７およびポリイミド樹脂６
を塗布した後、フォトエツチング法により上層のポリイ
ミド樹脂５を軸側するエツチングで孔９を形成し、位置
をずらさずに、ポリイミド樹脂５をマスクとしてガラス
系絶縁膜７を蝕刻するエツチングを施して孔８を形成し
てスルーホール１０とし、最後に２頌目メタル４を形成
する。この第２の方法によれは、孔８と孔８との同番こ
ミスアラインメントが生じず、従って、スルーホール１
０の径を小さくすることができ、高密度の半導体装置を
製作することができるが、第４図にこの第２の方法によ
って形成した半導体装１者の断匍側面図を示す如り、１
ｗ４目メタル３と２Ｊｉｉ！１日メタル４が良好に接続
されにくい。すなわち、ガラス系絶縁膜７をエツチング
する際、ポリイミド樹脂５をマスクとする為、どうして
もポリイミド樹脂６、に第４図の如きオーバー−ハング
部ｉが形成され、この状態で２層目メタルを形成するの
で、１層目メタル３と２層目メタル４がオーバーハング
部−によって分断され、いわゆる段切れ状態となってし
まう。この段切れは半導体装置の歩留を著しく低下させ
る原因となっている。In this method, the second layer metal 4 is formed. However, with this method, the lower glass insulating film 7 and the upper polyimide resin 5 are photo-etched completely separately, which inevitably causes misalignment as shown in Figure 8. 10 cannot be made smaller. On the other hand, in the second method, after forming the first rm metal 3, a glass-based insulating film 7 and a polyimide resin 6 are formed.
After coating, a hole 9 is formed by etching the upper layer polyimide resin 5 on the axis side using a photo-etching method, and etching is performed to etch the glass-based insulating film 7 using the polyimide resin 5 as a mask without shifting the position. A hole 8 is formed to form a through hole 10, and finally a second square metal 4 is formed. With this second method, no misalignment occurs between the holes 8 and 8, and therefore the through holes 1
The diameter of the semiconductor device 1 can be made small, and a high-density semiconductor device can be manufactured.
w 4th metal 3 and 2Jii! 1st Metal 4 is difficult to connect well. That is, since the polyimide resin 5 is used as a mask when etching the glass-based insulating film 7, an overhang part i as shown in FIG. 4 is inevitably formed in the polyimide resin 6, and in this state, the second layer metal is formed. Therefore, the first layer metal 3 and the second layer metal 4 are separated by the overhang portion, resulting in a so-called step-broken state. This disconnection causes a significant decrease in the yield of semiconductor devices.
本発明は上記に鑑みなされたもので、スルーホールの径
が小さく、かつ、２層目メタルの段切れを生じない半導
体装置の製造方法を提供することを目的とする。The present invention has been made in view of the above, and it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the diameter of a through hole is small and no breakage occurs in the second layer metal.
本発明の特徴とするところは、ガラス系絶縁膜等の無機
絶縁膜と、ポリイミド樹脂等の高分子樹脂膜とを重ねて
形成した後、上層の樹脂の上にフォトレジスト膜を形成
してフォトエツチング法により上層の樹脂に穿孔し、そ
のフォトレジストを残した状態で下層のガラス系絶縁膜
をそのフォトレジストおよび樹脂をマスクとしてフォト
エッチフグ法によって穿孔し、次に再度上述のフ第１・
レジストをマスクとして樹脂に先に穿った孔をエツチン
グすることにより、樹脂に形成されたオーバーハング部
を除去することにある。The present invention is characterized by forming an inorganic insulating film such as a glass-based insulating film and a polymeric resin film such as polyimide resin in a layered manner, and then forming a photoresist film on the upper layer of the resin. A hole is made in the upper layer resin by an etching method, and with the photoresist left, a hole is made in the lower glass insulating film by a photoetching method using the photoresist and resin as a mask, and then the above-mentioned step 1.
The purpose of this method is to remove overhangs formed in the resin by etching holes previously drilled in the resin using a resist as a mask.
以下、図面に基づいて本発明実施例を説明する。Embodiments of the present invention will be described below based on the drawings.
第５図（ａ）〜（ｆ）は、本発明実施例を経時的に説明
する為の断面図である。FIGS. 5(a) to 5(f) are sectional views for explaining the embodiments of the present invention over time.
第６図（ａ）は一層目メタル３が完成した段階を示す。FIG. 6(a) shows the stage when the first layer metal 3 is completed.
次に、ＣＶＤ法によってガラス系絶縁膜７（例えばＳｉ
Ｏ□膜、ＳＩＮ膜、ＰＳＧ膜、その他）を１μηＩの膜
厚にデポジションする。次にポリイミド樹脂５等の高分
子樹脂を同じく１μｍの膜厚で形成する。この状態を第
５図（ｂ）に示す。なお、膜の形成法はプラズマ法、ス
パッタ法、その他によっても行なうことができ、膜厚も
上記以外任意に選択すことができる。次に、ポリイミド
樹脂５の穿孔用フォトレジスト膜１１を４ｐｍの厚さで
形成し、そのフォトレジスト膜１１をマスクとしてポリ
イミド樹脂５を０２プラズマでエツチングして孔９を穿
つ。Next, a glass-based insulating film 7 (for example, Si
O□ film, SIN film, PSG film, etc.) is deposited to a film thickness of 1 μηI. Next, a polymer resin such as polyimide resin 5 is similarly formed with a film thickness of 1 μm. This state is shown in FIG. 5(b). Note that the film can be formed by a plasma method, a sputtering method, or other methods, and the film thickness can also be arbitrarily selected other than those mentioned above. Next, a photoresist film 11 for forming holes in the polyimide resin 5 is formed to a thickness of 4 pm, and using the photoresist film 11 as a mask, the polyimide resin 5 is etched with 02 plasma to form the holes 9.
この０２プラズマではガラス系絶縁膜７はエツチングさ
れず、又、ポリイミド樹脂５とフォトレジスト１１のエ
ツチング速度はほぼ等しく、従ってフォトレジスト１１
も同時にエツチングされて、ポリイミド樹脂５に穿たれ
た孔９は約４５°の傾斜が付く。In this 02 plasma, the glass-based insulating film 7 is not etched, and the etching speeds of the polyimide resin 5 and the photoresist 11 are almost equal, so the photoresist 11
The holes 9 made in the polyimide resin 5 are also etched at the same time, so that the holes 9 formed in the polyimide resin 5 have an inclination of about 45°.
この状態を第５図（Ｃ）に示す。なお、この様なエツチ
ングは０２プラズマの他に、リアクテイブスバッタエツ
チン、グあるいはウェットエツチングでも同 ′様で
ある。次に、ポリイミド樹脂５とその上方に形成された
フォトレジスト１１をマスクとして、下層の８１０μガ
ラス系絶縁膜７をフッ酸系のニッチヤードでエツチング
して孔８を形成する。このとき、ポリイミド樹脂６には
前述した如くオーバーハング部６ａが形成される。この
状態を第５図（ｄ）に示す。次いで、フォトレジスト１
１をマスクとして、再度ポリイミド樹脂６を０／ラズマ
で約１μｍエツチングする。そうすれば、孔９は側壁部
からエツチングされて径が大きな孔９′となり、ポリイ
ミド樹脂５のオーバーハング部６ａが除去される。この
状態を第５図（ｅ）に示す。次に、フォトレジスト１１
を除去した後、２層目メタル４を約１μｍ形成してその
２層目メタル４をフォトエツチングすれば、第５図（ｆ
）に示す如く、多層配線構造が完成する。This state is shown in FIG. 5(C). In addition to 02 plasma, this type of etching can also be done by reactive scattering etching, wet etching or etching. Next, using the polyimide resin 5 and the photoresist 11 formed above it as a mask, the lower 810 μm glass insulating film 7 is etched with a hydrofluoric acid niche yard to form holes 8. At this time, the overhang portion 6a is formed in the polyimide resin 6 as described above. This state is shown in FIG. 5(d). Next, photoresist 1
Using 1 as a mask, the polyimide resin 6 is etched again by about 1 μm using 0/lasma. Then, the hole 9 is etched from the side wall to become a hole 9' with a large diameter, and the overhang portion 6a of the polyimide resin 5 is removed. This state is shown in FIG. 5(e). Next, photoresist 11
After removing the second layer metal 4, a second layer metal 4 with a thickness of about 1 μm is formed and the second layer metal 4 is photoetched, as shown in FIG.
), the multilayer wiring structure is completed.
なお、１層目および２層目メタルは、一般にはアルミニ
ウムが用いられるが、多結晶Ｓｉ、Ｍｏ等の金属又はそ
れらの化合物であってもよいことはＢうまでもない。Note that aluminum is generally used as the first and second layer metals, but it goes without saying that metals such as polycrystalline Si and Mo or compounds thereof may also be used.
以上説明したように、本発明によれば、ポリイミド樹脂
等の高分子樹脂のステップカバリッジの良好な性質およ
びクラックが起りにくい等の長所と、ガラス系絶縁膜等
の無機絶縁膜の耐湿性および不純物が少いという長所と
を兼ねそなえた信頼性の高い半導体装置を、メタル配線
の段切れ等の不良品を生ずることなく高い歩留のもとに
製造することができる。As explained above, according to the present invention, the advantages of polymer resin such as polyimide resin such as good step coverage and less cracking, and the moisture resistance and resistance of inorganic insulating film such as glass insulating film A highly reliable semiconductor device having the advantage of having a small amount of impurities can be manufactured at a high yield without producing defective products such as broken metal wiring.
なお、本発明による多層配線構造は、実施例の如く２層
でなく、８層またはそれ以上のものであっても同様なる
手法によって形成し得ることは勿論である。It goes without saying that the multilayer wiring structure according to the present invention can be formed by the same method even if it has eight or more layers instead of two layers as in the embodiment.
第１図はポリイミド樹脂を眉間絶縁膜とした多層配線構
造の半導体装置の断面図１、第２図はポリイミド樹脂お
よびガラス系絶縁膜を重ねて層間絶縁膜を形成した多層
配線構造の半導体装置の断面図、第８図および第４図は
従来法によって第２図の構造を形成した場合のスルーホ
ール部形状を示す断面図、第５図（ａχ（ｂλ夙（ｄλ
（ｅχ（ｆ）はそれぞれ本発明実施例を経時的に説明す
る為の断面図である。
１・・・シリコン基板、 ２・・・ＭＯＳ）ランジス
タ、３・・・１層目メタル、 ４・・・２層目メタル
、６・・・ポリイミド樹脂％ ５ｉ・・オーパーツ１ン
グ部、７・・・ガラス系絶縁膜、１０・・・スルーホー
ル部、１１・・・フォトレジスト、
特許出願人 シャープ株式会社
代 理 人 弁理士 西１）新Figure 1 is a cross-sectional view of a semiconductor device with a multilayer wiring structure using polyimide resin as an insulating film between the eyebrows, and Figure 2 is a cross-sectional view of a semiconductor device with a multilayer wiring structure in which polyimide resin and glass-based insulation films are stacked to form an interlayer insulation film. 8 and 4 are cross-sectional views showing the shape of the through-hole portion when the structure shown in FIG. 2 is formed by the conventional method, and FIG.
(eχ(f) is a sectional view for explaining the embodiments of the present invention over time. 1... Silicon substrate, 2... MOS) transistor, 3... First layer metal, 4. ...Second layer metal, 6...Polyimide resin% 5i...Oparts 1 ring part, 7...Glass-based insulating film, 10...Through hole part, 11...Photoresist, Patent applicant Sharp Corporation Representative Patent Attorney Nishi 1) Arata
Claims (2)
って、配線間に２層以上の性質の異る絶縁膜を重ねて層
間絶縁膜を形成し、その層間絶縁膜にスルーホールを形
成するにあたり、上記異種の絶縁膜を同一のフォトレジ
ストマスクを用いてエツチングすることを特徴とする半
導体装置の製造方法。(1) A method for manufacturing a semiconductor device having a multilayer wiring structure, in which two or more layers of insulating films with different properties are stacked between wirings to form an interlayer insulating film, and through holes are formed in the interlayer insulating film. A method for manufacturing a semiconductor device, characterized in that the different types of insulating films are etched using the same photoresist mask.
て上記層間絶縁膜の上層側の絶縁膜をエツチングにより
孔を穿ち、その下層の絶縁膜を上記フオトレジスｌよび
上記上層の絶縁膜をマスクとしてエツチングした後、上
記上層の絶縁膜を再度上記フォトレジストをマスクとし
てエツチングして上記孔の側面部を所定量除去すること
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法(2) Form a photoresist above the interlayer insulating film, make a hole in the upper insulating film of the interlayer insulating film by etching, and use the lower insulating film to mask the photoresist l and the upper insulating film. The method for manufacturing a semiconductor device according to claim 1, wherein the upper insulating film is etched again using the photoresist as a mask to remove a predetermined amount of the side surface of the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14136782A JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14136782A JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5931028A true JPS5931028A (en) | 1984-02-18 |
| JPH0138370B2 JPH0138370B2 (en) | 1989-08-14 |
Family
ID=15290331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14136782A Granted JPS5931028A (en) | 1982-08-13 | 1982-08-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931028A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
-
1982
- 1982-08-13 JP JP14136782A patent/JPS5931028A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710936A (en) * | 1980-06-25 | 1982-01-20 | Sanyo Electric Co Ltd | Forming method for contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0138370B2 (en) | 1989-08-14 |
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