JPH0132436Y2 - - Google Patents

Description

[Detailed explanation of the idea]

<Industrial Application Field> This invention uses a voltage controlled oscillator as a local oscillator, and uses this voltage controlled oscillator as a component to create a phase lock loop (hereinafter referred to as PLL).
This invention relates to a so-called FM negative feedback type synthesizer receiver in which a part of the receiver output is used to frequency modulate a local oscillator. <Prior Art> Generally, a synthesizer receiver has a configuration as shown in FIG. In the figure, 1 is a high frequency amplifier, 2 is a mixer,
3 is an intermediate frequency amplifier, and 4 is a demodulator. A voltage controlled oscillator is used as the local oscillator 5, and a signal obtained by dividing this local oscillation output signal by a frequency divider 6 and a reference signal from a reference signal oscillator 7 are divided by a programmable frequency divider 8. (frequency division ratio N) is phase-compared by a phase comparator 9, and the phase comparison output is passed through a low-pass filter 10 to remove high-frequency components. Configure the PLL by entering: The reception frequency is determined by the contents preset in the programmable frequency divider 8 (tuning code corresponding to the reception frequency), and normally the tuning code generated by the tuning code generator 11 is set as above. The channel selection operation is performed by presetting the programmable frequency divider 8 and changing the frequency division ratio N. The tuning code from the tuning code generator 11 is converted into a decimal frequency display segment signal by the code conversion/drive circuit 12, and then
A plurality of segment groups 14a, 1 for displaying each digit of the received frequency of the frequency display 13 and other information.
4b..., respectively. On the other hand, the output of the demodulator 4 is fed back to the local oscillator 5 through the amplifier 15 to form an FM negative feedback loop, and part of the demodulated output is fed back to the local oscillator 5.
frequency modulation is applied to make the local oscillation frequency follow the frequency modulation of the received wave. In this FM negative feedback method, the frequency deviation in the intermediate frequency band is compressed more than that of the received wave, so the intermediate frequency amplifier 3 can be used without increasing distortion.
It has the feature that it is possible to narrow the band and improve the threshold level without sacrificing the S/N ratio. <Problems to be solved by the invention> Although the conventional techniques described above basically have excellent features, there are further problems to be solved. That is, FM band 76.0-90.0M in Japan
In a synthesizer receiver that targets Hz, the phase of the demodulated output of the demodulator 4 is delayed by about 90 degrees around 60 KHz, as shown in Figure 6, so the frequency characteristics of the demodulated output are at maximum reception. frequency
It is lifted in the high range even at the max and minimum reception frequency min. Conventionally, as shown in FIG. 5, a phase correction circuit 16 consisting of a series circuit of a capacitor C and a resistor R is connected to the output of the demodulator 4 to correct the phase in the high frequency range. However, in such a phase correction means, the phase correction at the maximum receiving frequency maz and the minimum receiving frequency min is performed by one phase correction circuit 16. If the constants of the phase correction circuit 16 are selected as shown in FIG. Become. Therefore, the separation near the maximum reception frequency and the minimum reception frequency decreases, and the frequency characteristics become as shown in FIG. 7. The present invention aims to improve these problems to be solved. <Means for solving the problem> The present invention uses programmable frequency division of a high frequency amplifier, mixer, intermediate frequency amplifier, demodulator, local oscillator, and a signal obtained by dividing the local oscillation output signal of the local oscillator and a reference signal. Divide by frequency (dividing ratio N)
It is equipped with a phase lock loop which compares the phase of the received signal with a phase comparator, and inputs the output of this phase comparator to the local oscillator via a low-pass filter. The configuration is such that the reception frequency is determined by presetting the channel selection code in the programmable frequency divider, and the output of the demodulator is fed back to the local oscillator via the amplifier to apply frequency modulation to the FM negative feedback loop. In a synthesizer receiver formed with This configuration is such that the correction circuit is selectively switched according to the divided reception frequency bands. <Operation> According to the present invention, it is possible to select the optimum phase correction circuit for the reception frequency according to each divided reception frequency band, and it is possible to perform the optimum phase correction in each divided reception frequency band. can. <Example> Hereinafter, an example of the present invention will be described with reference to the drawings. In the drawings, parts equivalent to those of the conventional example shown in FIG. 5 are given the same reference numerals, and their explanation will be omitted. <Example 1> In Fig. 1, 17 is a capacitor C ₁ and a resistor.
The first phase correction circuit consists of a series circuit of R ₁ ,
This is for phase correction of the reception frequency band of 80.0~90.0MHz. A second phase correction circuit 18 is composed of a series circuit of a capacitor C ₂ and a resistor R ₂ , and is used for phase correction in the receiving frequency band of 76.0 to 79.9 MHz. The first and second phase correction circuits 17 and 18 are grounded via first and second switching elements, such as field effect transistors 19 and 20, respectively. First and second control signals having opposite polarities are input to the gate terminals of the first and second field effect transistors 19 and 20. These first and second control signals having polarities opposite to each other are generated by a known drive circuit 21 that combines a PNP transistor 22 and an NPN transistor 23. On the other hand, the tuning code output from the tuning code generation circuit 11 is supplied to the reception frequency band detector 24, and its detection output is inputted to the drive circuit 21. The reception frequency band detector 24 detects two reception frequency bands (76.0MHz to 90.0MHz) in Japan's FM band 76.0 to 90.0MHz.
79.9MHz, 80.0-90.0MHz), the reception frequency band is detected by the following detection method. The reception frequency is 76.0~ as the tuning code is as follows
Assuming that each digit of 90.0MHz is given as a BCD code expressed in binary numbers, [10MHz digit] ₂ [MHz digit] ₂ [0.1MHz digit] ₂ (The subscript represents the binary number) The receiving frequency is 76.0 ~79.9MHz, the code for the 10MHz digit of the tuning code is [0111] ₂
If the receiving frequency is in the range of 80.0 to 90 MHz, the code for the 10 MHz digit of the channel selection code is [1000] ₂ or [1001] ₂ . Therefore, the 4th digit of the 10MHz digit code of the tuning code

By detecting [0] and [1], the receiving frequency band can be detected.

If [0], 76.0~
79.9MHz band, [1] is 80.0~90.0MHz band. The relationship between the receiving frequency band and its detection output is selected such that when the receiving frequency band is 76.0 to 79.9 MHz, it is a low level [L], and when it is 80.0 to 90.0 MHz, it is a high level [H]. The operation of the above configuration will be explained below. First, if the receiving frequency band is 76.0~79.9MHz,
Since the detection output of the reception frequency band detector 24 becomes low level [L], both transistors 22 and 23 of the drive circuit 21 are conductive, and the first control signal of low level [L] is output from the collector of the transistor 23. , a second control signal of high level [H] is output from the collector of the transistor 22, and these first and second control signals are applied to the first field effect transistor 19 and the second field effect transistor 20, respectively. Each is input to the gate terminal. Therefore, the first field effect transistor 19
maintains a cut-off state and the second field effect transistor 20 conducts, so the output of the demodulator 4 is grounded via the second phase correction circuit 18. The second phase correction circuit 18 has a 76.0
This is for phase correction of the reception frequency band of ~79.9MHz, and the frequency characteristics of the output of the demodulator 4 are shown in Figure 3.For example, the capacitor C ₂ and the resistor are used to obtain the maximum separation at 78MHz. When the value of R ₂ is determined, the separation characteristics with respect to the reception frequency are as shown in FIG. Next, if the receiving frequency is 80.0~90.0MHz,
The receiving frequency band detector 24 operates in the opposite manner to the above.
The detection output of is at a high level [H], the first and second control signals are at a high level and a low level, respectively, and the first and second field effect transistors 19 and 20 are respectively turned on and off, The output of the demodulator 4 is grounded via a first phase correction circuit 17. The first phase correction circuit 17 has an 80.0
This is for phase correction of the reception frequency band of ~90.0MHz, and the frequency characteristics of the output of the demodulator 4 are shown in Figure 3.For example, the capacitor C ₁ and the resistor are used to obtain the maximum separation at 85MHz. When the value of C ₂ is determined, the separation characteristics with respect to the reception frequency will be as shown in FIG. <Embodiment 2> In this embodiment, the reception frequency band is detected using a frequency display drive signal (segment signal) that drives the segment groups 14a, 14b, . . . of the frequency display 13. The receiving frequency band detector 24 in the first embodiment is unnecessary. This will be explained in FIG. The channel selection code from the channel selection code generator 11 is converted by the code conversion/drive circuit 12 into decimal frequency indicating segment signals Sa, Sb, Sc...Sg, which then represent the 10MHz digit of the reception frequency. It is supplied to each segment a, b, c...g of the segment group 14a. Here, focusing on the segment group 14a, segment g is 76.0 to 79.9MHz.
It does not light up in the reception frequency band of 80.0~
It can be seen that the light is displayed in the 90.0MHz reception frequency band. That is, the receiving frequency band can be detected by detecting the segment signal Sg that drives the segment g, and this segment signal Sg has a low level [L] of 80.0 to 90.0 MHz when the receiving frequency band is 76.0 to 79.9 MHz. At this time, it becomes high level [H]. This segment signal Sg is then input to the drive circuit 21 as a reception frequency band detection signal. <Effects of the invention> Since the present invention has the above-described configuration, it is possible to perform optimal phase correction in each divided receiving frequency band. This makes it possible to improve separation characteristics and achieve excellent separation characteristics as a whole.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of the synthesizer receiver of the present invention, Fig. 2 is a diagram showing the configuration of another embodiment of the same, and Figs. 3 and 4 are the same, and frequency characteristics of demodulated output and separation. 5 shows the configuration of a conventional synthesizer receiver, and FIGS. 6 and 7 show frequency characteristics of demodulated output and separation. 1 is a high frequency amplifier, 2 is a mixer, 3 is an intermediate frequency amplifier, 4 is a demodulator, 5 is a local oscillator, 8 is a programmable frequency divider, 9 is a phase comparator, 10 is a low-pass filter, 17 and 18 are first , a second phase correction circuit.

Claims (1)

[Scope of utility model registration request] A high frequency amplifier 1, a mixer 2, an intermediate frequency amplifier 3, a demodulator 4, a local oscillator 5, and a signal obtained by frequency-dividing the local oscillation output signal of the local oscillator 5 and a reference signal are divided by a programmable frequency divider 8. A phase lock loop is provided, which compares the phase of the frequency signal with a phase comparator 9, and inputs the phase comparison output to the local oscillator 5 via a low-pass filter 10, and generates a tuning code. The receiving frequency is determined by presetting the channel selection code output from the oscillator 11 into the programmable frequency divider 8, and the demodulated output of the demodulator 4 is fed back to the local oscillator 5 for frequency modulation. In a synthesizer receiver that forms an FM negative feedback loop, the received frequency band is divided into a plurality of bands, and a phase correction circuit for correcting the high-frequency phase of the demodulated output in the divided receiving frequency band is provided. 17 and 18, respectively, and the phase correction circuits 17 and 18 are selectively switched according to the divided receiving frequency bands.