JPS611940U - synthesizer receiver - Google Patents
synthesizer receiverInfo
- Publication number
- JPS611940U JPS611940U JP8562484U JP8562484U JPS611940U JP S611940 U JPS611940 U JP S611940U JP 8562484 U JP8562484 U JP 8562484U JP 8562484 U JP8562484 U JP 8562484U JP S611940 U JPS611940 U JP S611940U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- phase
- local oscillator
- divided
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Superheterodyne Receivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のシンセサイザー受信機の構成を示す図
、第２図は同、他の実施例の構成を示す図、第３図およ
び第４図は同、復調出力およびセパレーションの周波数
特性図、第５図は従来のシンセサイザー受信機の構成を
示す図、第６図および第７図は同、復調出力およびセパ
レーションの周波数特性図である。
１は高周波増幅器、２は混合器、３は中間周波増幅器、
４は復調器、５は局部発振器、８はプログラマブル分周
器、９は位相比較器、１０はローパスフィルタ、１７．
１８は第１、第２の位相補正回路である。Fig. 1 is a diagram showing the configuration of the synthesizer receiver of the present invention, Fig. 2 is a diagram showing the configuration of another embodiment of the same, and Figs. 3 and 4 are frequency characteristics diagrams of demodulated output and separation. , FIG. 5 is a diagram showing the configuration of a conventional synthesizer receiver, and FIGS. 6 and 7 are frequency characteristic diagrams of demodulated output and separation. 1 is a high frequency amplifier, 2 is a mixer, 3 is an intermediate frequency amplifier,
4 is a demodulator, 5 is a local oscillator, 8 is a programmable frequency divider, 9 is a phase comparator, 10 is a low-pass filter, 17.
Reference numeral 18 indicates first and second phase correction circuits.
Claims (1)
４、局部発振器５、および、当該局部発振器５の局部発
振出力信号を分周した信号と基準信号をプログラマブル
分周器８によって分周した信号とを位相比較器９によっ
て位相比較し、当該位相比較出力をローパスフィルタ１
０を介して上記局部発振器５に入力するようにしたフエ
ーズ・ロック・ループを具備し、選局コード発生器１１
から出力される選局コードを上記プログラマブル分周器
８にプリセットして受信周波数を定めるようにした構成
であって、上記復調器４の復調出力を上記局部発振器５
にフィードバックして周波数変調をかけるようにしたＦ
Ｍ負帰還ループを形成したシンセサイザー受信機におい
てＪ受信周波数パッドを複数個の帯域に分割し、当該分
割した受信周波数帯における復調出力の高域の位相補正
するための位相補正回路１７．１８をそれぞれ設け、肖
該位相補正回路１７．１８を上記分割した受信周波数帯
に応じて択一的に切換えるようにしたことを特徴とする
シンセサイザー受信機。A high frequency amplifier 1, a mixer 2, an intermediate frequency amplifier 3, a demodulator 4, a local oscillator 5, and a signal obtained by frequency-dividing the local oscillation output signal of the local oscillator 5 and a reference signal are frequency-divided by a programmable frequency divider 8. The phase of the signal is compared by a phase comparator 9, and the phase comparison output is sent to a low-pass filter 1.
0 to the local oscillator 5, and the tuning code generator 11
The receiving frequency is determined by presetting the channel selection code output from the programmable frequency divider 8 to the programmable frequency divider 8, and the demodulated output of the demodulator 4 is transmitted to the local oscillator 5.
Feedback is applied to frequency modulation.
In a synthesizer receiver forming an M negative feedback loop, the J reception frequency pad is divided into a plurality of bands, and phase correction circuits 17 and 18 are respectively provided for correcting the phase of the high frequency range of the demodulated output in the divided reception frequency bands. A synthesizer receiver characterized in that the phase correction circuits 17 and 18 are selectively switched according to the divided reception frequency bands.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8562484U JPS611940U (en) | 1984-06-08 | 1984-06-08 | synthesizer receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8562484U JPS611940U (en) | 1984-06-08 | 1984-06-08 | synthesizer receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS611940U true JPS611940U (en) | 1986-01-08 |
| JPH0132436Y2 JPH0132436Y2 (en) | 1989-10-04 |
Family
ID=30636186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8562484U Granted JPS611940U (en) | 1984-06-08 | 1984-06-08 | synthesizer receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS611940U (en) |
-
1984
- 1984-06-08 JP JP8562484U patent/JPS611940U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0132436Y2 (en) | 1989-10-04 |
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