JPH01319994A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH01319994A JPH01319994A JP15391688A JP15391688A JPH01319994A JP H01319994 A JPH01319994 A JP H01319994A JP 15391688 A JP15391688 A JP 15391688A JP 15391688 A JP15391688 A JP 15391688A JP H01319994 A JPH01319994 A JP H01319994A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- hole
- electroplating
- printed wiring
- circuit patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009713 electroplating Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 239000011889 copper foil Substances 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000839 emulsion Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は各種電子機器に使われるプリント配線板の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing printed wiring boards used in various electronic devices.
従来の技術
従来、この種の導電ペーストを用いたスルーホールプリ
ント配線板の製造方法は、第２図に示す・ ような方
法であった。第２図＆のように銅は＜１１は基板１２０
両面の回路パターンをエツチングなどで形成する。次に
第２図すで、回路パターンがめつきリードでつながって
いる銅はく１１上に、電気めっき１３を形成する。この
後、第２図Ｃのように導電ペースト１４で表裏の回路パ
ターンをスルーホール導通させ、第２図ｄの絶縁レジス
ト１６で、導電ペースト１４を覆うことによって、各種
電気めっき付のスルーホールプリント配線板を製造して
いた。Prior Art Conventionally, the method of manufacturing through-hole printed wiring boards using this type of conductive paste was as shown in FIG. 2. As shown in Figure 2, copper is <11 on the substrate 120.
Form circuit patterns on both sides by etching. Next, as shown in FIG. 2, electroplating 13 is formed on the copper foil 11 to which the circuit pattern is connected by plating leads. After that, as shown in FIG. 2C, the front and back circuit patterns are made to conduct through-holes with the conductive paste 14, and the conductive paste 14 is covered with the insulating resist 16 as shown in FIG. Manufactured wiring boards.
発明が解決しようとする課題
このような従来の製造方法では、各面ごとに、電気めっ
き１３をする回路パターンにめっき用リードを配線する
必要があり、近年の増々高密度化する回路では、めっき
リードが設けられなくなってきており、このめっきリー
ドを設けることが、プリント配線板の小型化や高密度化
を阻害し問題となっていた。Problems to be Solved by the Invention In such conventional manufacturing methods, it is necessary to wire plating leads to the circuit pattern to be electroplated 13 on each side. Leads are no longer provided, and the provision of these plated leads has become a problem as it hinders the miniaturization and higher density of printed wiring boards.
本発明はこのような問題点を解決するもので、プリント
配線板の高密度化を一層可能にすることを目的とするも
のである。The present invention is intended to solve these problems, and aims to further increase the density of printed wiring boards.
課題を解決するための手段
この課題を解決するために本発明は、導電ペーストのス
ルーホールで表裏の回路パターンヲ導通させた後、この
導電ペーストを絶縁レジストで覆い、その後に、回路パ
ターン上に電気めっきを施す方法としたものである。Means for Solving the Problem In order to solve this problem, the present invention provides electrical continuity between the front and back circuit patterns using through holes in a conductive paste, and then covering the conductive paste with an insulating resist. This is a method of applying plating.
作用
この製造方法によれば、導電ペーストによるスルーホー
ルを通して電気めっきをすることができるため、めっき
のリードは半減し、プリント配線板の小型化・高密度化
を一層可能にすることができる。Function: According to this manufacturing method, electroplating can be performed through the through-holes made of conductive paste, so the number of leads for plating can be halved, making it possible to further downsize and increase the density of printed wiring boards.
実施例
以下、本発明の実施例を第１図の図面を用いて説明する
。第１図ａは両面銅張板をエツチングし回路パターンを
形成したものであり、１は銅はくであり、２は基材であ
る。この基材２の孔２ａにに第１図すで、導電ペースト
４でスルーホールを形成し、回路パターンの表裏を導通
させる。さらに第１図Ｃで、導電ペースト４上に絶縁レ
ジスト５を印刷形成し、導電ペースト４の表面が外側に
でないように覆った。その後、第１図ｄのように電気め
っき３を銅はく１上に形成した。一般に電気めっきされ
る部分は銅はく１のめっきリードを通して、各面ごとに
導通していることが必要であるが、本発明では銅はく１
でつながっている部分はもちろん、導電ペースト４のス
ルーホールを通じてつながる表裏鋼はく部上圧も電気め
っき３をすることができた。なお、この時の電気めっき
３としては金・銀・ニッケル・パラジウム・半田めっき
など、各種組成の電気めっきでも可能である。Embodiment Hereinafter, an embodiment of the present invention will be explained using the drawing of FIG. Figure 1a shows a double-sided copper clad plate etched to form a circuit pattern, 1 being a copper foil and 2 being a base material. As shown in FIG. 1, a through hole is formed in the hole 2a of the base material 2 using a conductive paste 4, so that the front and back sides of the circuit pattern are electrically connected. Furthermore, as shown in FIG. 1C, an insulating resist 5 was printed on the conductive paste 4 to cover the surface of the conductive paste 4 so as not to expose it to the outside. Thereafter, electroplating 3 was formed on the copper foil 1 as shown in FIG. 1d. Generally, the parts to be electroplated must be electrically connected to each side through the plating leads of the copper foil 1, but in the present invention, the copper foil 1
It was possible to perform electroplating 3 not only on the parts connected by the conductive paste 4 but also on the upper pressure of the front and back steel foil parts connected through the through holes of the conductive paste 4. Note that the electroplating 3 at this time may be electroplating of various compositions such as gold, silver, nickel, palladium, and solder plating.
また、導電ペースト４としては比抵抗値が（１×１ｏ
〜ｌＸ１０ ）Ω・眞の銀ペースト・銅ペーストなど
が、電気めっき３の厚みのばらつきを小さくでき、良好
であった。絶縁レジスト５としては耐めっき性の良好な
エポキシ樹脂、エポキシアクリレート樹脂などのレジス
トが良好であった。In addition, the conductive paste 4 has a specific resistance value of (1×1o
~lX10) Ω/true silver paste, copper paste, etc. were able to reduce variations in the thickness of electroplating 3 and were good. As the insulation resist 5, resists made of epoxy resin, epoxy acrylate resin, etc., which have good plating resistance, were good.
絶縁レジスト５の厚みはできる限り厚く形成することが
必要であるが、−度に厚く印刷すると導電ペースト４の
スルーホールのへこみ部分に多量の絶縁レジスト６が入
りこみ、その後の焼付で、スルーホール部の絶縁レジス
ト５がふくれ、導電ペースト４の露出や、レジスト盛り
上りなどの問題がある。また、−印刷の場合はスクリー
ンの乳剤厚５０μと厚くし、版メツシュを１５０μと低
メツシュにした厚塗りの仕様であっても、ピンホールの
発生を完全に防止できないために、後工程の電電めっき
３が導電ペースト４上のピンホールに付着し、外観を損
うとともに、密着が悪いために工程中で落下し、ショー
トを発生したり、電気めっき３とのすり傷をプリント板
に発生させるなど様々な問題を発生させた。従って、少
なくとも絶縁レジスト６は２回刷の重ね刷り以上で、１
回の印刷が厚塗りでないことが好ましい。版のメツシュ
はテトロン２００〜２６０メツシユで、乳剤厚１０〜３
０μ程度が好ましく、１回印刷後、硬化し、再び印刷し
た。この条件によれば、前記、絶縁レジスト５のふくれ
、電気めつき３の付着も問題がなくなった。It is necessary to form the insulating resist 5 as thick as possible, but if it is printed too thick, a large amount of the insulating resist 6 will get into the recessed part of the through hole of the conductive paste 4, and the through hole will be damaged by subsequent baking. There are problems such as the insulating resist 5 swells, the conductive paste 4 is exposed, and the resist bulges. In addition, in the case of -printing, even if the screen emulsion thickness is as thick as 50μ and the plate mesh is as low as 150μ, which is a thick coating specification, it is not possible to completely prevent the occurrence of pinholes. The plating 3 adheres to the pinholes on the conductive paste 4, damaging the appearance, and falling during the process due to poor adhesion, causing short circuits and scratches on the printed board due to the electroplating 3. This caused various problems. Therefore, at least the insulation resist 6 is overprinted twice or more.
It is preferable that the printing is not thick. The mesh of the plate is 200 to 260 mesh, and the emulsion thickness is 10 to 3.
It is preferably about 0μ, and after printing once, it is cured and printed again. Under these conditions, there were no problems with the blistering of the insulating resist 5 and the adhesion of the electroplating 3.
発明の効果
以上のように本発明によれば、導電ペーストによるスル
ーホールを経由する回路パターン上にも電気めっきをす
ることができ、各面ごとに、単独に必ずめっきするリー
ドを設ける必要がなくなった。これにより、めっきリー
ドの配線量は著しく減少し、設計の容易さはもちろんの
こと、回路の高密度化、小型化が可能となる効果が得ら
れた。Effects of the Invention As described above, according to the present invention, electroplating can be performed even on circuit patterns via through holes made of conductive paste, and there is no need to provide a lead that must be plated separately on each side. Ta. As a result, the amount of wiring for plated leads has been significantly reduced, which has the effect of not only simplifying the design, but also making it possible to increase the density and miniaturize the circuit.
第１図ａ −％−ｄは本発明の一実施例によるプリント
配線板の製造方法を示す工程図、第２図ａ〜ｄは従来の
プリント配線板の製造方法を示す工程図である。
１・・・・・・銅はく、２・・・・・・基材、２ト・・
・・・孔、３・・・・・・電気めっき、４・・・・・・
導電ペースト、５・・・・・・絶縁レジスト。1A-%-D are process diagrams showing a method for manufacturing a printed wiring board according to an embodiment of the present invention, and FIGS. 2A to 2D are process diagrams showing a conventional method for manufacturing a printed wiring board. 1... Copper foil, 2... Base material, 2...
...hole, 3...electroplating, 4...
Conductive paste, 5...Insulating resist.
Claims (2)
ホールで導通させた後、この導電ペーストを絶縁レジス
トで覆い、その後に、回路パターン上に電気めっきを施
すプリント配線板の製造方法。(1) A method for manufacturing a printed wiring board, in which circuit patterns on the front and back sides are made conductive through through holes using conductive paste, the conductive paste is covered with an insulating resist, and then electroplating is performed on the circuit patterns.
２回以上の印刷の重ね刷りで形成する請求項（１）記載
のプリント配線板の製造方法。(2) The method for manufacturing a printed wiring board according to claim (1), wherein the insulating resist covering the conductive paste is formed by overprinting at least two times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63153916A JP2752988B2 (en) | 1988-06-22 | 1988-06-22 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63153916A JP2752988B2 (en) | 1988-06-22 | 1988-06-22 | Manufacturing method of printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01319994A true JPH01319994A (en) | 1989-12-26 |
| JP2752988B2 JP2752988B2 (en) | 1998-05-18 |
Family
ID=15572901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63153916A Expired - Fee Related JP2752988B2 (en) | 1988-06-22 | 1988-06-22 | Manufacturing method of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2752988B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100385657B1 (en) * | 1994-11-22 | 2003-08-02 | 소니 가부시끼 가이샤 | Printed wiring board and its manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5791263U (en) * | 1980-11-26 | 1982-06-04 | ||
| JPS57112096A (en) * | 1980-12-29 | 1982-07-12 | Matsushita Electric Ind Co Ltd | Stencil screen unit for connecting through hole print |
| JPS5879795A (en) * | 1981-11-06 | 1983-05-13 | 富士通株式会社 | Method of producing printed circuit board |
| JPS6296885U (en) * | 1985-12-09 | 1987-06-20 | ||
| JPS62200797A (en) * | 1986-02-27 | 1987-09-04 | シャープ株式会社 | Manufacture of printed wiring board |
-
1988
- 1988-06-22 JP JP63153916A patent/JP2752988B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5791263U (en) * | 1980-11-26 | 1982-06-04 | ||
| JPS57112096A (en) * | 1980-12-29 | 1982-07-12 | Matsushita Electric Ind Co Ltd | Stencil screen unit for connecting through hole print |
| JPS5879795A (en) * | 1981-11-06 | 1983-05-13 | 富士通株式会社 | Method of producing printed circuit board |
| JPS6296885U (en) * | 1985-12-09 | 1987-06-20 | ||
| JPS62200797A (en) * | 1986-02-27 | 1987-09-04 | シャープ株式会社 | Manufacture of printed wiring board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100385657B1 (en) * | 1994-11-22 | 2003-08-02 | 소니 가부시끼 가이샤 | Printed wiring board and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2752988B2 (en) | 1998-05-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |