JPH01312869A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a soft error due to alpha rays, etc., and a back channel phenomenon from being produced by supplying bias voltage to each element region of a single SOI substrate. CONSTITUTION:In an SOI substrate 100 composed of a support layer 11, an insulating layer 12, and a element layer 13, an electrode 14 is formed in the support layer 11 or the insulating layer 12, and voltages E1, E2, E3 are applied to the electrode 14. In such a manner, the voltage is applied to each electrode independently so that a desired positive or negative electric field can be produced at a proper portion from a proper material in a region between the element layer and the insulating layer. Hereby, a back channel phenomenon and a soft error due to alpha rays, etc., can be prevented from being produced.

Description

[Detailed Description of the Invention] [Summary] Regarding electrodes that supply bias voltage to semiconductor devices, particularly semiconductor elements formed on an SOI substrate, it is important to avoid supplying the same bias voltage to the entire surface of the jfsOI substrate (the S
The purpose of this method is to supply a desired voltage to each semiconductor element region of the OI substrate and prevent soft errors caused by bank channel phenomena and alpha rays. or at least one electrode is formed in the insulating layer, and a voltage is applied to the electrode, and the device is connected to the 11-electrode type semiconductor substrate and the first external wiring. A semiconductor device having an SO structure, comprising a supporting layer comprising a metal plate to be connected and a conductive layer, a base insulating film, and an element layer comprising a first and second element region, wherein the conductive layer is a first element region. The structure includes being provided on a semiconductor substrate of one conductivity type in an element region, connected to a second external wiring, and supplied with a bias voltage.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to an electrode for supplying a bias voltage to a semiconductor element formed on an SOI substrate and a method for forming the same.

[Conventional technology]

FIG. 7.8 is an explanatory diagram of a conventional example.

FIG. 7 is a structural diagram of a semiconductor device according to a conventional semiconductor manufacturing method, and shows a cross-sectional view of a So2 substrate.

In the figure, l is a support layer made of a Si layer containing p-type or n-type impurities, 2 is an insulating layer that becomes the underlying 8i film such as SiO□ or Si3N, and 3 is an element such as a MOS transistor or a bipolar transistor. It is a layer.

Further, 4 is a metal plate to which the SOf substrate is fixed.

Note that 10 is S consisting of a support layer 1, an insulating layer 2, and an element layer 3.
O ■ It is a substrate. Further, E is a voltage applied between the element layer 1 and the support layer 3. The voltage application method is to apply a voltage to the metal +14 formed on the back surface of the support layer 3, thereby determining the overall potential of the support layer 3. For example, by supplying a positive potential to the support layer 3, the insulating layer 2 side of the element layer 3 is charged with a negative charge.

FIG. 8 is a diagram illustrating problems related to a conventional semiconductor device, and FIG. 8(a) shows a MOS
) shows a cross-sectional view when α rays are incident on the transistor.

In the figure, nchMO3) alpha rays 5 are applied to transistors T and l.
When incident, the depletion layer region diffused from the drain 6 collects α rays (positive charges), which may cause transistor malfunction 1, for example, a soft error that inverts the contents of a memory cell.

To prevent this, it is necessary to supply a positive potential to the support layer l to negatively charge the surface of the insulation M2.

FIG. 2B is a diagram illustrating a method for preventing bank channels of MOS transistors provided on an SOI substrate.

In the figure, by making the element layer 3 thinner according to the requirements of the semiconductor device, nchMO5)U'/distorT is obtained.

At the bottom of the p-type Si layer 3a, a depletion layer of the n impurity diffusion region forming the source 7 and drain 6 may spread laterally along the base insulating film 2. As a result, the source and drain may become electrically short-circuited, and the transistor may not operate normally. This is called a back-channel phenomenon. To prevent this, the support layer
It is necessary to apply a negative voltage to the base insulating layer 20 to positively charge the surface area of the base insulating layer 20.

(Problem to be solved by the invention) According to the conventional example, as shown in FIG.
For each OI substrate 10, a voltage E is applied between the support it and the insulating layer 2.
is applied to supply the bias voltage.

For this reason, as shown in Fig. 8, there are cases in which a part for reducing soft errors and a part for preventing back channel phenomenon are mixed in one SOI substrate lO, and in cases where a part for reducing soft errors and a part for preventing back channel phenomenon are mixed,
When it is necessary to supply bias voltages on two sides in a device having a structure, it is not possible to supply bias voltages separately, so the selectivity is poor and it is difficult to improve the function and performance of the transistor. There is a problem that it becomes an obstacle.

The present invention was created in view of the problems of the conventional example, and it is possible to supply a desired voltage to each semiconductor element region of the SOI substrate without supplying the same bias voltage to the entire surface of the SOI substrate, and to provide a back channel. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent soft errors caused by phenomena such as alpha rays and alpha rays.

[Means to solve the problem]

The semiconductor device and its manufacturing method of the present invention, as its principle diagram is shown in FIG. 1 and one embodiment thereof is shown in FIGS. 2 to 6,
11111. supports that principle. Insulating layer 12 and element layer 1
3, at least one electrode 14 is formed in the support 11 or the insulating layer 12, and voltages E+, Et, and E3 are applied to the electrode 14, The first device is a semiconductor substrate 21a of one conductivity type.

A support layer 21 consisting of a metal plate 25 and a conductive layer 21b connected to the first external wiring L1, a base insulating film 22, and a first
．． A semiconductor device having an SOI structure 101, comprising an element layer 23 consisting of two element regions A, , A, wherein the conductive layer 21b is provided only on a semiconductor substrate 21a of one conductivity type in the first element region A1. and the second external wiring L
! and bias voltage V.

characterized by being supplied with The second device is a semiconductor substrate 31a of one conductivity type.

The first external wiring is connected to the metal plate 35 and the first external wiring.
a support layer 31 consisting of two conductive layers 31b and 31c, a base insulating film 32, and two or more element regions A+.

A! , and an element layer 33, the first conductive layer 31b is provided on the base insulating film 32 of the first element region A1, and the second external wiring layer 2 is provided with the first conductive layer 31b. The second conductive layer 31c is provided on the base insulating film 32 of the second element region A2, and is connected to the third external wiring, and is supplied with the first bias voltage (1). The third device is supplied with a bias voltage V of 2, and the conductive layers 21b, 31b, 31C are
．． It is characterized in that it is connected to one electrode of the semiconductor element T□, Tag in the element region A, , A, and is supplied with a bias voltage generated in an internal circuit. First and second element regions AI and A are formed on the semiconductor substrate 21a.
x, and the semiconductor substrate 21 of the first element region A;
forming a supporting layer 21 by providing an impurity diffusion region 21b of the opposite conductivity type in a, and laminating an element layer 23 made of a semiconductor N25a of one conductivity type and a base insulating film 22 on the support Ji21. Te, SO
Steps of forming an I substrate 101 and the SOI substrate 101
a step of thinning the element layer 23 of the element 1123;
tx, patterning the element N23, exposing the opposite conductivity type impurity diffusion region 21b, and external wiring L! or a step of selectively penetrating the element layer 23 and the insulating layer 22 and connecting the external wiring 2 and the impurity diffusion region 21b with a conductive material 27. The second forming method is to form a first and second polycrystalline semiconductor film 31d containing impurity ions of an opposite conductivity type on an insulated semiconductor substrate 31a of one conductivity type. A pattern is formed to define the 1.2nd element forming regions A+ and At, and then the cylinder 1. 2 the polycrystalline semiconductor #3 l b.

31c and forming the support layer 31, and laminating the base insulating film 32 and the element layer 33 on the support layer 31.
A step of forming the OI substrate 102 and the SOI substrate 10
2 is a transistor element T□.

T++1 is formed, and then an element layer 33 and a base insulating film 3 are formed.
1.2 conductive electrodes 37a, 37b selectively penetrate through 2 and connect to the 1.2 polycrystalline semiconductor films 31b, 31c and the 1.2 external wiring lines, . The above object is achieved by insulating the portion penetrating the element layer 33.

[Operation] According to the principle of the semiconductor device and its manufacturing method of the present invention,
A plurality of electrodes are provided on the element layer or the insulating layer.

Therefore, by independently supplying a voltage to each electrode, it is possible to generate a desired positive and negative electric field (interfacial potential) at the appropriate location in the region between the element layer and the insulating layer.

This makes it possible to prevent the occurrence of back channel phenomena, soft errors due to alpha rays, etc.

Further, according to the first device, a conductive layer consisting of an impurity diffusion layer of an opposite conductivity type supplies a bias voltage to the element layer in the first element region, and a bias voltage is supplied to the element layer in the second element region. A semiconductor substrate of one conductivity type is provided.

Therefore, the potential supplied to the semiconductor substrate of one conductivity type via the metal plate connected to the first external wiring and the potential of the conductive layer connected to the second external wiring are individually controlled. I can do it.

As a result, in one SOI structure, by supplying the voltage between the element layer and the supporting layer to the right material and the right place, it is possible to prevent back channel phenomena and reduce soft errors in each element region. becomes.

Furthermore, according to the second device, the conductive layer is made of a polycrystalline semiconductor film containing impurity ions of opposite conductivity type, and the nuclide i* is provided in the insulating layer.

Therefore, the bias voltage can be divided and supplied to each element region of the element layer independently from the semiconductor substrate of one conductivity type in the support layer, allowing more fine voltage control than in the first device. It becomes possible to do so.

According to the third device, the conductive layer provided for each element region is connected to one electrode of the semiconductor element of the element layer.

Therefore, in contrast to the external fixed bias method in which bias voltage is supplied from external wiring as in the device 1.2, it is possible to use an internal self-bias method by supplying a voltage generated inside the circuit. This makes it possible to eliminate the need for a dedicated power supply and reduce the complexity of wiring.

Further, according to the first formation method, after forming a diffusion region of the opposite conductivity type only in the semiconductor substrate of one conductivity type of the support layer of the first element formation region, the element layers are laminated to form the So+ substrate. ing.

Therefore, the element regions AI', A! are formed by the diffusion regions of opposite conductivity type and the semiconductor substrate of one conductivity type. A pn junction can be formed in the semiconductor layer, and a bias voltage can be supplied to each element formation region by connecting external wiring to each semiconductor layer.

Furthermore, according to the second formation method, after patterning a conductive layer made of a polycrystalline semiconductor film containing impurity ions in each of the 1.2 element formation regions, the element layer 33 is laminated and SOI is formed.
forming the substrate.

Therefore, the conductive layer can be formed independently from the support layer and the element layer. This makes it possible to perform extremely fine voltage control for each conductive layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 6 are diagrams for explaining a semiconductor device and its manufacturing method according to an embodiment of the present invention, and FIGS. 2(a) and 2(b)
1 shows a structural diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2(a) is a diagram of the first electrode structure, and in the figure, 21 is a support layer consisting of a p-type Si substrate 21a, an n'' diffusion region 21b, and a metal plate 25. Note that the n9 diffusion region 2
1b is provided on the p-type SI substrate 21a below the region A1 in order to supply a bias voltage only to the element region A1. In addition, the exposed n' diffusion region 21b and the voltage ■,
External wiring to supply! are connected. In addition, L
, are external wirings that supply a voltage V to the metal plate 25 bonded to the p-type Si substrate 21a.

In addition, 23 is a nchMOS transistor T, 11 or T1.
This is an element layer in which semiconductor elements such as the following are formed. lOl is an S consisting of an element Ji23, a support layer 21, and a base insulating film 22.
It is an OI substrate. Note that 24 is a PSGli that insulates the transistor element.

FIG. 5B is a second electrode structure diagram of the semiconductor device according to the first embodiment.

In the figure, parts with the same reference numerals have the same functions, so their explanation will be omitted. Note that the difference from the first electrode structure is that the method of connecting the external wiring L2 and the n' diffusion region 21b is different.

That is, 27 is an AN electrode that passes through the element rfi 23 and the like and is connected to the n' diffusion region 21b. This eliminates the stepped portion and allows flattening. Note that 26 is the element layer 3
2, it is an insulating film for insulating it.

These constitute the semiconductor device according to the first embodiment.

In this way, n1 expansion rI41. An electrode consisting of the region 21b is provided, and a voltage V is supplied to the external wiring L8. Therefore, for example, by supplying a positive voltage ■1 to the external wiring L+ and a negative voltage v1 to the wiring Lx, negative charges are charged on the surface area of the base insulating film 22 in the element region A. It becomes possible to prevent soft errors caused by , alpha rays, etc.

Further, in the element region A, the surface region of the underlying insulating film 22 is positively charged, making it possible to prevent the occurrence of the back-channel phenomenon.

FIG. 3 is a structural diagram of a semiconductor device according to a second embodiment of the present invention.

Here, the difference from the first embodiment is that the electrode for supplying the bias voltage is made up of a plurality of poly-Si films 31b and 31C doped with, for example, n-type impurity ions, and the electrode is inside the insulating film. This is the point that it is provided.

In the figure, 31 is a p-type Si layer 31a, a metal plate 35, n
゛ Poly-Si film 3lb, 31c, CVD
5i (h film 31, d, etc.), 33 is a p-type Si layer 33a, nch MOs transistor T Il
++ ”rll,.

This is an element layer made of a PSG film 34.

Note that 102 is the support layer 31. This is a So 15 plate consisting of a base insulating film 32 and an element layer 33. Also, 2 and 3 are external wirings that supply a bias voltage V to the /1 electrode 37a of the element region A, and similarly.

is an external wiring that supplies a bias voltage (2) to the /1 electrode 37b. Further, the A2 electrodes 37a and 37b are connected to the element layer 33.
The n0 poly S+ film 31b penetrates through the base insulating film 22, etc.
, 31c. Note that 36 is /l electrode 37
L is an insulating film that insulates a and 37b, and L is a support layer 31
This is an external wiring that is connected to the metal plate 35 of and supplies a common potential (2).

These constitute the semiconductor device according to the second embodiment.

In this way, n1 polys S for each element region At, As
The i-films 31b and 31C are provided, and are insulated from the support layer and provided in the base insulating film 22 and the CV DSiO film.

For this reason, the support layer 31 is set to a common potential (7), and the bias voltage (2) is applied to the element region A, and the element region A,
It becomes possible to divide and supply the bias voltage Vh.

As a result, compared to the first embodiment, in the second embodiment,
More fine voltage control can be performed, making it possible to fully meet the requirements for semiconductor device performance.

FIG. 4 is a structural diagram of a semiconductor device according to a third embodiment of the present invention.

Here, components with the same reference numerals as those in the second embodiment have the same functions, so a description thereof will be omitted.

Note that the difference from Embodiment 1.2 is the bias voltage V,
. It is connected to one of the electrodes, such as the drain, and is supplied with a bias voltage.

Furthermore, the nchMOS transistors T, . . . , T+tt, etc. may be power supply regulators or control transistors.

In the figure, 39a and 39b have one side at n° of the support layer 31.
It is connected to the poly-Si films 31b and 31c, and the other is connected to the element layer 3.
3 nchMO3l-n° diffusion region 38a of transistor
, 38b. 36 is an insulator that insulates the Ae electrodes 39a and 39b that penetrate the support layer 33.

These components constitute the semiconductor device of the third embodiment.

In this way, the conductive layer consisting of the n° poly-Si films 31b and 31c provided for each element region A, A is connected to one electrode such as the drain of the nchMOS transistors T□ and T1 of the element layer 33. ing.

For this reason, external wiring like the first and second embodiments, L
In contrast to the external fixed bias method, which supplies bias voltages V, ,V, from It becomes possible to improve the complexity of wiring, etc.

FIG. 5 is a process diagram for forming a semiconductor device according to the first embodiment of the present invention.

In the figure, first, the resistivity of the supporting layer 21 is 3 [ΩC1].
For example, an element region A that requires prevention of soft errors such as α rays and an element region A2 that requires prevention of back channel effects are defined on the P-type Si substrate 21a of about 100 mL.

After that, n-type impurity ions such as As'' are added to the element region A1.
Ions and the like are implanted into the P-type Si substrate 21 by an ion implantation method to form an n° diffusion region 21b. Note that the n4 diffusion region 21b serves as an electrode for supplying a bias voltage. Further, the ion implantation conditions are such that the implantation energy is about 50 (key) and the dose is about IX l O"(CM-") (FIG. 2(a)).

Next, a P-type Si layer 23a with a resistivity of about 10 [Ωe11] and an element layer 2 which becomes the base insulating film 22 with a film thickness of about 1 [μm]
3 to form an SOI substrate 101.

Note that the SOI substrate 101 is formed by a recrystallization method, a SIMOX method, or the like in addition to the bonding method (FIG. 2(b)).

Next, the element layer 23 is polished by a predetermined boring method to form a gi film with a thickness of about 3 [μm] (the same [im(
c)).

Furthermore, a gate electrode G is selectively formed on the p-type Si layer 23a by a conventional method, and then a source S and a drain D consisting of n diffusion regions are formed on the p-type Si layer 23a, and an nC
hMO3) Form transistor Tll ((d) in the same figure)
.

Next, wiring is formed on the electrode that supplies the bias voltage.

The first wiring method in this case is to attach the metal plate 25 to the support layer 21.
and connect the nchMOS transistor Tll+T
, , 2 is patterned to expose the n' diffusion region 21b, and then the transistor T+tl is patterned.
, T++1 is insulated by the PSG film 24, and further external wiring is provided to supply the voltage 1 to the metal plate 25, and external wiring to selectively supply the voltage 1 to the exposed n' diffusion region 21b, (see figure (e)
1)).

Further, the second wiring method uses nchM without patterning the element layer 23 as in the first wiring method.

The S transistor TLIIST, 11 is insulated by the PSG film 24, and then the PSG film 24 and the element layer 23 are selectively removed to open an electrode window, exposing the n° diffusion region 21b, and then the sidewall of the opening is Insulated by an insulating film 26 etc.
This is carried out by forming an Affi electrode 27 at the internuclear space and forming an external wiring for supplying the voltage 5. Note that the insulating film 25 may be a 5in2 film or a pn junction.

Further, the voltage (1) is supplied to the metal plate 25 similarly to the first wiring method ((e=) in the figure).

In this way, the P type S1 of the support layer 21 in the element region A1 is
After forming the n' diffusion region 21b only on the substrate 21a, the element layer 23 is laminated to form the SOT substrate 101.

Therefore, a pn junction can be formed in the element regions A, , A, by the n' diffusion region 21b and the p-type Si substrate 21a, and by connecting external wiring and Lt to each conductive layer, Bias voltage V, ,V, for each element region
It becomes possible to supply

This makes it possible to prevent soft errors such as alpha rays and bank channel phenomena from occurring.

FIG. 6 is a process diagram for forming a semiconductor device according to a second embodiment of the present invention.

In the figure, first, a p-type Si substrate 31a and an n9 poly 5l193lb doped with n-type impurities such as P゛ ions and AS° ions are placed in each element formation region A, .
3tc is patterned. Thereafter, the n゛poly Si films 31b and 31 become electrodes for supplying a bias voltage.
A supporting IN 31 is formed of a C V D SiO2 film 31 d insulating the C V D SiO2 film 31 d (FIG. 3(a)).

Next, as in the first embodiment, the element layer 33 is adhered by a bonding method or the like, and its surface is polished, and the SOI substrate 10 is
2 (FIG. 2(b)).

Next, similar to the first embodiment, nchMOs are formed in the element layer 33.
Transistor T1. After that, the transistor element is insulated with a PSG poly-Si film 34.

Next, the PSG film 34 and the element N33 are selectively removed to open the electrode, and the side wall of the opening is insulated with an insulating film 36 or the like.

Thereafter, an Al electrode 37a is formed to supply a voltage ``n'' to the poly-Si film 1b, and is further connected to external wiring 2. Further, an AN wiring 37b for supplying a voltage V to the n9 polySt film 31c is formed, and is similarly connected to the wiring.

Next, a conductive material such as a metal plate 35 is bonded to the support layer, and external wiring for supplying voltage (1) 8 is formed on the metal plate 35.

In this way, n' poly Sl films 31b, 31 . After patterning the conductive layer consisting of c, an element layer 33 is laminated to form the SO2 substrate 102.

Therefore, the conductive layer can be formed independently from the support layer 31 and the element layer 33. This makes it possible to perform extremely fine voltage control for each conductive layer.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to supply a bias voltage to each element region of one SO1 substrate, so it is possible to apply an appropriate electric field (interface state) to the semiconductor element in the region. becomes.

Therefore, soft errors and back channel phenomena due to α rays etc. can be prevented. This makes it possible to manufacture high-performance semiconductor devices.

[Brief explanation of the drawing]

1 is a principle diagram of a semiconductor device and its manufacturing method according to the present invention; FIGS. 2(a) and (b) are structural diagrams of a semiconductor device according to a first embodiment of the present invention; FIG. is a structural diagram of a semiconductor device according to a second embodiment of the present invention, FIG. 4 is a structural diagram of a semiconductor device according to a third embodiment of the present invention, FIGS. 5(a) to (e1), (e1) is a formation process diagram of a semiconductor device according to the first embodiment of the present invention, and FIG.
) to (C) are process diagrams for forming a semiconductor device according to a second embodiment of the present invention, FIG. 7 is a structural diagram of a semiconductor device according to a conventional semiconductor manufacturing method, and FIG. 8 is a conventional example FIG. 3 is a diagram illustrating problems related to the semiconductor device of FIG. (Explanation of symbols) 10.100.101.102...SOI substrate (SOT structure), 2]a, 31a...p-type Si substrate (semiconductor substrate of one conductivity type), 1.11.21.31 ... Supporting layer, 2.12, 22.32 ... Insulating layer (base insulating film), 3
．． 13.23.33...Element layer, 14...Electrode, 4.25.35...Metal plate, 5...α ray, D, 6.38a, :j8b-...Dray 7 (n 'diffusion region), 3.7...source, 3a, 23a, 33a.=P-type Si layer (semiconductor layer of one conductivity type), 24, 34...PSG film, 21b...n° diffusion region (conductive layer), 26, 36・
...Insulating film, 27, 37a, 37b, 39a, 39
b-...to! Electric I7i! (conductive material or first and second conductive electrodes), 31b, 31c...n Poly-Si film 1.2 polycrystalline semiconductor film containing impurity ions or 1.2 polycrystalline semiconductor film containing impurity ions; 2 conductive layer)
, 31d...CV D 5i (h film, E, V,, Vb...voltage, bias voltage (1st degree 2nd bias voltage), v7...common potential, L+, Lx, Lx... External wiring (1.2 and 3 external wiring), A+, At... 1.2 element region or 1.2 element formation slope, To, T□, TnC= n Ch MOS
Transistor (transistor element).

Claims (6)

[Claims] (1) Support layer (11), insulating layer (12) and element layer (1)
3) the support layer (11) of the SOI structure (100) consisting of
or at least one electrode (14) in the insulating layer (12)
A semiconductor device characterized in that a voltage (E_1, E_2, E_3) is applied to the electrode (14). (2) A semiconductor substrate (21a) of one conductivity type, a metal plate (25) connected to the first external wiring (L_1), and a conductive layer (
21b) and a base insulating film (22).
) and an element layer (23) consisting of first and second element regions (A_1, A_2), the semiconductor device having an SOI structure (101), wherein the conductive layer (21b) is the first element region. (A_1) is provided on the semiconductor substrate (21a) of one conductivity type, is connected to the second external wiring (L_2), and is connected to the bias voltage (V_b
). (3) A semiconductor substrate (31a) of one conductivity type, a metal plate (35) connected to the first external wiring (L_1), and the first and second
a support layer (31) consisting of conductive layers (31b, 31c), a base insulating film (32), and two or more element regions (A_1,
A_2), an SOI structure (1) comprising an element layer (33)
02), wherein the first conductive layer (31b) is connected to the first element region (A_1).
) is provided on the underlying insulating film (32), is connected to the second external wiring (L_2), and is connected to the first bias voltage (V_a
), and the second conductive layer (31c) is supplied with a second element region (A_2
) is provided on the underlying insulating film (32), is connected to the third external wiring (L_3), and is connected to the second bias voltage (V_b
). (4) The semiconductor device according to claim 2 or 3, wherein the first and second conductive layers (21b, 31b, 31c) are
, 2 semiconductor elements (T_
n_1, T_n_2) and is connected to one electrode of T_n_2), and is supplied with a bias voltage generated in an internal circuit. (5) First and second element regions (A_1, A_2) are defined in the semiconductor substrate (21a) of one conductivity type, and impurities of the opposite conductivity type are formed in the semiconductor substrate (21a) of the first element region (A_1). A step of forming a support layer (21) by providing a diffusion region (21b), and forming a semiconductor layer (23a) of one conductivity type on the support layer (21).
) and a base insulating film (22) to form an SOI substrate (101); and a step of thinning the element layer (23) of the SOI substrate (101). , a transistor element (T_n_1,
T_n_2) and patterning the element layer (23), then exposing the impurity diffusion region (21b) of the opposite conductivity type and forming the external wiring (L
_2) or the step of connecting the element layer (23) and the insulation layer (
22), selectively passing through the external wiring (L_2) and
A method of manufacturing a semiconductor device, comprising the step of connecting the impurity diffusion region (21b) with a conductive material (27), and insulating a portion penetrating the element layer (23). (6) First and second polycrystalline semiconductor films (31d) containing impurity ions of opposite conductivity type are patterned on an insulated semiconductor substrate (31a) of one conductivity type, and first and second element formation regions are formed. (A_1, A_2), and then insulate the first and second polycrystalline semiconductor films (31b, 31c) to form a supporting layer (3).
1) and laminating a base insulating film (32) and an element layer (33) on the support layer (31) to form an SOI substrate (
102), and forming a transistor element (T_n) on the SOI substrate (102).
_1, T_n_2), and then selectively penetrates the element layer (33) and the underlying insulating film (32) to form the first, T_n_2).
2 polycrystalline semiconductor films (31b, 31c) and a step of forming first and second metal electrodes (37a, 37b) connected to the first and second conductive electrodes (L_1, L_2), A method for manufacturing a semiconductor device, characterized in that a portion penetrating the element layer (33) is insulated.