JPH02166764A - Semiconductor device with capacitance element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a capacitance element having large electrostatic capacitance by forming a plurality of capacitors to the capacitance element and connecting these capacitors in parallel. CONSTITUTION:A capacitor 50 is composed of an impurity diffusion region 4a, capacitor insulating films 21a, 21b shaped onto the impurity diffusion region 4a, first capacitor electrodes 22a, 22b formed onto the capacitor insulating films 21a, 21b and insulated from the impurity diffusion region 4a, capacitor insulating films 23a, 23b coating the first capacitor electrodes 22a, 22b, and a second capacitor electrode 24 shaped onto the capacitor insulating films 23a, 23b and brought into contact with the impurity diffusion region 4a. Accordingly, a plurality of the capacitors are shaped, and these capacitors are connected in parallel, thus acquiring a semiconductor device having a capacitance element having large electrostatic capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a capacitive element and a method for manufacturing the same, and more particularly to a semiconductor device having a plurality of capacitive elements connected in parallel and a method for manufacturing the same.

[Prior Art] FIG. 4 is a sectional view of a semiconductor device including a conventional Brainer capacitor type memory cell, and FIG. 5 is an equivalent circuit diagram thereof. Next, the configuration of a conventional memory cell will be described with reference to FIGS. 4 and 5.

Memory cell 1 is a transistor 40 (switching element)
and a capacitor 50 (capacitive element).

The transistor 40 includes impurity diffusion regions 4a and 4b formed on the surface of the semiconductor substrate 2, a gate insulating film 7 formed on the surface region of the semiconductor substrate 2 sandwiched between the impurity diffusion regions 4a and 4b, and a gate. It is composed of a gate electrode 8 formed on an insulating film 7. Capacitor 50 is composed of impurity diffusion region 4a, capacitor electrode 6, and capacitor insulating film 5 sandwiched between them.

An interlayer insulating film 9 is formed on the gate electrode 8 and the capacitor electrode 6, and an impurity diffusion region 4b is formed on the interlayer insulating film 9.
A conductive layer 10 electrically connected to is formed. In addition,
Memory cell 1 is insulated and isolated from adjacent cells or elements by field oxide film 3 .

As shown in FIG. 5, conductive layer 10 is used as bit line B/L. Further, the gate electrode 8 is connected to the word line W/L. The capacitance of the capacitive element 50 includes a capacitance C of a charge storage portion and a junction capacitance Co. As can be seen from FIGS. 4 and 5, the memory cell 1 consists of one transistor 40 and one capacitor 50. .

Next, a method for manufacturing the conventional memory cell shown in FIG. 4 will be described with reference to FIGS. 6A to 6D.

First, referring to FIG. 6A, field oxide film 3, which is a thick oxide film for element isolation, is formed in a predetermined region of the main surface of semiconductor substrate 2. Referring to FIG. Next, using the patterned photoresist film as a mask, impurity ions are selectively implanted to form impurity diffusion regions 4a. Next, an oxide film 51 and a polycrystalline silicon film 61 are formed over the entire surface of the substrate.

Next, referring to FIG. 6B, the oxide film 51 and polycrystalline silicon film 61 are patterned into a predetermined shape using photolithography and etching. As a result, capacitor insulating film 5 and capacitor electrode 6 covering impurity diffusion region 4a are formed.

Next, referring to FIG. 6C, an oxide film and a polycrystalline silicon film are formed on a predetermined region or the entire surface, and patterned into a predetermined shape using photolithography and etching. As a result, gate oxide film 7 and gate electrode 8 are formed.

Next, referring to FIG. 6D, capacitor electrode 6 is masked with a photoresist film, and exposed surface 11 of semiconductor substrate 2 is masked.
Impurity ions are implanted into 12 to form an impurity diffusion region. The impurity diffusion region between gate electrode 8 and capacitor electrode 6 is electrically coupled to impurity diffusion region 4a. Impurity diffusion region 4 provided by this ion implantation process
a and 4b are formed in self alignment with the gate electrode 8a.

[Problems to be Solved by the Invention] Recently, semiconductor devices have become increasingly highly integrated. For this reason, in a semiconductor device having a capacitive element, it is difficult to ensure the capacitance of the capacitive element.

Therefore, a main object of the present invention is to provide a semiconductor device having a capacitive element with large capacitance and a method for manufacturing the same.

[Means for Solving the Problems] A capacitive element of a semiconductor device according to the present invention includes a first insulating film formed on an impurity diffused region, and a first insulating film formed on the first insulating film and insulated from the impurity diffused region. a first electrode formed on the first electrode; a second insulating film formed on the second insulating film, insulated from the first electrode and electrically connected to the impurity diffusion region; and a second electrode.

A method of manufacturing a semiconductor device having a capacitive element according to the present invention includes the steps of forming an impurity diffusion region in a capacitive element forming region of a semiconductor substrate, forming a first insulating film on the entire surface of the semiconductor substrate, and forming a first insulating film on the entire surface of the semiconductor substrate. forming a first conductive film thereon; and etching the first conductive film and the first insulating film in a predetermined region to leave the first insulating film and the first conductive film remaining on the impurity diffusion region. and exposing a part of the impurity diffusion region;
and forming a second conductive film on the exposed surface of the impurity diffusion region and on the second insulating film.

[Operation] In the present invention, an impurity diffusion region is provided in a capacitive element formation region of a semiconductor substrate. A first insulating film is provided on the impurity diffusion region, and a first conductive film is provided on the first insulating film. A second insulating film is provided on the first conductive film, and a second conductive film electrically connected to the impurity region is provided on the second insulating film. In this way, since a plurality of capacitors are provided and connected in parallel, a semiconductor device having a capacitive element with a large capacitance can be obtained.

Embodiment of the Invention FIG. 1 is a sectional view of a semiconductor device having a capacitive element according to an embodiment of the invention, and FIG. 2 is an equivalent circuit diagram thereof.

Next, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

The memory cell shown in FIG. 1 is the same as the conventional example shown in FIG. 4 except for the configuration of the capacitor 50, so the same parts are given the same reference numerals and the explanation will be omitted. The capacitor 50 includes an impurity diffusion region 4a, capacitor insulation films 21a and 21b formed on the impurity diffusion region 4a, and a first capacitor formed on the capacitor insulation films 21a and 21b and insulated from the impurity diffusion region 4a. Electrode 22a.

22b, capacitor insulating films 23a and 23b covering the first capacitor electrodes 22a and 22b, and a second capacitor electrode 24 formed on the capacitor insulating films 23a and 2Bb and in contact with the impurity diffusion region 4a. configured.

Ca shown in FIG. 2 is the capacitance of a capacitor constituted by the second capacitor electrode 24.degree. capacitor insulating film 23a and the first capacitor electrode 22a. cb is the capacitance of the capacitor constituted by the first capacitor electrode 22a, the capacitor insulating film 21a, and the impurity diffusion region 4a. Cc is the second capacitor electrode 24. This is the capacitance of the capacitor formed by the capacitor insulating film 23b and the first capacitor electrode 22b. Cd is the capacitance of the capacitor constituted by the first capacitor electrode 22b, the capacitor insulating film 21b, and the impurity diffusion region 4a.

FIGS. 3A to 3H are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG. 1. Next, Figures 38 to 3
A manufacturing method according to an embodiment of the present invention will be described with reference to FIG.

First, referring to FIG. 3A, field oxide film 3, which is a thick oxide film for element isolation, is formed in a predetermined region of the main surface of semiconductor substrate 2. Referring to FIG. Next, using the patterned photoresist film as a mask, impurity ions are selectively implanted to form impurity diffusion regions 4a. Next, an oxide film 21 and a polycrystalline silicon film 22 are formed over the entire surface of the substrate.

Next, referring to FIG. 3B, the oxide film 21 and polycrystalline silicon film 22 are patterned into a predetermined shape using photolithography and etching to expose surface regions 31 and 32 of the semiconductor substrate. . As a result, on the impurity diffusion region 4a, there is a region consisting of the capacitor insulating film 21a and the first capacitor electrode 22a, and a region consisting of the capacitor insulating film 22b and the first capacitor electrode 22b.
A region consisting of is formed.

Next, referring to FIG. 3C, an oxide film 23 is formed over the entire surface of the substrate.

Next, referring to FIG. 3D, surface regions 31 and 32 of the semiconductor substrate above impurity diffusion region 4a are exposed using photolithography and etching.

Next, referring to FIG. 3E, a polycrystalline silicon film 241 is formed over the entire surface of the substrate. At this time, the areas 31 and 3
2, the impurity diffusion region 4a and the polycrystalline silicon film 241 are electrically connected.

Next, referring to FIG. 3F, the polycrystalline silicon film in region 33 is removed using photolithography and etching. As a result, a second capacitor electrode 24 covering the impurity diffusion region 4a is formed.

Next, referring to FIG. 3G, gate oxide film 7 and gate electrode 8 of transistor 40 are formed.

Next, referring to FIG. 3H, the second capacitor electrode 24
is masked with a photoresist film, and impurity ions are implanted into the exposed surfaces 34 and 35 of the semiconductor substrate 2 to form impurity diffusion regions. An impurity diffusion region between gate electrode 8 and second capacitor electrode 24 is electrically coupled to impurity diffusion region 4a.

Impurity diffusion regions 4a and 4b provided by this ion implantation step are formed in a self-aligned manner with respect to gate electrode 8.

The memory cell shown in FIGS. 1 and 2 manufactured through the steps described above operates as follows. That is, a constant voltage v2 is applied to the first capacitor electrodes 22a and 22b. Next, by applying a constant voltage V to the word line W/L, the transistor 40 is made conductive. Thereafter, by applying a voltage corresponding to "0" or "1" to the bit line B/L made of the conductive layer 10, the capacitors Ca, C
Charges serving as information are accumulated in b, Cc, and Cd. Since the capacitors Ca, Cb, Cc, and Cd are all connected in parallel, the capacitance is larger than that of the conventional example. Reading of information is performed by turning on transistor 40 and then detecting a change in the potential of bit line B/L.

Note that in the above embodiment, the first capacitor electrode formed on the impurity diffusion region via the insulating film is divided into two, thereby providing four capacitors.
The first capacitor electrode does not have to be divided. In this case, 1. One capacitor is formed by the first capacitor electrode, the capacitor insulating film thereon, and the second capacitor electrode further above it. In addition,
On the contrary, the number of divisions of the first capacitor electrode is 3.
It may be more than that.

Further, in the above embodiment, the capacitor insulating film partially contacts the impurity diffusion region 4a, but the capacitor insulating film may have a structure in which the entire capacitor insulating film contacts the impurity diffusion region 4a. Furthermore, the second capacitor electrode only needs to be electrically connected to the impurity diffusion region of the capacitor, and its contact area may be any size.

In the above embodiment, an oxide film is used as the capacitor insulating film, but a film with a large dielectric constant such as St, N4 film, Ta20B film, or a multilayer insulating film made of a combination of these may also be used. By using such membranes, larger capacities can be obtained.

Further, although the capacitor insulating films are formed of the same material in the above description, the insulating films may be formed of different materials for each capacitance unit.

Furthermore, in order to increase the p/n junction capacitance, p+
It is also possible to perform two implantations: injection and n+ implantation.

[Effects of the Invention] As described above, according to the present invention, a capacitive element is provided with a plurality of capacitors and these are connected in parallel, so that a semiconductor device having a capacitive element with a large capacitance can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device having a capacitive element according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. FIGS. 3A to 3H are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 4 is a sectional view of a semiconductor device including a conventional planar capacitor type memory cell, and FIG. 5 is an equivalent circuit diagram thereof. FIGS. 68 to 6D are cross-sectional views showing a conventional method of manufacturing the memory cell shown in FIG. 4. In the figure, 1 is a memory cell, 2 is a semiconductor substrate, 4a,
4b is an impurity diffusion region, 7 is a gate oxide film, 8 is a gate electrode, 10 is a conductive layer, 21a, 21b. 23a and 23b are capacitor insulating films, 22a and 22b are first capacitor electrodes, 24 is a second capacitor electrode,
40 is a transistor, and 50 is a capacitor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) First electrodes formed at intervals on the surface of the semiconductor substrate.
and a switching element including a second impurity diffusion region and a conductive film located between the first and second impurity diffusion regions and formed on the surface of the semiconductor substrate with an insulating film interposed therebetween; a first insulating film formed on either one of the first and second impurity diffusion regions of the switching element;
a first electrode formed on the first insulating film and insulated from one of the impurity diffusion regions; a second insulating film formed on the first electrode; and the second insulating film. a second electrode formed on the first electrode and electrically connected to one of the impurity diffusion regions; and the first and second impurities of the switching element. A semiconductor device having a capacitive element, comprising a wiring layer electrically connected to the other diffusion region and for inputting/outputting signals exchanged with the capacitive element via the switching element. (2) A method for manufacturing a semiconductor device having a capacitive element, comprising: forming an impurity diffusion region in the capacitive element forming region of a semiconductor substrate; forming a first insulating film on the entire surface of the semiconductor substrate; forming a first conductive film on the first insulating film; etching the first conductive film and the first insulating film in a predetermined region to form the first insulating film on the impurity diffusion region; and a step of leaving the first conductive film and exposing a part of the impurity diffusion region; and a step of covering the first conductive film on the impurity diffusion region with a second insulating film; A method of manufacturing a semiconductor device having a capacitive element, the method comprising: forming a second conductive film on the exposed surface of the impurity diffusion region and the second insulating film.