JPH07153955A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To shorten a channel easily by forming a first semiconductor film and a second semiconductor film and then forming a third semiconductor film. CONSTITUTION:An SiO2 film is deposited on a semiconductor substrate to form an insulator 11, and a-Si is deposited and patterned to shape a first semiconductor film 12. A film 21aA for forming a lower insulator layer, a film 21bA for forming an intermediate layer, a film 21cA for forming an upper insulator layer and a film 13A for forming a second semiconductor layer are shaped. The films for forming each layer are patterned to form an interposing film 21 consisting of the lower insulator layer 21a, the intermediate layer 21b and the upper insulator layer 21c and the second semiconductor film 13. An insulator film 22 for floating the intermediate layer, a film 14A for forming a third semiconductor film, a film 15A for forming a gate insulating film and a film 16A for forming a gate electrode are shaped and patterned to form the third semiconductor film 14. Since a diffusion into the third semiconductor film 14 of impurities in the first and second semiconductor films 12, 13 is reduced extremely, channel length is controlled by the thickness of the interposing film 21, thus easily shortening a channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a thin film transistor for forming an IC on an insulator.

A thin film transistor, which can be formed on an insulator such as a glass plate, has recently been used as an accessory to a pixel of a liquid crystal display device.
If the C circuit is constructed, the circuit has a feature that it can be easily laminated, and is therefore expected as a transistor for a three-dimensional IC. On the other hand, the power supply voltage of the IC is changing from 5V to 3V level.

Under such circumstances, the present invention is easy to shorten the channel, has a large controllable range of the threshold voltage (Vth), is suitable for high integration, and is also convenient for the structure of the memory. It is intended to provide a thin film transistor.

[0004]

2. Description of the Related Art FIG. 10 is a side view of a conventional example of a thin film transistor. In FIG. 10, 1 is a base insulator, 2 is a first semiconductor film serving as one source / drain region, 3 is a second semiconductor film serving as the other source / drain region, and 4 is a third semiconductor film serving as a channel region. 5 is a gate insulating film, 6
Is a gate electrode, 7 is an insulator film, and 8, 9, 10 are wirings connected to the first semiconductor film 2, the second semiconductor film 3 and the gate electrode 6, respectively.

The first semiconductor film 2, the second semiconductor film 3 and the third semiconductor film 4 are integrated polycrystalline or amorphous semiconductor films, and the first semiconductor film 2 and the second semiconductor film 3 are integrated as described above. After forming the gate insulating film 5 and the gate electrode 6 on the semiconductor film, p-type or n-type impurities are ion-implanted and activated by heat treatment.

[0006]

By the way, the thin film transistor of the above-mentioned conventional example, when viewed as an IC structure,
Impurities in the semiconductor films 2 and 3 largely diffuse into the third semiconductor film 4 during the activation heat treatment, so that the channel length becomes unstable and it is difficult to shorten the channel length. Vth can be changed by changing the material of the gate electrode 5. Can be controlled,
The controllable range is small, the semiconductor films 2, 3 and 4 are arranged in a plane, which occupies a large area and is disadvantageous for high integration. It is not always convenient for the memory configuration.
There is such a problem.

Therefore, the present invention relates to a thin film transistor for forming an IC on an insulator, which is easy to shorten the channel, has a large controllable range of Vth, is suitable for high integration, and is suitable for a memory structure. It is an object to provide a thin film transistor which is convenient.

[0008]

FIG. 1 is an explanatory view of a main part of a thin film transistor according to the present invention, and (a) to (d) individually show various forms of the main part.

With reference to FIG. 1, in order to achieve the above object, a thin film transistor according to the present invention includes a first semiconductor film 12 provided on an insulator 11 and serving as one source / drain region, and a first semiconductor film. The intervening film 2 laminated on the film 12
1 and one end of which is laminated on the intervening film 21 to form one surface together with one end of the intervening film 21 and which is insulated and separated from the first semiconductor film 12 by the intervening film 21 to become the other source / drain region. The semiconductor film 13, the third semiconductor film 14 that covers the first end of the intervening film 21 and is in contact with the first semiconductor film 12 and the second semiconductor film 13 to be a channel region, and the gate insulating film 15 that covers the third semiconductor film 14. And the gate electrode 16 provided on the gate insulating film 15 including a portion facing the one end of the interposition film 21, the interposition film 21 includes:
As in (a) and (b), the upper and lower insulator layers 21c and 21c
It is characterized by a multi-layer structure having a and a conductive intermediate layer 21b sandwiched therebetween. Then, the intervening film 21
The intermediate layer 21b of 1 has one end in proximity to the third semiconductor film 14 and is electrically floating as shown in (a), or
As in (b), it is desirable that one end is in contact with the third semiconductor film 14 and the other end is electrically insulated.

In the thin film transistor, the intervening film 21 has a multilayer structure having an insulating layer 21d and a high dielectric layer 21e as shown in (c), instead of the above-mentioned multilayer structure, or ( As shown in d), it is characterized by having a single layer structure of a high dielectric (high dielectric layer 21e).

Further, any two of the above-mentioned thin film transistors including the duplication thereof are characterized by being arranged so as to face each other with the first semiconductor film 12 and the gate electrode 16 shared, respectively, with the gate electrode 16 as the center.

In each of the thin film transistors described above, the wiring connected to the first semiconductor film 12 is led out to the lower side of the thin film transistor, and the end of the first semiconductor film 12 opposite to the gate electrode 16 is the second semiconductor. It is characterized in that it is near the edge of the membrane 13 or inside the edge.

[0013]

In each of the above-mentioned thin film transistors, the third semiconductor film 14 serving as the channel region is separate from the first semiconductor film 12 and the second semiconductor film 13 serving as the source / drain regions, and as will be described later, Since the third semiconductor film 14 is formed after forming the first semiconductor film 12 and the second semiconductor film 13, the diffusion of impurities in the first semiconductor film 12 or the second semiconductor film 13 into the third semiconductor film 14 is extremely high. small.
For this reason, the channel length is regulated by the thickness of the intervening film 21, so that it is easy to shorten the channel.

Then, as shown in (a) and (b), the intervening film 2 is formed.
1 has a conductive intermediate layer 21b, the intermediate layer 21
Since Vth can be changed by changing the material of b, the controllable range of Vth is increased in combination with changing the material of the gate electrode 16. In particular,
When the intermediate layer 21b is electrically floating as in (a), charges can be accumulated in the intermediate layer 21b by external charge injection, and thus the device can be used as an EPROM.

Further, as shown in (c) and (d), the intervening layer 21
Has a high-dielectric layer 21e, a capacitor is inserted between the source and the drain. Therefore, the 1-capacitor / 2-transistor DR according to the circuit of FIG.
AM cells can be constructed.

Further, when the two transistors are opposed to each other as described above, the circuit to be used is limited, but the occupied area is smaller than that in the case of separate circuits, which is convenient for high integration. Further, when the end of the first semiconductor film 12 opposite to the gate electrode 16 is formed as described above, the area occupied by the transistor itself is reduced and the wiring is distributed above and below the transistor, which is convenient for high integration. Is.

[0017]

EXAMPLES Examples of thin film transistors according to the present invention will be described below with reference to FIGS. FIG. 2 shows the first embodiment
And FIG. 3 is a side view showing a modification of the first embodiment, FIG. 4 is a side view showing the second embodiment and its manufacturing process, and FIG. 5 is a side view showing the third embodiment and its manufacturing process. Figure, Figure 6
Is a circuit diagram of a DRAM configured by using the third embodiment, FIG. 7 is a side view of the first modification of the third embodiment, FIG. 8 is a side view of the second modification of the third embodiment, and FIG. It is a side view which shows a manufacturing process, and the same code | symbol shows the same target object through all the drawings.

In FIG. 2, Example 1 is a case where the above-mentioned intervening film has a conductive intermediate layer and the intermediate layer is electrically floating, and the structure shown in FIG. Make up.
(A)-(e) shows the manufacturing process mentioned later.

Reference numeral 11 is a base insulator, 12 is a first semiconductor film which will be one of the source / drain regions, 13 is a second semiconductor film which will be the other source / drain region, and 14 is a third semiconductor film which will be a channel region. Reference numeral 15 is a gate insulating film, 16 is a gate electrode, 17 is an insulating film, and 18, 19 and 20 are the first semiconductor film 12, the second semiconductor film 13, and the gate electrode 1, respectively.
Wiring connected to 6.

Reference numeral 21 is an intervening film for insulating the second insulator film 13 from the first insulator film 12, and 21a, 21b,
Reference numeral 21c is a lower insulator layer, a conductive intermediate layer, and an upper insulator layer in the intervening film 21, respectively, and 22 is an intermediate layer floating insulation that insulates the intermediate layer 21b from the third semiconductor layer 14 and electrically floats them. Body membranes.

In the embodiment 1, the channel length is stably determined by the sum of the thickness of the intervening film 21, the thickness of the second semiconductor film 13 and the thickness of the insulating film 22 for floating the intermediate layer.
It is easy to shorten the channel.

Further, just as Vth changes due to the difference in the material of the gate electrode 16, Vth also changes due to the difference in the material of the intermediate layer 21b, so that Vth can be controlled in a wide range by appropriately combining the two. . For example, a p-type semiconductor gate electrode 16 and an n-type semiconductor intermediate layer 2
1b, n-type semiconductor gate electrode 16 and p-type semiconductor intermediate layer 2
1b, conductor gate electrode 16 and conductor intermediate layer 21b, conductor gate electrode 16 and p-type semiconductor intermediate layer 21b
(P-channel type), the gate electrode 16 of the conductor and the intermediate layer 21b of the n-type semiconductor
(N-channel type), V is higher than that without the intermediate layer 21b.
Th can be lowered.

Since the intermediate layer 21b electrically floats and functions as a floating gate, charges can be injected into the intermediate layer 21b by applying a voltage between the first semiconductor film 12 and the second semiconductor film 13. To use E
It can be used as a PROM.

The insulator 11 may be an insulator film provided on a semiconductor substrate on which an IC circuit is formed. If it does so, a three-dimensional IC will be comprised. The first embodiment described above can be manufactured as follows.
It is a p-channel type, and the combination of the gate electrode 16 and the intermediate layer 21b is the same as above when the gate electrode 16 is W (tungsten).
This is the case.

First, referring to (a), S is formed by a CVD method on a semiconductor substrate on which an IC circuit is formed and whose surface is flattened.
The insulator 11 is formed by depositing iO ₂ to a thickness of 200 nm. On top of that, a-Si having a thickness of 100 n is formed by the CVD method.
m and is patterned by etching using a mask to form the first semiconductor film 12. After that, B (boron) is ion-implanted into the first semiconductor film 12. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ /
cm ²

Next, referring to (b), SiO ₂ is deposited to a thickness of 20 nm by a CVD method to form a lower insulator layer forming film 21aA, and a-Si is formed thereon by a CVD method.
Is deposited to a thickness of 100 nm and P (phosphorus) is ion-implanted to form an intermediate layer forming film 21bA. The implantation conditions are energy of 30 keV and dose of 5 × 10 ¹⁴ / cm ² . After that, SiO ₂ is formed to a thickness of 20 nm by the CVD method.
To form an upper insulator layer forming film 21cA.

Next, referring to (c), a-Si is deposited to a thickness of 100 nm by a CVD method, and B is ion-implanted to form a second semiconductor film forming film 13A. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ /
cm ² Then, by heat treatment, the first semiconductor layer 1
2. The intermediate layer forming film 21bA and the second semiconductor film forming film 13A are activated.

Next, referring to (d), the second semiconductor film forming film 13A, the upper insulating layer forming film 21cA, the intermediate layer forming film 21bA and the lower insulating layer forming film 13A are formed by etching using a mask. The film 21aA is patterned to form the intervening film 21 including the lower insulating layer 21a, the intermediate layer 21b, and the upper insulating layer 21c, and the second semiconductor film 13. After that, the intermediate layer floating insulator film forming film 22A made of SiO _{2 and having a} thickness of 20 nm is formed by the thermal oxidation method, and the first semiconductor film 12 and the second semiconductor film 12A are formed by the RIE method using a mask as shown in the figure. The intermediate layer floating insulator film 22 is formed while exposing a part of the film 13.

Then, referring to (e), a-Si is deposited to a thickness of 20 nm by a CVD method to form a third semiconductor film forming film 14A, and a gate insulating film having a thickness of 5 nm is formed by a thermal oxidation method. A film 15A for forming a gate electrode is formed, and W is deposited thereon to a thickness of 200 nm by a CVD method to form a film 16A for forming a gate electrode.

Next, referring to (f), the gate electrode forming film 16A, the gate insulating film forming film 15A and the third semiconductor film forming film 14 are etched by using a mask.
By patterning A, the third semiconductor film 14, the gate insulating film 15, and the gate electrode 16 are formed. Then CV
SiO ₂ is deposited to a thickness of 200 nm by the D method to form an insulator film 17, and wirings 18, 19 and 20 are further formed to complete the process.

In the above process, the third semiconductor film which becomes the channel region may be formed later separately from the first semiconductor film 12 and the second semiconductor film 13 which become the source / drain regions and exposed to a high temperature. Therefore, the first semiconductor film 12
And the impurity diffusion from the second semiconductor film 13 is extremely small. This stabilizes the channel length, which is approximately 260 nm in the above case.

The intermediate layer floating insulator film forming film 22A formed in (d) may be SiN deposited to a thickness of 20 nm by the CVD method instead of SiO ₂ . The Vth control effect of the intermediate tank 21b increases as the permittivity increases.

Further, the first semiconductor film 12 and the second semiconductor film 1
The material of the third and third semiconductor films 14 may be poly-Si. The materials of the other parts are not limited to the above and can be appropriately selected. Some examples are
This is shown in Examples 2 to 4 described later.

By the way, in the above-mentioned first embodiment, since all the three wirings 18, 19 and 20 are led out to the upper side of the transistor, the occupied area is not much different from the conventional example described above. Focusing on this point, the occupied area is reduced in the modification of the first embodiment shown in FIG.

In FIG. 3, a modification of the first embodiment is as follows.
The right end of the first semiconductor film 12 shown in FIG.
The wiring 18 connected to the first semiconductor film 12 is led out to the lower side of the transistor. The right end position of the first semiconductor film 12 is preferably near the right end position of the second semiconductor film 13 or on the left side thereof. Further, the wiring 18 can be easily led out to the lower side by forming the insulator 11 in a multi-layered structure. As a result, the occupied area of this modified example is reduced by about 20% to 30% as compared with the first embodiment. as a result,
The wirings 18, 19 and 20 are distributed above and below the transistor, which is convenient for high integration.

In FIG. 4, this Example 2 is a case where the above-mentioned intervening film has a conductive intermediate layer and the intermediate layer is in contact with the third semiconductor film, and the structure shown in FIG. Eggplant
(A)-(d) shows the manufacturing process mentioned later. Compared to the first embodiment, the intermediate layer floating insulator film 22 is removed and one end of the intermediate layer 21b is in contact with the third semiconductor film 14. As a matter that can be appropriately selected, the gate electrode 16 is set to W as in the first embodiment, but the intermediate layer 21b, which is a semiconductor in the first embodiment, is made of conductive TiN, and Si is used.
The gate insulating film 15 which was O ₂ was made of high dielectric BaMgF.
_{It is set to 4} . 23 on the second semiconductor film 13 which is not in Example 1 is an insulator film.

In the form of the second embodiment, the channel length is stably determined by the thickness of the intervening film 21, so that it is easy to shorten the channel. Further, the fact that Vth can be controlled in a wide range by the combination of the material of the gate electrode 16 and the material of the intermediate layer 21b is similar to that described in the first embodiment, and the combination here corresponds to the one described above. To do. Naturally, the middle layer 2
Although the contact of 1b with the third semiconductor film 14 cannot be the EPROM described in the first embodiment, the Vth control by the intermediate layer 21b becomes more effective, and the gate insulating film 1
The fact that 5 is a high dielectric also means that Vth due to the gate electrode 16
Make control more effective.

The second embodiment can be manufactured as follows. The case of the n-channel type is taken as an example. First, referring to (a), as in the case of FIG. 2 (a), the insulator 11 of SiO ₂ and the first semiconductor film 1 of a-Si are formed.
2 (thickness 100 nm) is formed. After that, P ions are implanted into the first semiconductor film 12. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ / cm ² .

Then, referring to (b), SiO ₂ is deposited to a thickness of 20 nm to form a lower insulator layer forming film 21aA, and TiN is formed thereon to a thickness of 100 n by a sputtering method.
m to form an intermediate layer forming film 21bA, and SiO ₂ is deposited thereon to a thickness of 20 nm to form an upper insulator layer forming film 21cA. Further thereon, a-Si is deposited to a thickness of 100 nm and P is ion-implanted to form a second semiconductor film forming film 13A. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ / cm ² .
After that, the first semiconductor layer 12 and the second semiconductor film forming film 13A are activated by heat treatment.

Next, with reference to (c), the second semiconductor film forming film 13A, the upper insulating layer forming film 21cA, the intermediate layer forming film 21bA and the lower insulating layer forming film 21aA are formed as shown in the figure. After patterning, the insulator film 23 is formed by depositing SiN to a thickness of 100 nm by the CVD method.

Next, referring to (d), the insulator film 23, the second semiconductor film forming film 13A, the upper insulator layer forming film 21cA, the intermediate layer forming film 21bA and the lower insulating film are etched by using a mask. A part of the body layer forming film 21aA is removed as shown to form the intervening film 21 including the lower insulator layer 21a, the intermediate layer 21b, and the upper insulator layer 21c, and the second semiconductor film 13, and A part of the first semiconductor film 12 is exposed. After that, a-Si is formed to a thickness of 20 n by the CVD method
to form a third semiconductor film forming film 15A, and then BaMgF ₄ is continuously deposited to a thickness of 20 nm by a vapor deposition method to form a gate insulating film forming film 15A. W is deposited thereon to a thickness of 200 nm to form a gate electrode forming film 16A.

Next, referring to (e), the gate electrode forming film 16A, the gate insulating film forming film 15A and the third semiconductor film forming film 14A are patterned to form the third semiconductor film 14 and the gate insulating film 15. And the gate electrode 16 is formed. After that, SiO ₂ is deposited to a thickness of 200 nm to form the insulator film 17, and the wirings 18, 19 and 20 are further formed.
To complete.

In the above process, the third semiconductor film 14 is not exposed to a high temperature as in the case of manufacturing the first embodiment, so that the channel length is stable, and in the above case, it is almost 140.
nm.

Since the arrangement of the first semiconductor film 12 in the second embodiment is similar to that of the first embodiment described with reference to FIG. 2, the modification of the first embodiment is performed as shown in FIG. This is convenient for high integration.

In FIG. 5, Example 3 is a case where the intervening film described above has a high dielectric layer, and has a structure shown in (e). (A)-(d) shows the manufacturing process mentioned later. In comparison with Example 2, in Example 2, the lower insulator layer 2
The intervening film 21 composed of 1a, the intermediate layer 21b and the upper insulator layer 21c is composed of the insulator layer 21d and the high dielectric layer 21e. Here, the high dielectric material of the high dielectric material layer 21e is T
a ₂ O ₅ is used. Further, as a matter that can be appropriately selected, the gate insulating film 15 is made of SiO ₂ and the insulator film 23 is made of SiO ₂ as in the first embodiment.

In the third embodiment, the channel length is stably determined by the thickness of the intervening film 21 as in the second embodiment, so that the channel can be shortened easily. Further, the high-dielectric layer 21e is interposed between the first semiconductor film 12 and the second semiconductor film 13, and the first semiconductor film 12 and the second semiconductor film 13 are interposed.
Since a capacitor having a counter electrode as a counter electrode is configured, a transistor having a large capacitance different from the normal parasitic capacitance is connected between the source and the drain.

This transistor is a 1-capacitor / 2-transistor DRAM by the circuit shown in FIG.
A cell can be constructed. This DRAM cell is a commonly used 1-capacitor / 1-transistor DRA.
It has a feature that writing or erasing (accessing) is faster than the M cell.

In the third embodiment, since the capacitor is contained within the transistor area, 1 capacitor /
Even if a two-transistor DRAM cell is constructed, the required area can be made small so as not to be much different from the usual one-capacitor / one-transistor DRAM cell.

The above Example 3 can be manufactured as follows in accordance with FIG. The case of the n-channel type is taken as an example. First, referring to FIG.
An insulator 11 of SiO ₂ and a first semiconductor film 12 (thickness: 100 nm) of a-Si are formed in the same manner as in (a). After that, P ions are implanted into the first semiconductor film 12. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ /
cm ²

Next, referring to (b), SiO ₂ is deposited to a thickness of 100 nm by a CVD method, and patterned to form an insulator layer forming film 21dA, and CVD is performed thereon.
Depositing a Ta ₂ O ₅ with a thickness of 20nm by law to form a high dielectric layer-forming film 21ea, further thereon, a-Si
Is deposited to a thickness of 100 nm, and P is ion-implanted to form the second semiconductor film forming film 13A. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ / cm ² . Then, by heat treatment, the first semiconductor layer 12 and the second semiconductor layer 12
The semiconductor film forming film 13A is activated. And the second
Semiconductor film forming film 13A and high dielectric layer forming film 21
Pattern eA as shown.

Next, referring to (c), SiO ₂ is deposited to a thickness of 100 nm by a CVD method to form an insulator film 23, and thereafter, the insulator film 23 and the second semiconductor film are etched by using a mask. A part of the forming film 13A, the high dielectric layer forming film 21eA, and the insulator layer forming film 21dA is removed as shown in the figure, and the insulator layer 21d and the high dielectric layer 21 are removed.
The intervening layer 21 made of e and the second semiconductor layer 13 are formed, and a part of the first semiconductor film 12 is exposed.

Next, referring to (d), a-Si is deposited to a thickness of 20 nm to form a third semiconductor film forming film 14A, and a 5 nm thick gate insulating film forming film 15A is formed by a thermal oxidation method. Is formed and W is deposited thereon to a thickness of 200 nm to form a gate electrode forming film 16A.

Next, with reference to (e), the gate electrode forming film 16A, the gate insulating film forming film 15A and the third semiconductor film forming film 14A are patterned to form the third semiconductor film 14 and the gate insulating film 15 And the gate electrode 16 is formed. After that, SiO ₂ is deposited to a thickness of 200 nm to form the insulator film 17, and the wirings 18, 19 and 20 are further formed.
To complete.

In the above steps, the third semiconductor film 14 is not exposed to high temperature as in the case of manufacturing the first embodiment, so that the channel length is stable, and in the above case, it is almost 120.
nm.

In FIG. 7, a first modification of the third embodiment.
Is an example of the case where the intervening film 21 of Example 3 is composed of only the high dielectric layer 21e. The high dielectric layer 21e here is
It is made of Ta ₂ O ₅ as in Example 3, and the thickness of the portion overlapping with the insulator layer 21d in Example 3 is 200 nm, and the thickness of the other portions is 50 nm. The usage of this modified example 1 is based on that of the third embodiment.

The first modification can be manufactured according to the manufacturing of the third embodiment described above with reference to FIG. 5, and the formation of the insulator layer forming film 21dA is deleted in the step of FIG. 5B. Then, after depositing Ta ₂ O ₅ to a thickness of 200 nm, the portion having a thickness of 50 nm may be thinned by the RIE method using a mask to form the high dielectric layer forming film 21eA.
The channel length is approximately 200 nm.

In FIG. 8, a second modification of the third embodiment.
Is another example of the case where the intervening film 21 of Example 3 is composed of only the high dielectric layer 21e. High dielectric layer 21e here
Is made of Ta ₂ O ₅ as in Example 3, and has a thickness of 50 nm over the entire region. The usage of this modified example 2 also conforms to the third embodiment.

The modification 2 can be manufactured in the same manner as the modification 1 described above according to the manufacture of the embodiment 3 described above with reference to FIG. 5, and in the step of FIG. 5B, the insulating layer is formed. The formation of the formation film 21dA may be omitted, and Ta ₂ O ₅ may be deposited to a thickness of 50 nm to form the high dielectric layer formation film 21eA. The channel length is approximately 50 nm.

Since the arrangement of the first semiconductor film 12 is the same as that of the first embodiment described with reference to FIG. 2 in the above-described third embodiment and the first and second modifications thereof, the modification of the first embodiment shown in FIG.
By doing so, it becomes convenient for high integration. Further, as can be understood from the description of the third embodiment and the modified examples 1 and 2, the capacitance of the capacitor described in the third embodiment can be appropriately increased / decreased by the structure of the intervening film 21.

In FIG. 9, Example 4 is a case where two transistors are opposed to each other by sharing the first semiconductor film and the gate electrode. The transistors to be opposed to each other can be any two including the overlapping of the transistors of the forms of the first to third embodiments described above, but here, the p-channel transistor and the n-channel type of the form of the second embodiment are used. The transistors are opposed to each other and have a structure shown in (f). (A)-(e) shows the manufacturing process mentioned later. Then, as a matter that can be appropriately selected, the gate insulating film 15 is BaMgF ₄ used in the second embodiment, the gate electrode 16 is W, and the intermediate layer 21b of the intervening film 21 is the semiconductor used in the first embodiment.

Such a structure facing each other can be used for an inverter circuit, a memory, etc., and occupies a smaller area than arranging two transistors individually, which is convenient for high integration. Further, the characteristic features of the individual transistors facing each other will be understood from the description of the first to third embodiments.

The fourth embodiment can be manufactured as follows. First, referring to (a), an insulator 11 of SiO ₂ is formed in the same manner as in FIG. 2 above, and a W film (thickness 100 nm), a TiN film (thickness 20 nm) and a Ti film are formed thereon by a sputtering method. Films (thickness 10 nm) are sequentially deposited and patterned to form wirings 18 and 19 made of W film.
Then, contacts 18a and 19a made of a TiN film and a Ti film are formed. After that, SiO ₂ is deposited and processed to expose the contacts 18a and 19a to form an insulator 11a flush with the contacts.

Next, referring to (b), a Ti film (thickness 2
0 nm) and an a-Si film (thickness 100 nm) are sequentially deposited and patterned to form the first semiconductor film 12 in contact with the contact 18a and the second semiconductor film connecting portion 13a in contact with the contact 19a. . After that, P is on the right side and B is on the left side of the center of the first semiconductor film 12.
Is ion-implanted. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ / cm ² .

Next, referring to (c), SiO ₂ is deposited to a thickness of 20 nm and patterned so as to cover only the upper surface and side surfaces of the first semiconductor film 12 to form a lower insulator layer forming film 21aA. To do. On top of that, a-Si with a thickness of 10
The intermediate layer forming film 21bA is formed by depositing 0 nm, and B is ion-implanted on the right side and P is ion-implanted on the left side with the center of the first semiconductor film 12 as a boundary. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹³ / cm ² . Then, the intermediate layer forming film 21bA is patterned so as to cover only the upper surface and side portions of the lower insulator layer forming film 21aA. Then, SiO ₂ is deposited to a thickness of 20 nm to form an upper insulator layer forming film 21cA, and is patterned so as to cover only the upper surface and side portions of the intermediate layer forming film 21bA.

Next, referring to (d), a-Si is deposited to a thickness of 100 nm, P is ion-implanted on the right side and B is ion-implanted on the left side with the center of the first semiconductor film 12 as a boundary. Second
The semiconductor film forming film 13A is formed. The implantation conditions are energy of 30 keV and dose of 3 × 10 ¹⁵ /
cm ² The second semiconductor film forming film 13A is in contact with the second semiconductor film connecting portion 13a at the left and right portions. afterwards,
By the heat treatment, the first semiconductor layer 12 and the intermediate layer forming film 21 are formed.
bA, the second semiconductor film forming film 13A and the second semiconductor film connecting portion 13a are activated.

Next, with reference to (e), the second semiconductor film forming film 13A is patterned, and SiO ₂ is formed to a thickness of 100.
After forming the insulator film 23 by depositing the insulator film 23 to a thickness of 2 nm, the insulator film 23, the second semiconductor film forming film 13A, the upper insulator layer forming film 21cA, the intermediate layer forming film 21bA and the lower insulator layer are etched. The central portion of the forming film 21aA is removed as shown, and the intervening film 21 including the lower insulator layer 21a, the intermediate layer 21b, and the upper insulator layer 21c, and the second semiconductor film 13 are formed on each of the left and right sides. At the same time, the central portion of the first semiconductor film 12 is exposed.

Next, referring to (f), a-Si is deposited to a thickness of 20 nm by the CVD method to form a third semiconductor film forming film (14A of Example 2), and the film is continuously deposited by the evaporation method. BaMgF ₄ is deposited to a thickness of 20 nm to form a film (15A of Example 2) for forming a gate insulating film, and W is formed on the film.
Is deposited to a thickness of 200 nm to form a gate electrode forming film (16A of Example 2) in which the central recess is sufficiently filled.
Then, these films are patterned to form the third semiconductor film 14, the gate insulating film 15, and the gate electrode 16. After that, the insulator film 1 of SiO ₂ (thickness 200 nm)
And a wiring 20 for connecting to the gate electrode 16
Is completed on the upper side. The wirings 18 and 19 connected to the first semiconductor film 12 and the second semiconductor film 13 which will be the source / drain regions are already formed on the lower side. The left side of the two facing transistors is a p-channel type and the right side is an n-channel type.

In the fourth embodiment, the wiring 19 is used.
It will be easily understood that the wiring 18 can be led to the upper side, and further, the wiring 18 can be led to the upper side by making at least one of the two opposing transistors have a structure according to FIG.

[0069]

As described above, according to the present invention, a thin film transistor for forming an IC on an insulator can easily have a short channel, has a wide controllable range of Vth, and is suitable for high integration. Therefore, a thin film transistor which is convenient for the structure of a memory is provided, which has the effect of facilitating the high integration of the IC by the thin film transistor, and further facilitating the structure of a highly integrated three-dimensional IC. It greatly contributes to miniaturization of semiconductor devices.

[Brief description of drawings]

FIG. 1 is an explanatory view of a main part of a thin film transistor according to the present invention.

FIG. 2 is a side view showing Example 1 and its manufacturing process.

FIG. 3 is a side view of a modified example of the first embodiment.

FIG. 4 is a side view showing the second embodiment and its manufacturing process.

FIG. 5 is a side view showing the third embodiment and its manufacturing process.

FIG. 6 is a circuit diagram of a DRAM configured by using a third embodiment.

FIG. 7 is a side view of a first modification of the third embodiment.

FIG. 8 is a side view of a second modification of the third embodiment.

FIG. 9 is a side view showing Example 4 and its manufacturing process.

FIG. 10 is a side view of a conventional example.

[Explanation of symbols]

1, 11 and 11a Insulator 2, 12 First semiconductor film 3 serving as one source / drain region 3, 13 Second semiconductor film 4 serving as the other source / drain region 4, 14 Third semiconductor film serving as a channel region 5, 15 Gate insulating film 6,16 Gate electrode 7, 17, 23 Insulator film 8-10, 18-20 Wiring derived from transistor 21 Intervening film 21a Lower insulating layer 21b in intervening film 21c Conductive intermediate layer in intervening film 21c Upper insulating layer 21d in intervening film 21d Insulating layer in intervening film 21e High dielectric layer in intervening film 22 Insulating film for floating intermediate layer

Claims (6)

[Claims] 1. A first semiconductor film (12) provided on an insulator (11) to be one source / drain region, and an intervening film (21) laminated on the first semiconductor film (12).
And one end of which is laminated on the intervening film (21) to form one surface together with one end of the intervening film (21), and which is insulated from the first semiconductor film (12) by the intervening film (21) and is the other source.・
The second semiconductor film (13) that becomes the drain region and the first semiconductor film (1) that covers the one end of the intervening film (21).
2) and the third semiconductor film (14) which is in contact with the second semiconductor film (13) and serves as a channel region, the gate insulating film (15) covering the third semiconductor film (14), and the intervening film (21). A gate electrode (16) provided on the gate insulating film (15) including a portion facing one end.
The intervening film (21) has upper and lower insulating layers (21c, 21).
A thin film transistor having a multi-layer structure having a) and a conductive intermediate layer (21b) sandwiched therebetween. 2. The thin film transistor according to claim 1, wherein one end of the intermediate layer (21b) of the intervening film (21) is the third layer.
A thin film transistor, which is electrically floating in proximity to a semiconductor film (14). 3. The thin film transistor according to claim 1, wherein one end of the intermediate layer (21b) of the intervening film (21) is a third layer.
A thin film transistor, which is in contact with a semiconductor film (14) and is electrically insulated at the other end. 4. The thin film transistor according to claim 1, wherein the intervening film (21) has an insulating layer (21d) and a high dielectric layer (21e) in place of the multilayer structure according to claim 1. Or a thin film transistor having a high dielectric constant single layer structure. 5. Any two of the thin film transistors according to any one of claims 1 to 4, including the thin film transistor, may be a first semiconductor film (1).
2) The thin film transistor, wherein the thin film transistor is arranged so as to face each other with the gate electrode (16) as a center, sharing the gate electrode (16). 6. The thin film transistor according to claim 1, 2 or 3 or 4 or 5, wherein the wiring connected to the first semiconductor film (12) is led out to the lower side of the thin film transistor to form the first semiconductor film (12). The thin film transistor, wherein the end opposite to the gate electrode (14) is near or inside the same end of the second semiconductor film (14).