JPH06112433A - Semiconductor memory cell and formation method thereof - Google Patents

Abstract

PURPOSE:To secure the overlap allowance between the first, second leading out electrodes and a bit line, a capacitor contact by a method wherein the first, second leading out electrodes connecting to a drain and a source region are provided to be connected to a bit line and an accumulation electrode on an upper layer. CONSTITUTION:The stacked capacitor part of a memory cell is formed of an accumulation electrode 123 connected to the source region 110S of a switching transistor through the intermediary of the second lead-out electrode 116 and an opposite electrode 126 formed through the intermediary of an insulation capacitor film 125. Next, a drain region 110D is connected to a bit line 119a through the intermediary of the first lead- out electrode 115. On the other hand, the first and second lead-out electrodes 115, 116 connecting to the drain source regions 110D, 110S are provided. The first lead-out electrode 115 is connected to the bit line 119a on an oxide film 102 while the second lead-out electrode 116 is connected to right above accumulation electrode 123. In such a constitution, the bit line 119a and the accumulation electrode 123 are structured on different layers. Accordingly, it may be almost needless to consider the registration margin between an element region 127, the bit line 119a and the accumulation electrode 123.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell including an insulated gate field effect transistor and a laminated type capacitance section, and a method for forming the same.

[0002]

2. Description of the Related Art A semiconductor memory which stores binary information in the form of electric charge has a small cell area and is therefore excellent as a memory cell for a highly integrated and large capacity semiconductor memory. In particular, a memory cell including one transistor and one capacitor (hereinafter abbreviated as 1T1C cell) as a memory cell has few constituent elements and a small cell area, and is therefore important as a highly integrated memory cell. By the way, as the memory cell size is reduced due to the higher integration of the memory, the area of the capacitance portion in the 1T1C cell structure is decreasing. Then, the decrease in the storage charge amount due to the decrease in the area of the capacitance portion causes the problem of α particle resistance and the deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve such a problem, there is known a method of forming a large storage capacity portion despite the reduction of the memory cell area. For example, International Electron Devices Conference (International Electron Device Meeting)
on Devices Meeting) 1988,
See pages 592-595, "3-Dimensional Stacked Capacitor Cell Fore, 16M &.
64M Dyramus (3-DIMENSIONAL
STACKED CAPACITOR CELL FO
R 16M AND 64M DRAMS) ”, a capacitor portion of a 1T1C cell is formed on a bit line 219a to maximize the area of the capacitor portion as shown in FIGS. Further, in order to connect the bit line to the drain region of the switching transistor, the element region 227 is made convex in the drain region of the switching transistor to reduce the dimension between the bit lines in the word line 204 direction to miniaturize the memory cell size. Are shown.

[0004]

However, in the conventional structure in which the element region is overhanging in the drain region of the switching transistor to form a convex shape, there is a misalignment in the bit line direction between the element region pattern and the bit line contact pattern. If it occurs, the area of the convex portion forming the bit line contact 229 in the bit line direction decreases, and it becomes difficult to form the bit line contact. In order to avoid this, it is necessary to allow for a misalignment margin between the element region pattern and the bit line contact pattern in consideration of misalignment, which is a major obstacle to the reduction of the memory cell size.

An object of the present invention is to eliminate such conventional defects and provide a fine semiconductor memory cell suitable for high integration and a manufacturing method thereof.

[0006]

In order to achieve the above-mentioned object, a semiconductor memory cell according to the present invention is a semiconductor memory cell including one insulated gate field effect transistor and one stacked type capacitance section. A memory which is connected to the drain region of the gate field effect transistor and the bit line, is insulated from the gate electrode through an insulating film, covers the drain region of the insulated gate field effect transistor, and is adjacent to the word line region; The first extraction electrode having a shape that spreads over the isolation region of the cell is connected to the source region and the charge storage electrode of the insulated gate field effect transistor, and is insulated from the gate electrode via an insulating film and Covers the source region of the gate field effect transistor and extends up to the word line region and the isolation region. Those that are configured to include Therefore a second lead-out electrode shapes formed by the on the first lead-out electrode of the same conductor film has.

In the semiconductor memory cell according to the present invention, a step of forming an element isolation region, a gate insulating film, and a gate electrode on a semiconductor substrate, then covering the periphery of the gate electrode with an insulating film, and forming source / drain regions, A step of sequentially depositing a conductor film and an insulating film after opening a part of the source / drain region, a step of processing the insulating film into a first extraction electrode shape, and a resist patterning into a second extraction electrode shape. Formation including a step and a step of simultaneously forming the first and second extraction electrodes by etching the conductor film using the insulating film having the first extraction electrode shape and the resist having the second extraction electrode shape as an etching mask Obtained by the method.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor memory cell of the present invention, FIG. 2 is a sectional view taken along line AA of FIG.
FIG. 3 is a sectional view taken along line BB of FIG.

The stacked capacitor portion of the semiconductor memory cell of this embodiment has a storage electrode 12 connected to a source region 110S of a switching transistor via a second lead electrode 116.
3 and the counter electrode 126 formed via the capacitive insulating film 125. On the other hand, the drain region 110D of the switching transistor is connected to the bit line 119a via the first extraction electrode 115.

Drain region 110D and source region 1
First extraction electrode 1 connected to each of 10S in a self-aligned manner
15 and the second extraction electrode 116 are provided, and the first extraction electrode 115 extends onto the field insulating film 102 (separation region) that defines the element region 127, and the upper bit line 1 is formed there.
19a and the second extraction electrode is the storage electrode 12 immediately above.
It is connected with 3. Bit line 119a and storage electrode 12
Reference numeral 3 is a conductive film having a different layer order. Therefore, the element region 1
The alignment margin between 27, the bit line 119a and the storage electrode 123 need not be taken into consideration at all.

4 to 14 are schematic sectional views for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention. However, FIG. 4 to FIG. 9, FIG. 13, and FIG.
-A schematically shows a cross section of a portion corresponding to A, and Figs. 10 to 12 schematically show a cross section of a portion corresponding to line BB in Fig. 1.

As shown in FIG. 4, a field insulating film 2 is formed on an element isolation region on a p-type single crystal silicon substrate 1, a gate insulating film 3 is formed next, and a polysilicon film for a gate electrode is further formed. After sequentially depositing a conductive film (4) and an insulating film 5 such as the above, the resist film 6 having a gate electrode shape is patterned, and then the insulating film 5 and the conductive film (4) are etched using the resist film 6 as an etching mask. Word line 4
To form.

Next, as shown in FIG. 5, after removing the resist film 6, low-dose n-type impurities are implanted into the silicon substrate 1 by the ion implantation method to form low-concentration source / drain regions 7. After that, the silicon oxide film 8 is deposited on the entire surface.

Next, as shown in FIG. 6, a silicon oxide film 8 is formed.
Is etched back using an anisotropic etching technique to leave the silicon oxide film 8 on the side wall of the word line 4 which is a gate electrode, and a narrow slit 9 is formed between the gate electrodes. A high-concentration source / drain region 10 is formed by implanting a dose of n-type impurities into the silicon substrate 1 using an ion implantation method. The slit 9 and the high-concentration source / drain region 10 are self-aligned.

Next, as shown in FIG. 7, an n-type conductive film 11 such as polysilicon and an insulating film 12 are sequentially deposited, and then a resist film 13 is patterned so as to cover at least the drain region of the switching transistor.

Next, as shown in FIG. 8, the insulating film 12 is formed by using the anisotropic etching technique with the resist film 13 as a mask.
Are removed by etching, the resist film 13 is removed thereafter, and then the resist film 14 is patterned so as to cover at least the source region of the switching transistor.

Next, as shown in FIG. 9, a silicon oxide film 1 is formed.
The n-type conductive film 13 is removed by etching using the anisotropic etching technique with the resist film 2 and the resist film 14 as a mask to form the first extraction electrode 15 and the second extraction electrode 16.

Next, as shown in FIG. 10, the insulating film 1 is formed on the entire surface.
After depositing No. 7, a resist film 18 is formed by opening a part of the first extraction electrode 15 forming region.

Next, as shown in FIG. 11, a resist film 18 is formed.
Insulating film 1 using anisotropic etching technology with mask as mask
After removing 7 by etching and removing the resist film 8, for example, a tungsten silicide film 1 is used as a bit line forming material.
9 is deposited on the entire surface.

Next, as shown in FIG. 12, after the resist film 20 having a bit line shape is formed, the tungsten silicide film 19 is removed by etching using the resist film 20 as a mask and using an anisotropic etching technique.
To form.

Next, as shown in FIG. 13, a resist film 20.
After removing the film, an insulating film 21 is deposited on the entire surface, and a resist film 2 in which a part of the second extraction electrode 16 formation region is opened.
Form 2. Here, the illustration of the insulating film 12 is omitted for convenience.

Next, as shown in FIG. 14, a resist film 22
The insulating film 21 is removed by etching by using an anisotropic etching technique with the mask as a mask, an n-type conductive film 23 is then deposited on the entire surface, and then a resist film 24 having a shape of a charge storage electrode is patterned.

Next, as shown in FIG. 2, the n-type conductive film 23 is removed by etching using the anisotropic etching technique using the resist film 24 as a mask to form a storage electrode 123.
After that, the resist film 24 is removed, and further a capacitive insulating film 125 such as a thin silicon oxide film is formed so as to cover at least the surface of the charge storage electrode 123, and then the n-type conductive film 4 is formed.
5 is deposited to form a memory cell as a counter electrode 126. Further, as a method of forming the thin capacitance insulating film 125, there are a thermal oxidation method and a CVD method.

[0025]

As described above, according to the present invention, the first extraction electrode and the second extraction electrode which are respectively connected to the drain region and the source region of the switching transistor in a self-aligned manner are provided, and the upper bit line and the storage electrode, respectively. By connecting to, the alignment margin between the first and second extraction electrodes, the bit line contact and the capacitance contact can be secured without increasing the memory size of 1T1C. The memory size can be reduced, and the memory cell suitable for high integration can be easily obtained.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor memory cell of the present invention.

2 is a schematic cross-sectional view showing one embodiment of the semiconductor memory cell of the present invention, which is a cross-sectional view taken along the line AA of FIG.

3 is a schematic cross-sectional view showing one embodiment of the semiconductor memory cell of the present invention, which is a cross-sectional view taken along the line BB of FIG.

FIG. 4 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 5 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor memory cell of the present invention.

FIG. 7 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 8 is a schematic cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor memory cell of the present invention.

FIG. 9 is a schematic cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor memory cell of the present invention.

FIG. 10 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 11 is a schematic cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor memory cell of the present invention.

FIG. 12 is a schematic cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor memory cell of the present invention.

FIG. 13 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 14 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor memory cell of the present invention.

FIG. 15 is an exploded perspective view showing a conventional 1T1C memory cell.

FIG. 16 is a plan view showing a conventional 1T1C memory cell.

[Explanation of symbols]

 1, 101 p-type silicon substrate 2, 102 field insulating film 3, 103 gate insulating film 4, 104, 204 word line (gate electrode) 5, 105 insulating film 6 resist film 7 low concentration source / drain region 8 silicon oxide film 9 slits 10 high concentration source / drain region 110D drain region 110S source region 11 n-type conductive film 12 insulating film 13 resist film 14 resist film 15,115 first extraction electrode 16,116 second extraction electrode 17 insulating film 18 resist film 19 Tungsten silicide film 19a, 119a, 219a Bit line 20 Resist film 21, 121 Insulating film 22 Resist film 23 n-type conductive film 123, 223 Storage electrode 24 Resist film 125 Capacitive insulating film 126 Counter electrode 127, 227 Device region 128, 228 Capacitance Ko Tact 129,229 bit line contact

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[Procedure amendment]

[Submission date] October 1, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Entire surface

[Correction method] Change

[Correction content]

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[Figure 5]

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[Figure 9]

[Figure 10]

FIG. 11

[Fig. 12]

[Fig. 13]

FIG. 14

FIG. 15

FIG. 16

Claims (2)

[Claims] 1. In a semiconductor memory cell including one insulated gate field effect transistor and one stacked capacitor, the drain region of the insulated gate field effect transistor and a bit line are connected to each other and insulated from the gate electrode. A first extraction electrode having a shape that is insulated and separated through a film, covers the drain region of the insulated gate field effect transistor, and further extends on the word line region and the adjacent isolation region of the memory cell; and the insulated gate It is connected to the source region of the field effect transistor and the charge storage electrode and is insulated and separated from the gate electrode through an insulating film and covers the source region of the insulated gate field effect transistor and further extends to the word line region and the isolation region. And a second drawing electrode formed of the same conductive film as that of the first extraction electrode. A semiconductor memory cell provided with an output electrode. 2. A step of forming an element isolation region, a gate insulating film, and a gate electrode on a semiconductor substrate, and then covering the periphery of the gate electrode with an insulating film to form a source / drain region, and the source / drain region. A step of sequentially depositing a conductor film and an insulating film after opening a part of the above, a step of processing the insulating film into a first extraction electrode shape, a step of patterning a resist into a second extraction electrode shape, A semiconductor including a step of simultaneously forming the first and second extraction electrodes by etching the conductive film using an insulating film having one extraction electrode shape and a resist having the second extraction electrode shape as an etching mask. Method of forming a memory cell.