JPH01282859A - Mos type dynamic ram and manufacture of the same - Google Patents

Abstract

PURPOSE:To eliminate a leak current by making stepped grooves around memory cells arranged in hounds-tooth form and equipping a separation area on the bottom, a capacitor area in the upper part, and a switching transistor having a ring-shaped gate electrode in the lower part of each groove. CONSTITUTION:Memory cells 10 are arranged in hounds-tooth form on a silicon semiconductor substrate 20 and each cell 10 is surrounded by a stepped groove 11. A separation area 1 to separate the cells 10 from each other are formed on the bottom of each groove 11 and capacitor areas 2 are formed between said areas 1 and the ring-shaped gate electrodes 3a of switching transistors 3. Each transistor 3 consists of an electrode 3a to connect a word wire 5, a diffusion area 3c connected to one of the electrodes of the area 2, and a diffusion area 3b connected to a bit line 6. The ring-shaped electrodes of the transistors 3 prevent a leak current along the edges of the areas 1 from being generated and the threshold voltage of the transistors from changing following the exudation of a element separating high concentration impurity layer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a MOS type dynamic RAM having a plurality of memory cells, and particularly to a MOS type dynamic RAM having a plurality of memory cells mutually arranged in a staggered pattern. The present invention relates to the structure of a memory cell in a transistor, one-capacitor type MOS type Namic RAM, and its manufacturing method.

[Conventional technology]

As a conventional MOS type dynamic RAM having a plurality of memory cells of this type, for example, in a MOS type dynamic RAM using a folded pit line method, as shown in FIG. (below.

Data is transferred to each memory cell via each contact portion 4 connected to the BL (also referred to as BL) 6, and
A switching transistor (hereinafter referred to as a switching transistor) connected to a word line (hereinafter also referred to as WL) 5.

These data are stored in the capacitor region 2 of each memory cell by on/off control of the transistor (also referred to as Tr) 3.

In this configuration, in order to electrically insulate and isolate these cells from each other, between each of the memory cells, the isolation region 1 is formed of a radially thick insulating film, a deep groove, or a semiconductor substrate. An impurity layer of the same conductivity type but with a higher concentration is formed.

[Problem to be solved by the invention]

However, in the MOS type dynamic RAM configured as described above, even though no potential is applied to the switching Tr3, that is, the switching Tr3 is in the OFF state, the edge of the isolation region l is Along these lines, a leakage current as shown by the arrow is likely to occur, which often causes the inconvenience that data stored in the capacitor region 2 of each memory cell leaks out.
On the other hand, since the high concentration impurity layer for element isolation is diffused into the end of the isolation region 1, the channel width of the switching Tr 3 is inevitably narrowed, and the set threshold voltage vth There was also the problem that it could change.

The present invention was made to solve these conventional problems, and its purpose is to prevent leakage current from occurring along the edges of the isolation region, and to improve the performance of switching transistors. In addition to preventing threshold voltage fluctuations and obtaining stable MOS transistor characteristics, it is also possible to efficiently form a MOS transistor within a limited cell area. It is an object of the present invention to provide this type of MOS type dynamic RAM and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above-mentioned object, a MOS according to the present invention
In a type dynamic RAM, a plurality of memory cells are arranged in a staggered pattern, and two grooves are formed on the peripheral edge of each memory cell, one above the other. Switching transistors each having a ring-shaped gate electrode are provided in the capacitor region and the upper part of the intervening trench, and an isolation region is provided in the bottom of the trench so as to surround the capacitor region.

That is, the present invention provides a one-transistor, one-capacitor type MO5 type namic RAM including a plurality of memory cells arranged in a staggered pattern on a semiconductor substrate,
Upper and lower parts 2 formed at the peripheral edge surrounding each memory cell
a step groove, a capacitor region provided in the lower part of the groove, a ring-shaped gate electrode formed in the upper part of the groove, and one diffusion layer that becomes a source or drain connected to the capacitor region. , and a switching transistor having another diffusion layer formed on the substrate surface inside the gate electrode and serving as a drain or source connected to a data line via a contact, and the capacitor region at the bottom of the trench. A MOS type dynamic RAM characterized by comprising an isolation region surrounding the memory cells and isolating adjacent memory cells from each other,
In addition, it is a one-transistor, one-capacitor type MOS type dynamic RAM in which a plurality of memory cell parts are arranged in a staggered pattern on the surface of a semiconductor substrate, and a peripheral edge portion surrounding each memory cell on the surface includes: forming two upper and lower grooves consisting of a first groove portion serving as an upper portion of the groove and a second groove portion serving as a lower portion of the groove; and forming a separation region at the bottom portion of the second groove portion. a step of forming one diffusion region that will become the source or drain of the transistor on the exposed sidewall portion of the second groove portion;
With a thin insulating film interposed on the surface of one of the diffusion regions, the second groove portion is filled with polycrystalline silicon that will become one electrode of the capacitor region, and one of the diffusion regions will be filled with polycrystalline silicon that will become the other electrode of the same capacitor region. a step of opposing the diffusion region;
a step of forming a ring-shaped gate electrode via a gate oxide film on the side wall of the first groove portion or from the side wall to the surface of the substrate; and on the surface of the substrate inside the gate electrode; A MOS type dynamic RAM characterized in that it includes at least a step of forming another diffusion region that becomes a drain or a source of a transistor.
This is a manufacturing method.

[For production]

Therefore, in the present invention, a plurality of memory cells are arranged in a staggered pattern, two grooves are formed on the peripheral edge of each memory cell, and a capacitor is formed in the lower part of the groove. The regions are constructed by providing switching transistors each having a ring-shaped gate electrode in the upper part of the groove, and providing an isolation region surrounding the capacitor region in the bottom part of the groove. By arranging the corresponding switching transistor and capacitor regions so that they have the same effective cell area, the boundaries between these capacitor regions and isolation regions and the current flow in the channel region of the switching transistor are This prevents leakage current from occurring along the edges of the isolation region, and also prevents leakage current from occurring in the switching transistor due to seepage of the high-concentration impurity layer for device isolation from the edge of the isolation region. This makes it possible to prevent fluctuations in threshold voltage.

[Embodiment] Hereinafter, an embodiment of a MOS type dynamic RAM and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS. 1 and 2.

Figures 1(a) and 1(b) show M to which this embodiment is applied.
These are a planar pattern diagram showing the memory cell structure of the OS type dynamic RAM and an enlarged cross-sectional view of the main parts, and FIGS. FIG. 3 is a cross-sectional view of a memory cell shown in the order of steps.

In each of the embodiments shown in FIGS. 1 and 2, the same reference numerals as in the conventional structure shown in FIG. 3 represent the same or corresponding parts.

That is, in the memory cell structure of the MOS type dynamic RAM in this embodiment shown in FIGS. 1(a) and (b), reference numeral 10 is on the silicon semiconductor substrate 20,
A plurality of memory cells are arranged in a houndstooth pattern on a plane, and reference numeral 11 denotes a plurality of memory cells arranged in a planar pattern in the form of a houndstooth checkerboard. It shows the groove.

3 is an isolation region formed at the bottom of the trench 11 consisting of two upper and lower stages to electrically isolate each memory cell 10 from each other, and the part indicated by a solid line in the center is an isolation region of these regions. This corresponds to the boundary between each cell, and as a separating means at the bottom of this groove, for example, the well-known LOC
A thick oxide film formed by the OS method, a high concentration impurity layer, or either one of these may be applied.

Reference numeral 2 denotes a capacitor region formed on the inner surface of the lower step of the groove 11 having the isolation region i between the memory cells 1O, and in this case, the capacitor region 2 is a Brehner type capacitor.

In other words, a plate film formed on the lower stage side of the groove 11 dug into the silicon substrate 20 via an insulated film;
The structure may be such that an impurity layer formed on the side surface of the substrate with an opposite conductivity type, and in this case, an impurity region 3c which also becomes one diffusion region of a switching Tr 3 to be described later, is used as an electrode. However, in addition to this, for example, a so-called stacked structure in which conductor layers and insulator layers are stacked alternately may also be used. Tr
It is formed in the region between the gate electrode 3a of No. 3 and does not appear on a plane.

Reference numeral 3 denotes a MOS type switching Tr formed on the inner surface of the −F step of the groove II in the isolation region 1, and this switching Tr 3 is formed in a ring shape on the inner surface of the upper step of the groove 11. word line 5. In this case, the gate voltage g3a connected to the WL line 5a or 5b
A diffusion region (source or drain) 3c connected to one electrode of the capacitor region 2 formed below the ring-shaped gate electrode 3a, and a diffusion region (source or drain) 3c of the substrate 20 inside the ring-shaped gate electrode fj3a. It is formed on the surface side and consists of a diffusion region (drain or source) 3b connected to the BL line 6a or 6b in the bit line 6° process.
．． The boundary line (minute 1114) of the isolation region l and the channel region of this switching Tr3, in other words, the direction of current flow in the current path between the source and drain are not parallel to each other. In other words, as shown in FIG. 1(a), the gate voltage g of this switching Tr3
3a is ring-shaped in each memory cell, the flow of electrons from the source to the drain is not parallel to the separation edge at all, thereby causing the separation region l
At the same time, the threshold voltage of the switching Tr 3 is reduced due to seepage of the high concentration impurity layer for element isolation from the edge of the isolation region l. Fluctuations are prevented.

Further, as shown in FIG. 1(a), 4 is a contact portion formed in the diffusion region 3b inside the ring-shaped gate electrode 3a in the switching Tr 3, and the contact portion 4 is used to connect the diffusion region 3b is connected to the bit line 6. Furthermore, although the gate electrode 3a of each switching Tr 3 is connected to the word line 5, the word line 5 may be formed by connecting adjacent gate electrodes 3a to each other. Alternatively, the word line 5 such as the A1 wiring layer may be connected to a part of the gate electrode 3a via a contact portion.

Furthermore, when arranging the navigation word 1i15 and the bit line 6, if this is a folded pit line system, the BL lines 6a and 6b are arranged alternately,
These BL lines 6a, 6b on one WL line 5a
When the contact portion 4 is provided, each of the BL lines 6a, 6
Since the two memory cells connected to line 5b will be selected at the same time, it is necessary to shift one of them below the next WL line 5b.
As shown in a), the memory cells 10 are arranged in a staggered pattern. However,
The shape of each memory cell 10 arranged in a houndstooth pattern may be circular or square in plan, but as shown in FIG. 1(a), the edges are rounded. When setting a planar hexagonal shape, it can be said to be an ideal shape in that it makes effective use of the pattern area and does not have an acute-angled vertex.

Next, a method of manufacturing a MOS type dynamic RAM according to this embodiment, which is shown in the order of steps in FIGS. 2(a) to 2(f), will be described.

First, the surface portion of the silicon semiconductor substrate 20 is covered with a silicon oxide film 21, and this is patterned to open as desired.
1 as a mask, reactive ion etching (RIE)
Therefore, in this method, a wide groove is formed by selectively digging the first groove portion 11a, which is the upper part of the groove 11 (FIG. 2(a)).

Then, the entire surface including the first groove portion 11a is again etched.
It is covered with a silicon oxide film 21 and etched by RIE until the bottom of the first trench portion 11a is partially exposed. That is, as a result of this etching, oxide film residues 22 are left on the side walls of the first trench portions 11a, forming side walls. Then, using this residue 22 as a mask, the bottom surface of the first groove portion 11a is similarly treated with RI.
By selectively etching with E, a narrow groove, here the second groove portion 1 which is the lower part of the groove 11, is formed.
1b is formed by digging (Fig. 2(b)).

After that, a silicon nitride film 23. Then,
The first silicon oxide film is sequentially formed and then etched by RIE. A sidewall is formed leaving a residue 24 of the silicon oxide film only on the sidewalls of each of the second groove portions 11a and Ilb. continue,
Using this residue 24 as a mask, the portion of the silicon nitride film 23 at the bottom of the second groove portion 11b is similarly selectively etched away by RIE (FIG. 2(C)).

Further, an impurity layer 25. of the same conductivity type as the substrate 20 is provided at the bottom of the second groove portion 11b. Thick silicon oxide films 26 are sequentially formed. These impurity layer 25 and silicon oxide film 26 correspond to the isolation region 1 in the trench. Thereafter, while leaving the original oxide film residue 22 described above, the remaining silicon oxide film 24. and the silicon nitride film 23 is removed to expose the side wall portion of the second groove portion 11b, and then,
This exposed sidewall portion is doped with an impurity having a conductivity type opposite to that of the silicon substrate 20 to form a diffusion region (source or drain) 3c of the switching Tr3 (FIG. 2(d)).

Further, a second groove portion 11b is formed on the surface of the diffusion region 3c by using polycrystalline silicon or silicon via a thin insulating film 2a.
Now, the capacitor region 2 is filled with polycrystalline silicon that will become one electrode 2b. That is, one electrode 2b is opposed to the diffusion region 3C, which is the other electrode, with the thin insulating film 2a interposed therebetween, thereby forming the capacitor region 2 (FIG. 2(e)).

Finally, the silicon oxide film 21 serving as the mask.
After removing the residue 22, the switching Tr
To control the threshold at 3, its channel region 3
d, and at the same time, a ring-shaped gate electrode 3a is formed on the side wall of the first groove portion 11a or from the side wall to the surface of the substrate 20 via a gate oxide film 3e made of a silicon oxide film. and the diffusion region (drain).

or source) 3b (Fig. 2(d)),
Furthermore, as shown in FIG. 1(b), the contact portion 4. and word line 5. The bit line 6 is formed and the entire structure is covered with a protective film 27 to complete the process.

As described above, according to this embodiment, a plurality of memory cells IO are arranged in a staggered pattern on the silicon semiconductor substrate 20, and the periphery of each memory cell IO is arranged in a staggered pattern. Two upper and lower grooves 11 are formed at the end, a capacitor region 2 is provided in the lower part of the groove 11, and a switching transistor 3 in which the gate electrode i3a is formed into a ring shape is provided in the upper part of the open groove 11.
In addition, since the isolation region l was formed at the bottom of the trench so as to surround the capacitor region 2, each of the plurality of memory cells 10
The pattern is arranged in a houndstooth pattern, and the upper and lower two rows of full 11
Switching transistor compatible with 3. By arranging and forming the capacitor region 2, it is possible to effectively utilize the cell area.

On the other hand, unlike the conventional configuration, in this embodiment, the capacitor region 2.
Since the boundary line of the isolation region l and the current flow in the channel region 3d of the switching transistor 3 are no longer parallel, it is possible to reliably prevent the generation of leakage current along the edge of the isolation region l, and at the same time, this isolation The seepage of the high-concentration impurity layer for element isolation from the end of the region 1 is no longer caused, and as a result, fluctuations in the threshold voltage of the switching transistor 3 can also be prevented.

Furthermore, in this embodiment, in the above-described separate and merged memory cell structure, the capacitor portion 2 and the switching transistor portion 3 of each cell IO are formed vertically in one trench 11. This is extremely effective for cell structures that are being miniaturized, since it is possible to secure as large a capacitor capacity as possible.

Furthermore, the configuration of such an embodiment is not limited to a one-transistor, one-capacitor type MOS dynamic RAM, but also a static RAM in which a high-resistance wiring, a transistor, a capacitor, etc. are built into each memory cell. For devices that require a combination of two or more types of single elements, such as applications for resistors and capacitors in RAM, etc., it is necessary to It goes without saying that it can be easily adopted by manufacturing, and as a result, it is possible to achieve high density in this type of device configuration relatively easily.

〔Effect of the invention〕

As detailed above, according to the present invention, a plurality of memory cells are arranged in a 5% grid pattern, and two grooves are formed in the upper and lower grooves at the peripheral edge of each memory cell. and a capacitor area at the bottom of the groove.

Each of the switching transistors with a ring-shaped gate electrode is provided at the top of the trench, and an isolation region is provided at the bottom of the trench to surround the capacitor region. The pattern arrangement and the arrangement of the switching transistor and capacitor region corresponding to the upper and lower grooves make it possible to effectively utilize the cell area and effectively achieve higher device density. In addition, with this configuration, the boundaries between the capacitor region and the isolation region are no longer parallel to the current flow in the channel region of the switching transistor, so the generation of leakage current along the edges of the isolation region can be suppressed. It is also possible to prevent fluctuations in the threshold voltage of the switching transistor due to seepage of the high concentration impurity layer for element isolation from the ends of the isolation region, and to obtain stable MOS transistor characteristics. The houndstooth pattern arrangement of each memory cell makes it possible to easily adapt this configuration to a MOS type dynamic RAM using a folded bit line method, and also allows each memory cell to have rounded edges. When setting a planar hexagonal shape, not only can the pattern area be used effectively, but it also has excellent features such as being able to effectively suppress leakage phenomena between cells due to electric field concentration at the cell edges. It is.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view showing a memory cell structure of a MOS type dynamic RAM to which an embodiment of the present invention is applied, and FIG. 2(a) is a cross-sectional view. to f) are respective cross-sectional views of memory cells showing the manufacturing method of the above MOS type dynamic RAM in the order of steps, and Fig. 3 is an explanation showing the planar pattern of the memory cell in the above MO8 type dynamic RAM according to the conventional example. It is a diagram. 10...Memory cell, 11...Two upper and lower grooves dug into the peripheral edge of the memory cell, lla, llb...
...First groove part in the upper part of the groove, second groove part in the lower part, 2
0...Silicon semiconductor substrate. 1... Separation region, 2... Capacitor region, 2a
-... Thin film in the same capacitor area, 1j film, 2b...
...One electrode of the same capacitor region, 3... Switching transistor, 3a... Ring-shaped gate electrode of the same transistor, 3b... Diffusion region that becomes the source or drain of the same transistor, 3C... ...Diffusion region that becomes the drain or source of the same transistor (
3d... Channel region of the same transistor, 3e... Gate oxide film of the same transistor, 4... Contact portion, 5 and 5a, 5b... Word Lines, 6 and 6a, 6b...
...Bit line. Agent: Masuo Oiwa, Figure 1, Figure 1 (b) 6 Ayo Muro a, 6b; Pinto Ko, Figure 2, Figure 3, voluntarily written amendments to the procedures) Showa 64 Nigeto 27゛Dear Director-General of the Juryaku Agency 1 , Incident Display Patent Application No. 112943/1983 2,
Name of the invention MO8 type dynamic RAM$- and its manufacturing method 3,
Person making the amendment 5, Subject of amendment (1) Claims column 6 of the specification, Contents of amendment (1) The claims of the specification shall be amended as a separate sheet. (2) On page 14, line 13 of the specification, after "obtaining." [On the other hand, in the case of the so-called open pit line method, it is not necessary to arrange the memory cells in a staggered pattern as described above, and therefore the shape of each memory cell is The square shape has the highest density arrangement. ”
join. (3) Figure 1 (,), Figure 2 (d), (,) of the drawings
and (f) are revised with the attached sheet. Claims (1) 1) In a MO8fi dynamic RAM of a transistor and one capacitor type, a plurality of memory cells arranged in a staggered pattern on a semiconductor substrate, and a peripheral edge surrounding each memory cell. There are two grooves formed in the upper and lower parts,
A capacitor region provided in the lower part of the groove, a ring-shaped gate electrode formed in the upper part of the groove, one diffusion layer that becomes a source or drain connected to the capacitor region, and the gate electrode. a switching transistor formed on the inner substrate surface and having the other diffusion layer serving as a drain or source connected to the data line via a contact; and a switching transistor provided at the bottom of the trench so as to surround the capacitor region. (2) A plurality of memory cells arranged in a staggered pattern on a semiconductor substrate are arranged in a ridge corner. MO8 according to claim 1, characterized in that the MO8 is set in a planar hexagonal shape with a rounded shape.
Type Dynamic RAM0 (3) A 1-transistor, 1-capacitor type MO8 type dynamic RAM in which a plurality of memory cell parts are arranged in a staggered pattern on the semiconductor substrate surface, and the peripheral area surrounding the memory cells on each side is a step of forming a groove with two upper and lower stages in the end portion consisting of a first groove portion serving as an upper step portion of the groove and a second groove portion serving as a lower step portion of the groove; and a step of forming a groove bottom portion of the second groove portion. forming an isolation region on the exposed sidewall of the second groove portion; forming one diffusion region that will become the source or drain of the transistor;
With a thin insulating film interposed on the surface of one of the diffusion regions, the second groove portion is filled with polycrystalline silicon that will become one electrode of the capacitor region, and one of the diffusion regions will be filled with polycrystalline silicon that will become the other electrode of the same capacitor region. a step of opposing the diffusion region;
a step of forming a ring-shaped gate electrode via a gate oxide film on the side wall of the first groove portion or from the side wall to the surface of the substrate; and on the surface of the substrate inside the gate electrode; MO8 type dynamic RAM characterized in that it includes at least a step of forming the other diffusion region that becomes the drain or source of the transistor.
manufacturing method. Figure 1

Claims (3)

[Claims] (1) In a 1-transistor, 1-capacitor type MOS-type namic RAM, a plurality of memory cells are arranged in a staggered pattern on a semiconductor substrate, and a memory cell is formed at the peripheral edge surrounding each memory cell. A capacitor region provided in the lower part of the groove, a ring-shaped gate electrode formed in the upper part of the groove, and one of the capacitor regions connected to the capacitor region to serve as a source or a drain. a switching transistor having a diffusion layer and another diffusion layer formed on the substrate surface inside the gate electrode and serving as a drain or source connected to a data line via a contact; and a switching transistor having the capacitor at the bottom of the groove. What is claimed is: 1. A MOS type dynamic RAM comprising: an isolation region that surrounds a region and isolates adjacent memory cells from each other; (2) The MOS type dynamic RAM according to claim 1, wherein the plurality of memory cells arranged in a staggered pattern on the semiconductor substrate are set in a planar hexagonal shape with rounded edges. . (3) A one-transistor, one-capacitor type MOS type dynamic RAM in which a plurality of memory cell parts are arranged in a staggered pattern on the surface of a semiconductor substrate, in which a peripheral edge part surrounding each of the memory cells, forming two upper and lower grooves consisting of a first groove portion serving as an upper portion of the groove and a second groove portion serving as a lower portion of the groove; and forming a separation region at the bottom portion of the second groove portion. a step of forming one diffusion region that will become the source or drain of the transistor on the exposed sidewall portion of the second groove portion;
With a thin insulating film interposed on the surface of one of the diffusion regions, the second groove portion is filled with polycrystalline silicon that will become one electrode of the capacitor region, and one of the diffusion regions will be filled with polycrystalline silicon that will become the other electrode of the same capacitor region. a step of opposing the diffusion region;
a step of forming a ring-shaped gate electrode via a gate oxide film on the side wall of the first groove portion or from the side wall to the surface of the substrate; and on the surface of the substrate inside the gate electrode; A MOS type dynamic RAM characterized in that it includes at least a step of forming another diffusion region that becomes a drain or a source of a transistor.
manufacturing method.