JP2629818B2 - MOS dynamic RAM and method of manufacturing the same - Google Patents

Description

The present invention relates to a MOS dynamic RAM having a plurality of memory cells, and more particularly to a MOS dynamic RAM having a plurality of memory cells arranged in a staggered pattern. The present invention relates to a structure of a memory cell in a transistor and a one-capacitor type MOS dynamic RAM and a method of manufacturing the same.

[Conventional technology]

As a conventional MOS dynamic RAM having a plurality of memory cells of this kind, for example, in a MOS dynamic RAM based on a folded bit line method, as shown in FIG. 3, a data line, a so-called bit line ( In addition to transferring data to each memory cell via each contact portion 4 connected to a BL 6, a switching transistor (hereinafter Tr) connected to a word line (hereinafter also referred to as WL) 5. These data are stored in the capacitor region 2 of each memory cell by the on / off control of (3).

In the case of this configuration, in order to electrically insulate and separate these memory cells from each other, a generally thick insulating film, a deep groove, or a semiconductor substrate is used as the isolation region 1. And an impurity layer having a higher concentration than that of this is formed.

[Problems to be solved by the invention]

However, in the MOS dynamic RAM configured as described above, the potential is not applied to the switching Tr 3, that is, along the edge of the isolation region 1 even though the switching Tr 3 is off. As a result, a leak current as indicated by an arrow is liable to occur, which often causes inconvenience that data described in the capacitor region 2 of each memory cell leaks out. In contrast, the high-concentration impurity layer for element isolation is diffused,
Channel width becomes narrower and the set threshold voltage Vth
There was also a problem that it changed.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and has as its object to prevent generation of a leakage current along an end of an isolation region and to reduce the size of a switching transistor. This type of MOS dynamic RA is designed to prevent fluctuations in the threshold voltage to obtain stable MOS transistor characteristics and to efficiently form MOS transistors within a limited cell area.
M, and its manufacturing method.

[Means for solving the problem]

In order to achieve the above-mentioned object, a MOS according to the present invention is provided.
In the dynamic RAM, a plurality of memory cells set in a planar hexagon with a plurality of rounded corners are arranged in a zigzag pattern. And a switching transistor having a gate electrode formed in a ring shape is provided in a lower portion of the groove and a gate electrode is formed in an upper portion of the groove, respectively.
In addition, an isolation region is provided at the bottom of the groove so as to surround the capacitor region.

That is, the present invention provides a one-transistor, one-capacitor MOS dynamic RAM on a semiconductor substrate.
A plurality of memory cells which are set in a planar hexagon with rounded ridges and are arranged in a staggered pattern, and two upper and lower grooves formed at the peripheral end surrounding the individual memory cells; A capacitor region provided in a lower part of the groove, a ring-shaped gate electrode formed in an upper part of the groove, one of diffusion layers serving as a source or a drain connected to the capacitor region, and the gate A switching transistor formed on the substrate surface inside the electrode and having the other diffusion layer serving as a drain or a source connected to a data line via a contact, and a switching region surrounding the capacitor region at a groove bottom of the groove; And a separation region for separating adjacent memory cells from each other. A one-transistor, one-capacitor MOS dynamic RAM in which the memory cells are arranged in a staggered pattern, wherein a first groove serving as an upper step of the groove is provided at a peripheral end surrounding each of the memory cells. Forming a two-step upper and lower groove composed of a portion and a second groove part serving as a lower part of the groove, forming an isolation region at a groove bottom of the second groove part, and forming the second groove. Forming one diffusion region serving as a source or a drain of the transistor on the exposed side wall portion; and forming the second trench portion with a thin insulating film interposed on the surface of the one diffusion region. Is buried in polycrystalline silicon to be one electrode of the capacitor region and is opposed to one diffusion region also to be the other electrode of the capacitor region; Surface Forming a ring-shaped gate electrode on the channel region of the transistor through a gate oxide film from the side wall portion of the first groove portion or from the side wall portion to the surface portion of the substrate; On the surface of the substrate inside,
Forming a second diffusion region serving as a drain or a source of the transistor.

[Action]

Therefore, in the present invention, a plurality of memory cells are arranged in a staggered pattern with each other, two upper and lower grooves are formed at the peripheral end of each of the memory cells, and Since the capacitor region is formed by providing a switching transistor having a ring-shaped gate electrode at the upper part of the groove and providing an isolation region at the bottom of the groove so as to surround the capacitor region, the two upper and lower grooves are formed. The boundary between the capacitor region and the isolation region, the current flow in the channel region of the switching transistor, and the effective cell area accompanying the arrangement of the switching transistor and the capacitor region corresponding to Are no longer parallel to each other, which can prevent the generation of a leak current along the edge of the isolation region. It is as it can prevent the fluctuation of the threshold voltage of the switching transistor according to exudation of the high concentration impurity layer use.

〔Example〕

Hereinafter, an embodiment of a MOS type dynamic RAM according to the present invention and a method of manufacturing the same will be described in detail with reference to FIG. 1 and FIG.

FIGS. 1 (a) and (b) apply this embodiment.
FIGS. 2A and 2F are a plan view showing a MOS dynamic RAM memory cell structure and an enlarged sectional view of a main part. FIGS. 2A to 2F show a method of manufacturing a MOS dynamic RAM according to this embodiment. It is sectional drawing of each memory cell shown in order.

In these embodiments shown in FIGS. 1 and 2, the same reference numerals as those in the prior art shown in FIG. 3 represent the same or corresponding parts.

That is, in the memory cell structure of the MOS dynamic RAM according to this embodiment shown in FIGS. 1 (a) and 1 (b), reference numeral 10 is arranged on a silicon semiconductor substrate 20 and arranged in a staggered plane pattern. Each of the plurality of memory cells,
Reference numeral 11 denotes a two-level groove dug at the peripheral end of each of the memory cells 10 so as to individually surround the memory cells.

Reference numeral 1 denotes an isolation region formed at the bottom of the two-stage groove 11 for electrically isolating the memory cells 10 from each other. It corresponds to the boundary between the cells, and as a separating means at the bottom of the groove, for example, a thick oxide film or a high-concentration impurity layer by a known LOCOS method or any one of these may be applied. .

Reference numeral 2 denotes a capacitor region formed on the inner surface of the lower portion of the groove 11 having the isolation region 1 between the memory cells 10. The capacitor region 2 is a planar capacitor, That is, the silicon substrate 20
A plate film formed on the lower side of the groove 11 formed through an insulating film and an impurity layer formed on the side surface of the substrate in a reverse conductivity type.
The structure may be such that the impurity region 3c, which is also one of the three diffusion regions, is used as an electrode. However, in addition to the above, for example, a structure called a stacked type in which conductor layers and insulator layers are alternately stacked may be adopted. In any case, the capacitor region 2 is switched with the isolation region 1 which is vertically stacked. It is formed in a region between Tr3 and gate electrode 3a, and does not appear on a plane.

Reference numeral 3 denotes a MOS switching transistor formed on the inner surface of the upper portion of the groove 11 in the isolation region 1. The switching Tr 3 is formed in a ring shape on the inner surface of the upper portion of the groove 11. In the word line 5, the gate electrode 3a connected to the WL line 5a or 5b and the diffusion connected to one electrode of the capacitor region 2 formed below the ring-shaped gate electrode 3a. Region (source or drain) 3c and substrate 20 inside ring-shaped gate electrode 3a
The bit line 6 is formed on the surface side of the
Or a diffusion region (drain or source) 3b connected to the switching transistor 6b. In this case, the boundary line (separation end) between the capacitor region 2 and the isolation region 1 and the channel region of the switching Tr3 In other words, the direction of the current flow in the current path between the source and the drain is not parallel. That is, as shown in FIG. 1 (a), the gate electrode 3 of this switching Tr3
Since a is in a ring shape in the individual memory cells, the flow of electrons from the source to the drain is not completely parallel to the separation end, and thus the end of the separation region 1 In addition to preventing the generation of a leak current along the portion, the fluctuation of the threshold voltage of the switching Tr3 due to the seepage of the high-concentration impurity layer for element isolation from the end of the isolation region 1 is also reduced. Is prevented.

Further, as shown in FIG. 1 (a), reference numeral 4 denotes a contact portion formed in the diffusion region 3b inside the ring-shaped gate electrode 3a in the switching Tr3. 3b is connected to the bit line 6. Further, the gate electrode 3a of each switching Tr3 is:
Although connected to the word line 5, the word line 5 may be formed by connecting adjacent gate electrodes 3a to each other, or the word line 5 such as an Al wiring layer may be connected. Gate electrode 3a via contact
May be connected.

When the word lines 5 and the bit lines 6 are arranged in a folded bit line system, the BL lines 6a and 6b are alternately arranged, and one WL
If the contact portions 4 for these BL lines 6a and 6b are provided on the line 5a, two memory cells connected to the respective BL lines 6a and 6b will be simultaneously selected. It is necessary to displace each memory cell 10 below the next WL line 5b. In this case, as shown in FIG. -ing The shape of each of the memory cells 10 arranged in a staggered lattice shape as described above may be a planar circular shape or a rectangular shape. However, as shown in FIG. When a flat hexagonal shape is set, the pattern area can be effectively used, and it can be said that it is one ideal shape in that it has no acute-angled vertex ridge. On the other hand, in the case of the so-called oven bit line method, it is not necessary to arrange the memory cells in a staggered pattern as described above. Therefore, the shape of each memory cell is the highest density arrangement.

Next, a method of manufacturing the MOS type dynamic RAM according to this embodiment shown in FIGS. 2A and 2F in the order of steps will be described.

First, the surface of the silicon semiconductor substrate 20 is covered with a silicon oxide film 21 and these are patterned and opened as expected.
Is formed as a mask by reactive ion etching (RIE) to selectively dig a first groove portion 11a to be an upper step portion of the wide groove, ie, the upper portion of the groove 11 (FIG. 2 ( a)).

Next, the entire surface including the first groove portion 11a is again
The silicon oxide film 21 is covered and etched by RIE until the bottom surface of the first groove portion 11a is partially exposed. That is, the first groove portion is formed by this etching.
An oxide film residue 22 is left on the side wall 11a to form a sidewall. Using the residue 22 as a mask, the bottom surface of the first groove portion 11a is selectively etched by RIE in the same manner, so that a narrow groove is formed.
A second groove portion 11b serving as a lower portion of 11 is dug and formed (FIG. 2 (b)).

Thereafter, a silicon nitride film 23 is formed on these entire surfaces, and then
After a silicon oxide film is sequentially formed, the first and second groove portions 11 are etched by RIE.
Sidewalls are formed only on the side walls of a and 11b except for the residue 24 of the silicon oxide film. Subsequently, using the residue 24 as a mask, the portion of the silicon nitride film 23 at the bottom of the second groove portion 11b is similarly selectively etched away by RIE (FIG. 2 (c)).

Further, an impurity layer 25 of the same conductivity type as the substrate 20 and a thick silicon oxide film 26 are sequentially formed at the bottom of the second groove portion 11b. These impurity layers 25 and silicon oxide film 26
This corresponds to the separation region 1 here. After that, the silicon oxide film residue is left until the original oxide film residue 22 is left.
24 and the silicon nitride film 23 are removed, and the second trench portion 1 is removed.
Then, the side wall of the switching transistor 3b is exposed by doping the exposed side wall with an impurity having a conductivity type opposite to that of the silicon substrate 20, thereby forming a diffusion region (source or drain) 3c of the switching Tr3 (see FIG. FIG. 2 (d).

Further, the second groove portion 11b is buried in the surface of the diffusion region 3c through a thin insulating film 2a with polycrystalline silicon. In this case, the second groove portion 11b is buried with the polycrystalline silicon serving as one electrode 2b of the capacitor region 2. That is, the one electrode 2b is opposed to the diffusion region 3c to be the other electrode by the interposition of the thin insulating film 2a to form the capacitor region 2 (FIG. 2 (e)).

Finally, the silicon oxide film 21 serving as the mask,
In order to control the threshold value in the switching Tr3 after removing the residue 22 and doping the channel region 3d with an impurity, a ring-shaped gate is formed through a gate oxide film 3e of a silicon oxide film. The electrode 3a is connected to the side wall of the first groove portion 11a or the substrate 2 from the side wall.
0 and formed on the diffusion region (drain,
Alternatively, a source) 3b is formed (FIG. 2D), and further, as shown in FIG.
4 and the word line 5 and the bit line 6 are formed, and the whole is covered with the protective film 27, thus completing the process.

As described above, according to this embodiment, the plurality of memory cells 10 are arranged on the silicon semiconductor substrate 20 in a staggered pattern, and the peripheral ends of these memory cells 10 are arranged. The upper and lower two-stage groove 11 is formed in the portion, and the capacitor region 2 is
A switching transistor 3 having a ring shape of a gate electrode 3a is provided in each upper part of the transistor 11, and an isolation region 1 is formed so as to surround the capacitor region 2 at the bottom of the groove. The cell area can be effectively utilized by the pattern arrangement of ten staggered lattices and the arrangement and formation of the switching transistors 3 and the capacitor regions 2 corresponding to the upper and lower grooves 11.

On the other hand, unlike the conventional configuration, in this embodiment, the capacitor region 2,
In addition, since the boundary between the isolation region 1 and the current flow in the channel region 3d of the switching transistor 3 are not parallel, generation of a leak current along the end of the isolation region 1 can be reliably prevented. This separation area 1
And the threshold voltage of the switching transistor 3 can be prevented from fluctuating as a result.

Further, in this embodiment, in the above-described separation / merging type memory cell configuration, the capacitor portion 2 and the switching transistor portion 3 of each cell 10 are formed vertically in one groove 11. For a cell structure to be miniaturized, it is possible to secure as much capacitor capacity as possible, which is extremely effective.

The configuration in such an embodiment is not limited to a one-transistor, one-capacitor type MOS dynamic RAM.
For example, a static type in which high-resistance wiring and transistors and capacitors are built in individual memory cells
For devices that require a combination of two or more single elements, such as applications to resistors and capacitors in RAM, etc., each of these single elements must be formed in the vertical direction of the trench to be dug. Of course, it is possible to easily adopt the device by incorporating it, and thereby, it is possible to relatively easily achieve high density in this type of device configuration.

〔The invention's effect〕

As described in detail above, according to the present invention, a plurality of memory cells set in a planar hexagon with rounded corners are arranged in a staggered pattern, and the peripheral ends of these memory cells are The upper part of the groove is provided with a capacitor region, the upper part of the groove is provided with a ring-shaped switching transistor having a gate electrode, and the bottom part of the groove surrounds the capacitor region. Since the isolation region is provided as described above, the cell area can be reduced by the pattern arrangement of the plurality of memory cells in a staggered lattice pattern and the arrangement of the switching transistor and the capacitor area corresponding to the two upper and lower grooves. It is possible to achieve effective utilization and achieve high density of the device effectively, and with this configuration, the boundary between the capacitor region and the isolation region and the switching device Since the current flow in the transistor channel region is no longer parallel, the generation of leakage current along the edge of the isolation region can be prevented well, and high-concentration impurities for element isolation from the edge of the isolation region. Variations in the threshold voltage of the switching transistor due to exudation of the layer can be prevented, stable MOS transistor characteristics can be obtained, and this configuration can be folded down by the staggered pattern arrangement of each memory cell. It is possible to easily adapt to MOS dynamic RAM of the bit line type, and when each memory cell is set to a hexagonal shape with rounded corners, the pattern area can be effectively used. In addition, it has an excellent feature that a leak phenomenon between cells due to electric field concentration at a cell edge can be effectively suppressed.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view showing a memory cell structure of a MOS type dynamic RAM to which an embodiment of the present invention is applied, and FIGS. FIG. 3 is a sectional view of a memory cell showing a method of manufacturing the same MOS dynamic RAM in the order of steps, and FIG. 3 is an explanatory view showing a plane pattern of the memory cell in the same conventional MOS dynamic RAM. 10: memory cell, 11: upper and lower grooves dug in the peripheral end of the emory cell, 11a, 11b: upper groove first groove portion, lower groove second groove portion, 20 ... ... Silicon semiconductor substrate. DESCRIPTION OF SYMBOLS 1 ... Separation area, 2 ... Capacitor area, 2a ... Thin insulating film of the same capacitor area, 2b ... One electrode of the same capacitor area, 3 ... Switching transistor, 3a ... Ring gate electrode of the same transistor , 3b... Diffusion region serving as source or drain of the transistor, 3c.
A diffusion region (the other electrode of the capacitor region) serving as a drain or a source of the transistor; 3d, a channel region of the transistor; 3e, a gate oxide film of the transistor; 5b: word line, 6 and 6a, 6b: bit line.

Claims (2)

(57) [Claims] In a one-transistor, one-capacitor type MOS dynamic RAM, a plurality of memory cells are set on a semiconductor substrate to have a hexagonal shape with rounded corners and are arranged in a staggered pattern. An upper and lower groove formed at the peripheral end surrounding each memory cell, a capacitor region provided at a lower part of the groove, and a ring-shaped gate formed at an upper part of the groove An electrode, one diffusion layer serving as a source or a drain connected to the capacitor region, and another formed on the substrate surface inside the gate electrode and connected to a data line via a contact, or the other serving as a source A switching transistor having a diffusion layer, and a separation region provided at a groove bottom of the groove so as to surround the capacitor region to separate adjacent memory cells from each other. Characterized by comprising a preparative
MOS type dynamic RAM. 2. A one-transistor, one-capacitor MOS type in which a plurality of memory cell parts are arranged in a staggered pattern on a semiconductor substrate surface, and the memory cells are set in a hexagonal shape with rounded corners. A dynamic RAM, comprising two upper and lower grooves formed at a peripheral end surrounding the individual memory cells, the first groove being an upper part of the groove and the second groove being a lower part of the groove. Forming a separation region at the bottom of the second groove portion, and forming a source and a transistor of the transistor on the exposed side wall portion of the second groove portion.
Alternatively, a step of forming one diffusion region serving as a drain, and, in a state where a thin insulating film is interposed on the surface of the one diffusion region, the second groove portion is formed of polycrystalline silicon serving as one electrode of a capacitor region. Embedding and opposing one diffusion region which also serves as the other electrode of the capacitor region; and forming a gate on the side wall of the first groove portion or on the channel region of the transistor extending from the side wall to the surface of the substrate. Forming a ring-shaped gate electrode through the oxide film from the side wall of the first groove or from the side wall to the surface of the substrate; and forming a transistor on the surface of the substrate inside the gate electrode. Forming a second diffusion region serving as a drain or a source of the MOS type dynamic RAM.