JPH01310536A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a bipolar transistor element at low resistance to be formed without forming an epitaxial film, etc., by a method wherein an NPN type or PNP type transistors are simultaneously formed in a one conductivity type semiconductor region by an ion implantation process. CONSTITUTION:A P-type silicon substrate 1 is implanted with phosphorous ion as an N-type impurity to form an N-type semiconductor region 2. Next, after coating the surface with a resist 3 as a mask for implanting ion, the N-type semiconductor region 2 is irradiated with boron ion as a P-type impurity to form an NPN type transistor region assuming the part near the mean path length of the boron ion as a P-type inversion layer. After forming such an NPN type transistor region on the surface layer part, a high concentration P-type impurity doped part 17 for connecting a base and for isolating a base part as well as high concentration N-type impurity doped parts 18, 19 for connecting an emitter and a collector are formed to form an NPN type bipolar transistor. Through these procedures, the bipolar transistor of low resistance can be manufactured at high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a bipolar junction.

(b) Conventional technology A monolithic bipolar transistor can be obtained by forming a PNP or NPN semiconductor region in a semiconductor substrate using various methods, or conventionally, in order to lower the well resistance, impurities are first introduced into the semiconductor substrate. A highly doped semiconductor region of one conductivity type is formed by ion implantation or the like, and then a low concentration semiconductor layer of one conductivity type is formed thereon by epitaxial and thermal diffusion of impurities. P-type impurities and N-type impurities are implanted in a predetermined order by ion implantation into PNP or NP.
A method of forming an N semiconductor junction is widely used.

An example of a typical manufacturing process for a bipolar transistor element by this method is shown in sequence in FIGS. 2(a) to 2(h).

Figure 2 (a) is a P-type silicon semiconductor substrate! N heavily doped by ion implantation using resist 3
The process of forming a type semiconductor region 2 (so-called buried layer) is shown. FIG. 2(b) shows a step of forming a P-type semiconductor film 4 by covering it with Ebitaki Soyal. FIG. 2(c) shows a step of doping an N-type impurity into the P-type semiconductor film 4 by ion implantation to form an N-type epitaxial film 5. FIG. 2(d) shows the element isolation step by forming the insulating layer 6. FIG. 2(e) shows an N-type epitaxial film 5.
FIG. 2F shows a step of forming a P-type head region 7 by ion implantation, and FIG. 2(f) similarly shows a step of forming a heavily doped N-type impurity region 8 for collector connection. Figure 2 (g) is
A process of forming a heavily doped P-type impurity region 9 for base connection in the P-type head region 7 is shown. And, FIG. 2(h) shows P
The figure shows a state in which after forming a high concentration N-type region 10 for an emitter in the mold head region 7, a base wiring 911, an emitter wiring 12, and a collector wiring 13 are connected to each other.

(c) Problems to be Solved by the Invention However, in the above-mentioned conventional method for manufacturing bipolar transistors, the manufacturing process is complicated because an epitaxial film of 4°5 is used, and the yield rate is reduced due to defects that may occur in the epitaxial film. There was an inconvenience in that it was easy to decrease. Furthermore, the formation of such an epitaxial film is costly and, moreover, the process involves forming a buried layer, so that it is not always satisfactory from an economic point of view.

This invention was made in view of such circumstances, and in particular, without forming an epitaxial film as described above,
The present invention aims to provide a manufacturing method that can efficiently obtain low-resistance bipolar transistors.

(d) Means for Solving the Problems From the above viewpoint, the present inventors conducted intensive research and found that ion implantation, which is used to create a so-called retrograde well, is performed in a single conductivity type semiconductor region doped with a high concentration of impurities. By applying the method and implanting impurity ions of the opposite conductivity type, P is automatically added to the surface layer of the semiconductor region of one conductivity type.
It was discovered that an NP type or NPN type transistor region is formed, and the present invention was achieved.

Thus, according to the present invention, the above-mentioned PN in one conductivity type semiconductor region
A method of manufacturing a semiconductor device is provided, the method comprising forming a P-type or N P N-type transistor region.

The semiconductor region of one conductivity type in the present invention can be formed, for example, by doping a silicon semiconductor substrate with a predetermined P-type or N-type impurity at a high concentration, and can be formed by a normal ion implantation method in terms of concentration control. Preferably, doping is performed. At this time, the concentration is N in the P-type silicon substrate.
When implanting a type impurity (for example, phosphorus), the concentration in the N-type semiconductor region after annealing is 1×107 to lXl0'.
It is suitable to control the amount of particles/cm3.

Impurity ions of opposite conductivity type are irradiated and implanted into the semiconductor tilted wall by an ion implantation method. For example, for an N-type semiconductor region, P-type impurity ions such as boron, aluminum, gallium, etc., and for a P-type semiconductor region, N-type impurity ions such as phosphorus, arsenic, etc.
Type impurity ions are implanted. The energy of the implanted ions at this time is not particularly limited or is usually 5
0 KeV to several hundred KeV. is suitable, 50K
It is preferable to set it to ev-100KeV.

By such ion irradiation, a new tj P N P type or NPN type is usually formed near the ion irradiated surface of the semiconductor region, especially in the surface layer, around the average landing position of the ions.
A type transistor region is formed.

However, by increasing the energy of ion implantation, such a transistor region can also be formed inside. Thereafter, a bipolar transistor element to be actually used is constructed by appropriately performing necessary connection parts, attachment of lead wires, annealing treatment, etc.

However, at this time, the annealing treatment
It is necessary to carry out the process at a temperature or for a processing time that does not destroy the structure of the type or NPN type transistor region.

(e) Effect: By irradiating N-type (or P-type) impurity ions, that is, opposite conductivity type impurity ions, there is a high concentration of impurity ions near the average range position in the surface layer of the highly doped one-conductivity type semiconductor region. Impurity ions of opposite conductivity type are implanted at a concentration of
Further, low concentration impurity ions of opposite conductivity type are implanted into the lower and upper sides around this average range position. As a result, the conductivity type of the average range position impurity is reversed to form an opposite conductivity type semiconductor region, and on the upper and lower sides of the
A portion of the impurity of one conductivity type in the base is neutralized to form a lightly doped semiconductor region of one conductivity type, and as a result, a new NPN or PNP transistor is formed in the heavily doped semiconductor region of one conductivity type. A region will be formed.

(f) Example Phosphorus ions (180 KeV) as N-type impurities were implanted into a p-type silicon semiconductor substrate l using an ion irradiation device, and annealing was performed at 1150'C for 3 hours.
As shown in Figure (a), phosphorus ions are in high concentration (2X 1
N-type semiconductor region 2 doped with 0”/am3)
was formed.

Next, after applying a resist to the surface as a mask for ion implantation, the N-type semiconductor region 2 was irradiated with boron ions (70 KeV) as a P-type impurity, and then annealing was performed at 1050° C. for 2 hours. As a result, an NPN transistor region was formed in the vicinity of the irradiated surface of the N-type semiconductor region 2 in a self-aligned manner, with the P-type inversion layer located near the average range position of boron ions.

This state is shown in FIG. 1(b). In the figure, 3 is Renost, 15 is a P-type layer produced by inversion, and 14° and 16 are N, respectively.
This shows the mold layer.

Note that FIG. 3 shows the results of confirming by simulation the impurity concentrations of the NPN transistor regions formed in the surface layer by the boron ion implantation.

After forming the NPN type transistor region in the surface layer portion in this way, as shown in FIG. As shown in Figure (d), an NPN bipolar transistor was obtained by forming heavily doped N-type impurity regions 18 and 19 for emitter connection and collector connection. The transistor thus obtained exhibits transistor characteristics and has a high concentration of N.
Since the type impurity region was formed as a well, the resistance was low.

(g) Effects of the Invention According to the present invention, since an NPN or PNP transistor region is simultaneously formed in a semiconductor region of one conductivity type by ion implantation, a bipolar transistor element can be constructed extremely easily. In particular, since a low-resistance bipolar transistor element can be constructed without forming a conventional epitaxial film or the like, manufacturing efficiency, yield, etc. are excellent, and it is extremely advantageous in terms of economy.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are manufacturing process diagrams showing one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. 2(a) to (h)
) is a manufacturing process diagram illustrating a conventional method for manufacturing a bipolar transistor element, and FIG. 3 is a graph diagram showing by simulation the impurity concentration of an NPN transistor region formed by an embodiment of the manufacturing method of the present invention. be. 1... P-type silicon semiconductor substrate, 2...
N-type semiconductor region, 3...Resist, 14.16
...N-type layer, 15...P-type layer, 17...
・・・High concentration N-type impurity doped part, 18.19...
... Highly concentrated N-type impurity doped section. Figure 1 Figure 3 Figure 3? i;, Go (/Am) (b) (h) Procedural amendment dated August 7q, 1988 1, Case description 1988 Patent Application No. 141377 2, Title of invention Method for manufacturing semiconductor devices 3, hli Relationship with the case of the right person Patent applicant address Abe, Osaka City! 22-22 Nagaike-cho, IIF-ku Name (504) Nyab Co., Ltd. Representative Tsuji
Haruo 4, Agent 530 Address 1-3 Quarter, Nishitenma 5-chome, Kita-ku, Osaka
One Building G,? +li positive "Detailed description of the invention" column 7 of the subject specification, hli positive content amendment content 1, rlxlO' to 1xlO' on page 5, line 8 of the specification
pcs/c+a'J rlxlo" ~ lxl O" pcs/c
+n″J. ・2. Change “N-type impurity ion” in line 14 of the same page to rN.
type impurity ions,” he corrected.

Claims (1)

[Claims] 1. By irradiating and implanting N-type (or P-type) impurity ions into the one-conductivity type semiconductor region doped with P-type (or N-type) impurities at a high concentration using an ion implantation method, the above-mentioned one-conductivity type semiconductor region is 1. A method of manufacturing a semiconductor device, comprising forming a PNP type or NPN type transistor region within the semiconductor device.