JPH01307259A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate abnormal operation relating to a substrate potential, by providing a switching element having a highly doped source or drain electrode of a first conductivity type, substantially vertically to the substrate. CONSTITUTION:When a high voltage is applied to a gate electrode 14, a depletion layer 54 extending below the gate electrode can electrically isolate N<+>-type doped layers 15, 17 arranged on and under a transistor from each other. When a low voltage is applied to the gate electrode 14, the depletion layer 54 is made small and the N<+>-type doped layers 15, 17 on and under the transistor are electrically connected with each other. The transistor is of the type in which the carriers flow through the substrate 11 and operates completely independent of a potential of the P-type Si substrate 11. In this manner, stable operation of the memory can be obtained without causing any abnormal operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a vertical MIS transistor suitable for high integration.

[Conventional technology]

Conventionally, a semiconductor memory device in which a memory cell for dynamic RAM is formed in a semiconductor island region using a vertical MIS transistor and a capacitor is disclosed in Japanese Patent Application Laid-Open No. 60-7075.
8. It is described in JP-A-62-140456 and the like.

FIG. 2 is a partial cross-sectional view of the conventional memory cell. This memory cell is a vertical MOS consisting of a p-type Si island region 22, two n+ impurity layers 23 and 24, and a gate electrode 14.
The transistor and the n4'' impurity WJ23 on the lower surface of the island region 22 serve as a charge storage portion, and the insulating film (SiO
It has a one-transistor, one-capacitor structure consisting of a capacitor formed by a capacitor (□) and an electrode 16 thereon. Since the MOS capacitor and the MoS transistor are formed using the sidewalls of the island region in this way, the area occupied by the memory cell can be reduced and the capacitance of the capacitor can be maintained at a large value.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not give consideration to further reducing the number of memory cells. Regarding this, Figure 3 shows
The operating state of the memory cell shown in FIG. 2 will be shown and explained.

The substrate voltage of the transistor on the upper part of the island region of the memory cell is the p
It is supplied via the type impurity region. This is not a problem if the memory cell is large, but if the memory cell is shrunk, when positive (+) charges accumulate in the n+ impurity layer 23, which is the charge storage part, the depletion layer 31 extending from there causes There is a problem in that the substrate portion of the MOS transistor is insulated, and as a result, power is not supplied from the p''Si substrate 21 to the substrate portion (island region 22) of the MOS transistor, causing abnormal operation of the transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a vertical transistor without abnormal operation related to substrate voltage.

[Means to solve the problem]

The above object is to provide a semiconductor memory device which has a semiconductor pillar containing impurities of a first conductivity type on the surface of a semiconductor substrate, and in which at least a switching element and a capacitor are disposed on the semiconductor pillar.
This is achieved by a semiconductor memory device characterized in that the switching element has a highly doped source electrode or drain electrode of the first conductivity type and is provided substantially perpendicular to the substrate.

The above-mentioned semiconductor pillar also includes an island-like region surrounded by a groove provided in the semiconductor substrate and separated from the others.

In the present invention, the conductivity type of the semiconductor substrate and the conductivity type of the semiconductor pillar may be the same or different.

When both are of the same conductivity type, it is necessary to electrically insulate the semiconductor substrate and the semiconductor pillar by a method such as providing an insulating film between them. On the other hand, when the conductivity types of the two are different, it is not necessarily necessary to insulate the two, but it is preferable to insulate both in the same way as described above, since it is possible to prevent malfunctions caused by electrons generated by the incidence of alpha rays.

The semiconductor memory device of the present invention has a transistor formed in a semiconductor column containing an impurity of the same conductivity type as a high concentration impurity layer serving as a charge storage portion, and has a different operating principle from conventional devices.

[Effect]

A semiconductor memory device according to an embodiment of the present invention is shown in FIG. 5, and the present invention will be described in detail. In FIG. 5, 13 is an n-type impurity layer, 14 is a gate electrode, 15 is an n+ impurity layer, and 17 is an n-type impurity layer.
is an n+ impurity layer, and 54 is a depletion layer.

In this transistor, when a high voltage is applied to the gate electrode 14, the n+ impurity layers 15 and 17 disposed above and below the transistor can be electrically isolated by the depletion layer 54 extending below the gate electrode. On the other hand, when a low voltage is applied to the gate electrode 14, the depletion layer 54 becomes smaller and the 5
As shown in the figure, electrical conduction occurs between the n+ impurity layers above and below the transistor. This transistor is of a type in which carriers flow within the substrate. This transistor operates completely independent of the potential of the p-type Si substrate 11.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described in detail using FIGS. 1 and 4.

FIG. 1 shows an embodiment of the present invention, in which an n
+ impurity layer 17, gate electrode 14 and n+ impurity layer 15
This figure shows a memory cell for a dynamic RAM having a capacitance consisting of a vertical M/S transistor consisting of an n+ impurity layer 15 and an electrode 16 serving as a charge storage section.

FIG. 4 shows an embodiment of the manufacturing method of the embodiment shown in FIG. First, on the surface of the p-type Si substrate 11, for example, 3
An n-type impurity layer 13 having a depth of -.

It was formed using phosphorus ion implantation and diffusion technology (Fig. 4 (a)
)). After that, chemical vapor deposition (Chemical vapor deposition) is applied to the surface of the substrate.
cal Vapor Deposition: CV
Si, N4 layer 4 with a thickness of about 300 nm deposited by method D)
3 was processed using a photoresist pattern formed by photolithography as a mask, and further, using this photoresist pattern as a mask, the n-type impurity layer 42 was processed using an anisotropic dry etching technique.
An i-pillar is formed (Fig. 4(b)). Furthermore, Si and N4 are deposited by CVD method, processed by anisotropic dry etching,
Si, N4 with a thickness of 50 nm is formed on the column side wall of the n-type impurity layer 13.
Form layer 45. Thereafter, the Si substrate is further etched by approximately 2 mm by anisotropic dry etching (FIG. 4(C)).

Si and N4 were deposited again using the CVD method and processed using anisotropic dry etching to form a 50 nm thick layer of SL and N4 on the side walls of the Si pillars.
A layer 46 is formed (FIG. 4(d)). Using this Si3N4 layer 46 and Si, N4 layer 43 as an oxidation-resistant mask, Sj
The substrate surface is oxidized to form a Sio layer 47 approximately 200 nm thick.
(Fig. 4(e)).

After removing the Si, N4 layer 46 using, for example, hot phosphoric acid, an n+ impurity layer 15 is formed on the Si surface below the Si pillar by using a phosphorus diffusion method (FIG. 4(f)). This n+ impurity layer becomes a charge storage electrode of the capacitor. After oxidizing the surface of the n4'' impurity layer 15 to form an 8102 layer 49 with a thickness of 10 nm, n'' poly Si was buried by the CVD method to form a layer of about 2
By isotropically etching to a depth of 1M, an n"poly Si layer that will become the plate electrode 16 of the capacitor is formed (Fig. 4 (g)). Using the Si, N4 layer 43.45 as an oxidation-resistant mask, a Si pillar is formed. while protecting n”pol
The ySi surface is oxidized to form a 200 nm thick Si02 layer 50 (FIG. 4(h)). After removing the SL and N4 layers 45 using, for example, hot phosphoric acid, the side walls of the upper part of the Si pillars are oxidized to form an SiO2 layer for the gate oxide film of the vertical MQS transistor.
The layer 51 is formed to a thickness of 15 nm, and further
Si is deposited using the CVD method, and anisotropic dry etching is used to form an n ” p layer, which will become the gate electrode 14, on the side wall of the Si pillar.
An olySi layer is formed (FIG. 4(i)). The Si and N4 layers 43 on the surface of the Si pillars are removed using hot phosphoric acid and then oxidized to form a SiO2 layer 52 with a thickness of about 10 nm, and then arsenic is implanted by ion implantation to form the n+ impurity layer 1.
7 (Fig. 4 (j)). Finally, a Sio layer 12 is formed by the CVD method, a contact hole 53 is formed, and a data line wiring 18 is formed to form a semiconductor memory device equivalent to the first embodiment shown in FIG. It is possible (Fig. 4(k)).

FIG. 6 shows another embodiment of the invention. This example shows a structure in which a p+ impurity layer 61 is added to the structure of the embodiment shown in FIG. This p+ impurity layer 61 is provided to prevent leakage current from flowing between adjacent Si pillars. Of course, even if the p+ impurity layer covers the entire surface of the Si substrate at the bottom of the Si pillars, it will not cause any problem in operation.

From the viewpoint of barrier effect against electrons generated in the substrate due to the incidence of α-rays, p
It is preferable that four impurity layers be formed.

Another embodiment shown in FIG. 7 has a structure that can theoretically prevent malfunctions due to leakage between adjacent cells and electrons generated by the incidence of α rays. That is, the Si pillars are insulated from the p-type Si substrate 11 by the Si02 layer 71, eliminating the problems of inter-cell leakage and alpha rays.

FIG. 8 shows an embodiment of a structure capable of improving the cut-off characteristics of the vertical M/S transistor in the embodiment of FIG.

By forming a constriction 81 in the side wall of the upper part of the Si column, the surface area of the Si column viewed from above is locally narrowed. Therefore, even if the width of the depletion layer formed in the Si pillar by the electric field of the gate electrode 14 is thin, the transistor can be easily brought into the cut-off state.

In the embodiments of the present invention, an example of a memory cell having an n-type impurity has been described, but it goes without saying that the same effect can be achieved with a similar structure even for a memory cell of the opposite conductivity type having a p-type impurity. .

[Effects of the Invention] ″ According to the present invention, the storage electrode (
Positive charges are accumulated in the n "impurity layer), and due to this charge,
Even if all the Si pillars surrounded by the n+ impurity layer are depleted,
The characteristics of the transistor under the Si pillar are not affected. In other words, there is an effect of realizing stable memory operation regardless of the presence or absence of accumulated charge.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a conventional semiconductor memory device, FIG. 3 is an explanatory diagram explaining the operation of the conventional semiconductor memory device, and FIG. 4 is a process showing the manufacturing process of the semiconductor memory device shown in FIG. 1. 5 are explanatory diagrams for explaining the operation of the semiconductor memory device shown in FIG. 1, and FIGS. 6, 7, and 8 are sectional views of semiconductor memory devices according to other embodiments of the present invention, respectively. It is. 11...p-type Si substrate 12...insulating film 13.
...N-type impurity layer 14...Gate electrode 15.1
7...n+ impurity layer 16...electrode 18...wiring 21...p"si substrate 22...island region 23.24...n+ impurity layer 31...
・Depletion layer 43.45.46...Si, N
, layer 47.49.50.51.52...SiO□ layer 5
3... Contact hole 54... Depletion layer 61...
・P impurity layer 71...Sin, layer 81...
Constriction Agent Patent Attorney Junnosuke Nakamura Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 4 Fig. 4 Fig. 4 Fig. 4 Fig. 4 Fig. 4 Fig. 4 Fig. 1b m-ρd1chi4) Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A semiconductor memory device having a semiconductor pillar containing impurities of a first conductivity type on the surface of a semiconductor substrate, and in which at least a switching element and a capacitor are disposed on the semiconductor pillar, wherein the switching element has a high 1. A semiconductor memory device comprising a switching element having a source electrode or a drain electrode of a first conductivity type and provided substantially perpendicular to a substrate. 2. The semiconductor memory device according to claim 1, further comprising an insulating film between the semiconductor substrate and the semiconductor pillar, so that the two are electrically insulated. 3. The semiconductor pillar according to claim 1, wherein at least a part of the upper side wall of the semiconductor column has a recess, and a gate electrode is provided on the surface of the semiconductor pillar upper side wall including at least a part of the recess with an insulating film interposed therebetween. Semiconductor storage device. 4. The semiconductor memory device according to claim 1, wherein the switching element is an insulated gate field effect transistor.