JPH01304768A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent aging variation of a threshold voltage of an MISFET by providing a hydrogen ion absorption film which absorbs hydrogen ion emitted from a silicon oxide film between the MISFET and the silicon oxide film. CONSTITUTION:A memory cell of DRAM is provided with a hydrogen ion absorption film 17A at a formation region of p-channel MISFET Qp. The hydrogen ion absorption film 17A is provided to an upper part of an interlayer insulating film 8 to cover a channel formation region 3 and a source regions 10, 13 thereabout. The hydrogen ion absorption film 17A is formed by a material such as a polycrystalline silicon film or a combination film mainly composed thereof. Therefore, trapping of hydrogen ion into the channel formation region 3 or a silicon substrate thereabout can be reduced, resulting in reduction of aging variation of threshold voltage of p-channel MISFET Qp.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device.
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a resistance element formed of SFET or a silicon film.

[Conventional technology]

In a DRAM (dynamic random access memory) currently being developed by the present inventor, a memory cell is constituted by a series circuit of a MISFET for memory cell selection and a capacitive element for information storage. The memory cell selection MISFET is composed of an n-channel. The information storage capacitive element has a stacked capacitor structure and consists of 11 elements.

A plurality of the memory cells are arranged at intersections between word lines and complementary data lines, forming a memory cell array. The word line is formed of the same conductive film as the gate electrode of the memory cell selection MISFET, and is integrated therewith. The complementary data line is connected to one semiconductor region of the memory cell selection MISFET, and the complementary data line is connected to one semiconductor region of the memory cell selection MISFET.
It extends over the FET and the information storage capacitive element with interlayer insulation interposed therebetween. The complementary data line is formed of, for example, an aluminum alloy film.

A shunt word line extends above the complementary data line with an interlayer insulating film interposed therebetween.

This shunt word line is connected to the word line in the lower layer every predetermined number of memory cells, and reduces the apparent resistance value of the word line. The shunt word line is formed of, for example, an aluminum alloy film.

In this way, a DRAM with a shunt word line is
Since the memory cell selection time can be made faster, the information write operation speed and the information read operation speed can be made faster.

This type of DRAM uses MISFE for memory cell selection.
The shape of the step becomes large due to the information storage capacitive element having the T or stacked capacitor structure. Therefore, the surface of the interlayer insulating film that is the base of each of the complementary data line (first layer wiring) and the shunt word line (second layer wiring) needs to have improved step coverage, so it is smooth. has been made into

The glabellar insulating film, which is the base of the complementary data line, has not yet been formed with the aluminum alloy film, so it is mainly formed of a PSG film subjected to glass flow, which is a high-temperature process.

The interlayer insulating film that forms the base of the shunt word line is formed after the 5 aluminum alloy film (complementary data line) is formed.
Spin-on-glass (SOG), a low-temperature process
It is mainly formed of a silicon oxide film coated by a method.

Further, this type of DRAM is subjected to hydrogen annealing (H2 annealing) after forming the complementary data lines.

Hydrogen annealing is mainly performed to establish an ohmic connection between the complementary data line and one semiconductor region (single crystal silicon) of the memory cell selection MISFET. Hydrogen annealing is performed, for example, at 400 to 450 ['C] in a hydrogen gas atmosphere.
It is carried out for about 20 to 40 minutes at a temperature of .

Regarding this type of DRAM, for example, Nikkei McGraw-Hill, Separate Volume No. 011, Nikkei Micro Devices, 1
Published in May 1987, pages 165 to 174.

[Problem to be solved by the invention]

The inventor of the present invention found that the following problem occurred as a result of the above-mentioned DRAM characteristic defect test.

The DRAM is mainly formed of a silicon oxide film coated with an SOG method as an interlayer insulating film that serves as the base of the shunt word line. This silicon oxide film has fluidity that alleviates the step shape, so it contains a large amount of hydrogen-based ions such as H" and H2C. These hydrogen-based ions are formed in the silicon oxide film and silicon nitride film. The M I S
It is trapped in the crystalline silicon substrate at or near the channel forming region of the FET. This trapped hydrogen ion changes the threshold voltage of the MISFET.

The electrical reliability of DRAM decreases over time.

Furthermore, the DRAM has a peripheral circuit connected to a complementary MISFIE.
In particular, the inventors have confirmed that the amount of variation in the threshold voltage of the p-channel MISFET is larger than that of the n-channel MISFET. In other words, the electrical reliability of DRAM is
This is defined by the amount of variation in the threshold voltage of the FET.

Further, the DRAM is subjected to hydrogen annealing after forming complementary data lines. Since this hydrogen annealing is performed in a hydrogen gas atmosphere, as mentioned above, the penetration of hydrogen-based ions changes the threshold voltage of the P channel M r S F E T in particular, reducing the electrical reliability of the DRAM. do.

An object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor integrated circuit device over time.

Another object of the present invention is to provide a semiconductor integrated circuit device in which a store-open insulating film mainly composed of a silicon oxide film coated by the SOG method is formed on a semiconductor element, in which hydrogen-based ions of the silicon oxide film are applied to the semiconductor element. The object of the present invention is to provide a technique that can reduce the number of traps and achieve the above object.

Another object of the present invention is to reduce trapping of hydrogen-based ions from the hydrogen annealing in the semiconductor element in a semiconductor integrated circuit device in which hydrogen annealing is performed after forming a semiconductor element, thereby achieving the above object. Our goal is to provide the technology that is possible.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing methods required to achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a silicon oxide film coated on the top of a MISFET (or a resistance element) by the SOG method, between the MISFET and the silicon oxide film, the amount of energy emitted from the silicon oxide film is A hydrogen-based ion absorption membrane is provided to absorb hydrogen-based ions.

Further, in a semiconductor integrated circuit device in which hydrogen annealing is performed after forming a MISFET (or a resistance element), the hydrogen-based ion absorption film is provided over the MISFET when performing the hydrogen annealing.

[For production]

According to the above-mentioned means, it is possible to reduce trapping of hydrogen-based ions in the silicon saw plate (or in the resistance element) in or near the channel forming region of the MISFET, so that the aging of the MISFET can be reduced. It is possible to reduce fluctuations in the threshold voltage (or fluctuations in the amount of leakage current of the resistance element).

Hereinafter, the configuration of the present invention will be described together with embodiments in which the present invention is applied to each of DRAM and SRAM (static random access memory).

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) This example (2) is a first example of the present invention in which the present invention is applied to a DRAM.

FIG. 2 (equivalent circuit diagram) shows the structure of a memory cell of a DRAM which is Embodiment I of the present invention.

The DRAM of this embodiment is constructed using a folded pit line method (folded bit line method). D.R.
AM memory cells have complementary data lines D extending in the row direction.
It is arranged at the intersection of one of the word lines WL extending in the column direction.

Memory cell is M I S F E T for memory cell selection.
It consists of a series circuit of Qs and an information storage capacitive element C.

The memory cell selection MISFETQs is composed of n-channel. One semiconductor region of the memory cell selection MISFETQs is connected to one of the complementary data lines DL. The other semiconductor region is an information storage capacitive element C.
is connected to one electrode of the The gate electrode is connected to word line WL. The other electrode of the information storage capacitive element C has a power supply voltage of t/2V. . It is connected to the.

This power supply voltage 1/2 Vcc is an intermediate potential (approximately 2.5 [V]) between the power supply voltage Vcc, for example, the operating potential of the circuit, 5 [V], and the reference voltage Vig, for example, the ground potential of the circuit, 0 [V].
V]).

Next, FIG. 1 (cross-sectional view of the main parts) shows the specific structure of the main parts of the memory cells of the DRAM and the peripheral circuit of the DRAM.
Let's briefly explain using.

As shown in Figure 1, DRAM is made of single crystal silicon.
It is composed of a - type semiconductor substrate 1. A p-type well region 2 is provided on the main surface of the semiconductor substrate 1 in each of the memory cell array formation region and the n-channel MISFET formation region. Also, p-channel M I S F E
In the T formation region, an n-type well region 3 is provided on the main surface of the semiconductor substrate 1 .

As shown on the left side of FIG. 1, the memory cell of the DRAM is formed on the main surface of a p-type potential barrier region 5B in a region defined by a field insulating film 4 and a p-type channel stopper region 5A. ing. The potential barrier region 5B is provided on the main surface of the well region 2, and is configured to reduce α-ray soft errors.

The memory cell selection MI S FET QS is mainly composed of a potential barrier region 5B (channel formation region), a gate insulating film 6, a gate electrode 7, and a pair of n-type semiconductor regions 9 which are a source region and a drain region. has been done. Although the gate material Vi7 is not limited to this gate material, in this embodiment, it is composed of a composite film in which a high melting point metal silicide film is laminated on a polycrystalline silicon film. The gate electrode 7 has a word line (W) extending in the gate width direction.
L) 7 are integrally constructed. The word line 7 is configured to extend over the field insulating film 3.

The information storage capacitive element C is mainly constructed by sequentially stacking a lower electrode 15, a dielectric film 16, and an upper electrode (common plate electrode) 17. This information storage capacitive element C has a so-called stacked capacitor structure.

The lower electrode 15 is connected to the other semiconductor region 9 of the memory cell selection MISFETQs through a connection hole 14 formed in a region defined by the sidewall spacer 11. The lower electrode 15 is provided for each memory cell. The lower electrode 15 is formed of, for example, a polycrystalline silicon film doped with n-type impurities. The connection between the lower electrode 15 and the other half-solid region 9 is made through an n° type semiconductor region 15A formed by diffusing the n type impurity introduced into the lower electrode 15 into the main surface of the potential barrier region 5B. It is being done. The lower electrode 15 is connected to the gate electrode 7 and the word line 7.
The gate electrodes 7. It is electrically isolated from each word line 7. The dielectric film 16 is composed of, for example, a single layer of a silicon nitride film or a silicon oxide film, or a composite film thereof. Upper electrode 1
7 is constructed integrally with that of other adjacent memory cells.

The upper electrode 17 is supplied with a power supply voltage of 1/2V as described above. is applied. The upper electrode 17 is formed of, for example, a polycrystalline silicon film doped with n-type impurities.

Gate electrode 7 of the memory cell selection MISFETQs
, word line 7 are formed by a first layer gate wiring forming process. The lower electrode 14 is formed by a second layer gate wiring forming process, and is, for example, 1500~
It is formed with a film thickness of about 3000 [people]. The upper electrode 17 is formed by a third layer gate wiring forming process, and has a thickness of, for example, about 1,500 to 3,000 [layers].

One of the complementary data lines (DL) 19 is connected to one semiconductor region 9 of the memory cell selection MISFETQs through a connection hole 17 formed in the interlayer insulating film 16. The connection between the semiconductor region 9 and the complementary data line 19 is made with an n° type semiconductor region 18 interposed therebetween.

In order to alleviate the step difference that occurs in the memory cell selection M I S F E T Q s and the information storage capacitive element C,
The surface of the interlayer insulating film 16 is flattened. Although not shown in detail, the interlayer insulating film 16 is CV
Silicon oxide film deposited by D method, P deposited by CVD method
It is formed of a composite film in which an SG film and a silicon oxide film coated by the SOG method are sequentially laminated.

The silicon oxide film deposited by the CVD method is formed to have a thickness of about 1,000 to 2,500 [in], for example, in order to prevent P in the PSG film from leaking particularly into the p-channel MISFET QP formation region. The PSG film is, for example, 4000
~ 5000 [A film thickness of about 1100 [
Glass flow is applied at a high temperature of 'C]. S
The silicon oxide film coated by the OG method has a thickness of 800 to 1000[
Deposited with a film thickness comparable to that of a human being, at approximately 900 to 1000 [℃]
The densification process is carried out at a moderately high temperature.

The complementary data line 19 is formed by a first layer wiring forming process, and is formed of, for example, an aluminum film or an aluminum alloy film to which Si or Cu is added. The complementary data line 19 is, for example, 8000 to 10000 [
The thickness of the film is about the same as that of a human.

A shunt word line (W L ) 22 is provided above the complementary data line 19 with an interlayer insulating film 20 interposed therebetween. Although the shunt word line 22 is not shown,
In a predetermined region, it is once connected to the intermediate conductive film formed in the first layer wiring forming step through the contact hole 21 formed in the interlayer insulating film 20. This intermediate conductive film is connected to the connection hole 1.
7 to word m7. In other words, the shunt word line 22 is electrically short-circuited with the word line 7, and is configured to reduce the apparent resistance value of the word line 7.

The surface of the interlayer insulating film 20 is flattened in order to reduce the step difference caused by the complementary data line 19 and the like. In this embodiment, the interlayer insulating film 20 is a composite film in which a silicon nitride film 20A deposited by a plasma CVD method, a silicon oxide film 20B applied by an SOG method, and a silicon oxide film 20C deposited by a plasma CVD method are sequentially laminated. It is formed of. The silicon nitride film 20A deposited by the plasma CVD method is formed so as to reduce hillocks that occur mainly on the surface of the complementary data line 19.
It is formed with a film thickness of approximately The silicon oxide film 20B coated by the SOG method is deposited to a thickness of, for example, about 1,500 to 2,500 mm, and is not subjected to densification treatment, mainly to alleviate the step shape. The silicon oxide film 20G deposited by the plasma CVD method is deposited to a thickness of about 5000 to 7000 [layers] mainly to ensure the film thickness necessary for insulation isolation.

The shunt word line 22 is formed in the second layer wiring formation process, and is made of the same material as the wiring formed in the first F third wiring formation process, and has a material of 10,000 to 1
It is formed with a film thickness of about 2000 [people].

The peripheral circuit of the DRAM is composed of an n-channel MISFETQn shown in the center of FIG. 1 and a p-channel MISFETQp shown on the right side of FIG. In other words, the peripheral circuit is composed of complementary MISFETs (CMO3).

The n-channel MISFET Qn is formed on the main surface of the well region 2 in a region defined by the field insulating film 4 and the channel stopper region 5A. In other words, the n-channel MISFETQn mainly operates in the well region (
channel formation region) 2, gate insulating film 6, gate electrode 7
, a pair of n-type semiconductor regions 9 and a pair of go-type semiconductor regions 12, which are source and drain regions. This n-channel MISFETQn is configured with an LDD structure, although it is not limited to this structure.

A wiring 19 formed in the first layer wiring formation step is connected to the semiconductor region 12 of the n-channel MISFETQn with a semiconductor region 18 interposed therebetween. A wiring 22 formed in the second layer wiring forming step is connected to this wiring 19.

The p-channel MISFET Qp is formed on the main surface of the well region 3 in a region defined by the field insulating film 4 . In other words, p-channel MISFETQ
P is mainly composed of a well region (channel forming region) 3, a gate insulating film 6, a gate voltage Vi7, a pair of p-type semiconductor regions 10 and a pair of p°-type semiconductor regions 13, which are source and drain regions. There is. This P channel MIS
FETQp has an LDD structure. A wiring 19 is connected to the semiconductor region 13 of the p-channel MISFETQp.

A passivation film (final protective film) 2 is provided on the entire surface of the substrate including the upper parts of the shunt word lines 22 and the wirings 22.
3 is provided. The passivation film 23 is formed of an insulating film with excellent moisture resistance, such as a silicon nitride film or a silane film.

In the DRAM configured in this manner, a hydrogen-based ion absorption film 17A is provided at least in the formation region of the p-channel MISFETQp. This hydrogen-based ion absorbing film 17A is provided on the interlayer insulating film 8 so as to cover the channel forming region (3) and the source and drain regions (10 or 13) in the vicinity thereof. The hydrogen-based ion absorbing film 17A is basically a silicon oxide film 20 coated by the SOG method on the channel forming region and the interlayer insulating film 20.
It suffices if it is provided between B and B. Metal films such as silicon oxide films, silicon nitride films, and high-melting point metal films allow hydrogen-based ions to pass through, so the hydrogen-based ion absorption film 17A is made of a material that absorbs hydrogen-based ions, such as a polycrystalline silicon film, or is mainly composed of it. Formed with a composite membrane. In this embodiment, the hydrogen-based ion absorption film 17A is the information storage capacitive element C of the memory cell.
It is formed of the same conductive film (same manufacturing process) as the upper electrode 17 (or lower electrode 15). In this embodiment, the hydrogen-based ion absorption film 17A is also provided in the n-channel MISFETQn formation region.

As a result of failure analysis conducted by the present inventor, the threshold voltage vth of the p-channel MISFET QP fluctuates (increases) over time, as shown in Figure 3 (diagram showing stress time dependence of threshold voltage). do. This p-channel MISFETQP
Although not shown in FIG. 3, the inventor has confirmed that the amount of variation in the threshold voltage of is larger than that of the n-channel MISFETQn.

In this way, hydrogen-based ions (H" and R2
DRA having silicon oxide 11420B containing a large amount of
In M, a hydrogen-based ion absorption film 17 that absorbs hydrogen-based ions released from the silicon oxide film 20B is provided between the n-channel MISFET Qp and the silicon oxide film 20B.
By providing A.

Since it is possible to reduce trapping of hydrogen-based ions in the channel formation region (3) of the n-channel MI 5FETQp or the silicon substrate in its vicinity, the p-channel MISF
Fluctuations in the threshold voltage of ETQP over time can be reduced. As a result, the electrical reliability of the DRAM can be improved.

Further, in the DRAM, the hydrogen-based ion absorption film 17A is formed in the same manufacturing process as the upper electrode 17 (or lower electrode 15) of the information storage capacitive element C of the memory cell. The manufacturing process can be reduced by the amount corresponding to the forming process.

(Example 2) This example 2 is a second example of the present invention in which the present invention is applied to an SRAM.

FIG. 4 (equivalent circuit diagram) shows the configuration of a high-resistance load type memory cell of an SRAM, which is Embodiment 2 of the present invention.

As shown in FIG. 4, the high resistance load type memory cell of the SRAM is arranged at the intersection of the complementary data lines DL and 1 and the word line WL. Complementary data lines DL extend in the row direction. The word line WL extends in the column direction. The memory cell is composed of a flip-flop circuit and two transfer MISFETs Qt and Qt2, each of which has one semiconductor region connected to its pair of input/output terminals.

Each of the transfer MISFETQt, Qt2 is composed of n channels. MISFE for transfer
The other semiconductor regions of TQt and Qt2 are connected to complementary data line DL. Transfer MISFETQt
The gate electrodes of Qt2 and Qt2 are connected to the word line WL.

The flip-flop circuit is configured as an information storage section (having an information storage node section).

The flip-flop circuit consists of two driving MISFETQd
It consists of a load element R□ and a load element Qdz, and two high-resistance load elements R□ and Ryo. The drive MISFET Qd1
．． Each of Qd2 is composed of n channels.

The source regions of the driving MISFETs Qd1 and Qd2 are connected to a reference voltage V0, for example, a circuit ground potential 0 [V]. The drain region of the drive MISFET Qd1 is connected to the high resistance load element R2, one semiconductor region of the transfer MISFET Qt2, and the gate electrode of the drive MISFET Qd2, respectively.

The drain region of the drive MISFET Qd2 is connected to the high resistance load element R, one semiconductor region of the transfer MISFET Qt1, and the gate electrode of the drive MTSFET Qd1. Each of the high-resistance load elements R and R2 is connected to a power supply voltage V e e, for example, a circuit operating voltage 5 [V].

Next, the specific configuration of the SRAM memory cell configured as described above will be briefly explained using FIG. 5 (a sectional view of the main part).

As shown in FIG. 5, the high resistance load type memory cell is formed on the main surface of the well region 2 in a region defined by the field insulating film 4 and the channel stopper region 5A.

MISFETQt for transfer of high resistance load type memory cells,
Qtz mainly covers the well region 2 and the gate insulating film 6.
, a gate electrode 7, a pair of n-type semiconductor regions 9 and a pair of n-type semiconductor regions 12, which are source and drain regions.
It consists of Transfer MISFET Qt, Qtz
Although the gate electrodes 7 of each word line (WL) are not shown,
It is integrated with 7. MISF for this transfer
Each of E TQt, and Qt2 is configured with an LDD structure.

A complementary data line 19 is connected to the other semiconductor region 12 of each of the transfer MISFETs Qt and Qt through connection holes 17 formed in interlayer insulating films 24, 27 and 16. Complementary data line 19 is configured to extend above interlayer insulating film 16 in the row direction.

The surface of the opened fiber rim film 16 is flattened in substantially the same manner as in the embodiment (2). The interlayer insulating film 16 is, for example, CV
Silicon oxide film deposited by D method, P deposited by CVD method
It is formed of a composite film in which an SG film and a silicon oxide film coated by the SOG method are sequentially laminated. Complementary data line 1
Reference numeral 9 is configured to extend on the gate electrode 6 of each of the driving MISFETs Qd and Qd2 in the same direction as the gate width direction thereof. (The 1-complementary data line 19 is formed of, for example, an aluminum alloy film, substantially the same as in Embodiment I.

Transfer MISFET Qt1, Q through the connection hole 17
After complementary data lines 19 are formed so as to connect to the other semiconductor region 12 of each of tz, hydrogen annealing (R2
annealing) is applied. Hydrogen annealing is, for example, 400
This is carried out for about 20 to 30 minutes in a mixed gas atmosphere of hydrogen gas and nitrogen gas at about 450 ['C]. This hydrogen annealing is performed mainly to improve the ohmic characteristics at the connection portion between the complementary data line 19 (aluminum alloy) and the semiconductor region 12 (single crystal silicon substrate).

Each of the driving MISFETs Qd1 and Qd2 mainly includes a well region 2, a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 9 serving as a source region and a drain region, and a pair of n°-type semiconductor regions 12. It is configured. Each of the driving MISFETs Qd1 and Qd has an LDD structure.

One semiconductor region 12 of the transfer MISFET Qt
A high resistance load element R is connected to one end of the gate electrode 7 of the driving MISFET Qd with a conductive film 26A interposed therebetween. Although not shown in FIG. 5, the transfer M
One semiconductor region 12 of ISFETQt2 and driving M
A conductive film 2 is provided at one end of the gate electrode 7 of the ISF'ETQd2.
A high resistance load element R2 is connected with 6A interposed therebetween. The conductive film 26A is.

The semiconductor region 12 and the gate electrode 7 are connected to each other through a connection hole 25 formed in an interlayer insulating film 8 provided on the gate electrode 7 and an interlayer insulating film 24 provided over the entire surface of the substrate including the upper part thereof. The conductive film 26A is formed of, for example, a polycrystalline silicon film into which n-type impurities are introduced to reduce the resistance value. Each of the high-resistance load elements R1 and R2 is formed of a polycrystalline silicon film 26B into which n-type impurities or n-type impurities that reduce resistance are not introduced or are slightly introduced.

The high resistance load element R□ is arranged above the gate electrode 7 of the driving MISFET Qd□. Similarly, the high resistance load element R2 is arranged above the gate electrode 7 of the driving MISFET Qd2.

The polycrystalline silicon film 26B forming each of the high resistance load elements R and R2 is connected to a power supply voltage arrangement (V, c) 26G. This power supply voltage wiring 26C is formed of, for example, a polycrystalline silicon film into which n-type impurities are introduced to reduce the resistance value.

The aforementioned conductive film 26A, the polycrystalline silicon film 26B which is each of the high resistance load elements R and R2, and the power supply voltage wiring 26C are formed of the same conductive film, and are integrally formed (formed in the same manufacturing process). ing.

A passivation film 23 is provided on the entire surface of the substrate including the complementary data line 19.

The SRAM configured in this manner is constructed using a hydrogen-based insulating film 27 interposed over at least the high resistance load element R, R2 (polycrystalline silicon film 13B), the conductive film 26A in its vicinity, and the power supply voltage wiring 26C. An ion absorption membrane 28 is provided. The hydrogen-based ion absorbing film 28 is formed before the hydrogen annealing described above in order to reduce trapping of hydrogen-based ions in each of the high resistance load elements R and R2 and the polycrystalline silicon film in their vicinity. It is formed to cover the polycrystalline silicon film. The hydrogen-based ion absorbing film 28 is formed of a polycrystalline silicon film as in Example I above. Since the hydrogen-based ion absorbing film 28 requires an additional manufacturing process and hydrogen-based ions permeate over time, it is preferable to leave it in place even after hydrogen annealing.

As a result of failure analysis conducted by the inventor, Figure 6 (diagram showing the hydrogen annealing temperature dependence of leakage current of high resistance load element)
As shown in FIG. 2, it was confirmed that as the hydrogen annealing temperature rose, the leakage current amount of the high resistance load element R decreased. Data A is the result of measuring the amount of leakage current flowing between the source region and the drain region in a parasitic MO3FET in which the high resistance load element R is the channel formation region and the complementary data line (DL) 19 is the gate electrode. It shows. Data B is the result of measuring the amount of leakage current flowing between the source region and the drain region in a parasitic MO8FET in which the high resistance load element R is used as the channel formation region, and the gate electrode 7 of the driving MISFET Qd is used as the gate electrode. It shows.

In this way, high resistance load element R (polycrystalline silicon film 13B)
In an SRAM in which hydrogen annealing is performed after forming
By providing the hydrogen-based ion absorption film 28 above the high-resistance load element R when performing the hydrogen annealing, it is possible to reduce trapping of hydrogen-based ions in or near the high-resistance load element R. , high resistance load element R
Fluctuations (decrease) in leakage current amount can be reduced. In other words, since power is reliably supplied through the high-resistance load element R, the potential of the information storage node can be held stably and erroneous operations such as information inversion can be prevented.

Further, the DRAM of Example I described above is the SRAM of Example H.
Since hydrogen annealing is performed in the same manner as in Example 1 above,
The hydrogen-based ion absorbing film 17A provided in the DRAM can also absorb hydrogen-based ions generated during hydrogen annealing.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to DRAM or SRAM,
It can be widely applied to semiconductor integrated circuit devices having a silicon oxide film coated by the SOG method and semiconductor integrated circuit devices subjected to hydrogen annealing.

〔Effect of the invention〕

The effects obtained by typical inventions disclosed in this application are as follows.

The electrical reliability of a semiconductor integrated circuit device having a silicon oxide film coated by the SOG method can be improved.

The electrical reliability of a semiconductor integrated circuit device subjected to hydrogen annealing can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part showing the configuration of a DRAM memory cell according to Embodiment I of the present invention. FIG. 2 is an equivalent circuit diagram showing the configuration of the memory cell, FIG. 3 is a diagram showing the stress time dependence of the threshold voltage of MISFET in the peripheral circuit of the DRAM, and FIG. An equivalent circuit diagram showing the configuration of a high-resistance load type memory cell of an SRAM according to Example 2, FIG. 5 is a sectional view of a main part showing the configuration of the memory cell, and FIG. FIG. 3 is a diagram showing the hydrogen annealing temperature dependence of leakage current of an element. In the figure, 2, 3...well region, 6...gate insulating film, 7...gate electrode, 9, 10.12.13...
・Semiconductor field. 16, 20... Interlayer insulating film, 20A... Silicon nitride film, 20B. 20C...Silicon oxide film, 19.22...Wiring, 1
7A, 28...Hydrogen-based ion absorption membrane, 26A...
Conductive film, 26B: Polycrystalline silicon film, 26C: Power supply voltage wiring, Q: MISFET, C: Capacitive element for information storage, R: High resistance load element.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a silicon oxide film coated by a spin-on-glass method on top of a MISFET or a resistive element formed of a silicon film, the MISFET
Alternatively, a semiconductor integrated circuit device comprising a hydrogen-based ion absorbing film that absorbs hydrogen-based ions released from the silicon oxide film between the resistive element and the silicon oxide film. 2. The semiconductor integrated circuit device according to claim 1, wherein the hydrogen-based ion absorption film is formed of a single layer of polycrystalline silicon film or a composite film mainly composed of polycrystalline silicon film. 3. The semiconductor integrated circuit device has an MIS for memory cell selection.
The DRAM has a memory cell having a series circuit of an FET and an information storage capacitive element having a stacked capacitor structure, and the hydrogen-based ion absorption film is the same as the electrode of the information storage capacitive element having the stacked capacitor structure. A method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is formed in a manufacturing process. 4. In a semiconductor integrated circuit device in which hydrogen annealing is performed after forming a MISFET or a resistance element made of a silicon film, when performing the hydrogen annealing, the MISFET
Alternatively, a semiconductor integrated circuit device characterized in that a hydrogen-based ion absorption film that absorbs hydrogen-based ions is provided above the resistive element.