JPH01304492A - Area painting generation circuit - Google Patents

Abstract

PURPOSE:To minimize the number of times of writing to a frame memory, to decide whether or not an area is painted out at a time and eliminate the need to clear a cache, and to paint out the area speedily by drawing the arithmetic result of area painting in fast buffer memory (cache) units. CONSTITUTION:The (x) and (y) coordinates of the cache 16 are specified for a C field, the coordinates in the cache are specified for a B field, and the coordinates on a display device are specified for an A field. A counter 7 indicates the (x) coordinate of the cache 16 being drawn. A register 8 stores the cache X coordinate of the rightmost end of a selected cache (y) coordinate. Registers 1-6 store the (x) coordinates of the right and left ends of the cache (y) coordinates, in-cache (x) coordinates, and in-cache (y) coordinates 0-2. A shift register 10 obtains the outputs of the registers 1 and 2, determines a data line of the cache 16 through comparators 11 and 12, and latch a line of the cache with the output of the shift register 18. When the counter 7 reaches a specific value, the end of arithmetic is reported through a control line 22. The painting becomes about twice as fast as before.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an area filling generation circuit in a raster scan type graphic display device for displaying input/output information of an electronic computer or the like.

2. Description of the Related Art A graphic display device has a frame memory corresponding to the screen to be displayed, writes an arbitrary figure to the frame memory, reads out the figure from the frame memory in response to scanning of the screen, and displays the figure. To draw an arbitrary straight line, a function to calculate the coordinates of pixels located on the straight line and a function to write the coordinates into frame memory are required.

Therefore, in graphic display devices that require high speed, a digital differential analyzer that generates point coordinates on a line segment from a starting point to an ending point is generally used.
Differential Analyzer DD
A), a high-speed buffer memory (hereinafter abbreviated as cache) for temporarily storing the output of this ODA as M×N pixel data, and a frame memory.

An example of filling in an area in the graphic display device configured as described above will be described below. Since DDA draws straight lines, the left and right coordinates for each X coordinate of the filled area are calculated in an external circuit, and a straight line parallel to the y axis is drawn using DDA to fill the area. do. For simplicity, the size of the buffer memory from this DDA is assumed to be 3×3, and is (6,3), (9°3),
Assume that the area connecting the four points (3, 6) and (9, 6) is filled in.

FIG. 2 shows the relationship between the coordinates on the display, the coordinates of the cache, and the coordinates in the cache. A is the x, x coordinate on the display, B is in the cache, and C is the cache.

Furthermore, Fig. 5 shows how the area is actually filled in.

First, the coordinates on the display are (6, 3) as the starting point, (9,
The DDA is operated with 3) as the end point. ODA is the cache coordinate (2,1), and the coordinate in the cache is (0,O)
, (1,0), and (2°O) are set to "4", and after writing to the frame memory, the cache is cleared (part 1 in Fig. 5).

Next, the DDA sets the cache coordinates (0,0) to "H" at the cache coordinates (3,1), writes it to the frame memory corresponding to the coordinates (9,3) on the display, and then (
(Part 2 in FIG. 5), the straight line drawing from (6, 3) to (9, 3) is completed by clearing the cache.

While the DDA is performing the above operation, the external circuit calculates y=
The left end (5, 4) and right end (9, 4) of the display coordinates of 4
), and after waiting for the end of DDA, operate DDA with starting point (5, 4) and ending point (9, 4).

After that, increase the X coordinate on the display in the same way,
When the straight line drawing from (3, 6) to (9, 6> is completed, the filling is completed. The numbers in FIG. 5 indicate the order of filling in each cache.

Problems to be Solved by the Invention However, in the above configuration, the DDA for straight line drawing
is used as is, so when performing fill-in drawing, m
Since only m caches at most can be filled out of x n caches, the number of accesses to the frame memory increases and the filling speed is slow.

In view of this point, it is an object of the present invention to provide a graphic display device that can also perform high-speed fill-in drawing.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a graphic display device that temporarily stores drawing pixels in a buffer memory of multiple rows and multiple columns and writes them to a frame memory.
A group of registers for storing the coordinates of the left and right ends of the fill area computed for each X-coordinate by the area filling circuit, outside the number of columns of the buffer memory, and the rightmost coordinate of the right end coordinates stored in the register group. A register that stores the data, a counter that indicates the X coordinate of the buffer memory during filling, and a register that determines whether it is inside or outside the filling area.
From the a l/register group output and the output of the counter,
The area filling generation circuit includes means for calculating each row of the buffer memory.

Effects According to the present invention, with the above-described configuration, the results calculated for filling the area are drawn in cache units, so that writing from the cache to the frame memory can be executed in the minimum number of times. In addition, it is possible to determine whether to fill each line in the cache every time, and also to determine whether to fill in all the caches, so there is no need to clear the cache, so filling can be performed at high speed. can.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the area filling generation circuit of the present invention. The size of the cache is 3×3, and the relationship between display coordinates, cache coordinates, and cache coordinates is shown in FIG. Figure 3 shows the first
FIG. 2 is a truth diagram of encoder 1.4.15 used in one embodiment of the present invention in FIG. FIG. 4 is an explanatory diagram showing the execution of filling an area in display coordinates.

The coordinates of the left and right ends of the filled area are calculated for each y-coordinate by the number of cache columns by an external circuit, and are output as cache coordinates and coordinates in the cache.For y-coordinates that are not filled in the cache, the screen is set to the left-most coordinate. The cache coordinates (3 in this example) indicating the outside of the cache are calculated.

- Examples are (6,3), (9,3), (3°6), (9
, 6) where the area connecting the four points is filled will be explained. 10.18 is a shift register which is loaded with YO at "H" and others at "L" at reset, and is configured so that the output of Y2 becomes the output of YO with a clock. 7 indicates the cache X coordinate being drawn on the counter. 8 is a register, the rightmost cache X of the selected cache X coordinate
Remember the coordinates. 9 is the cache X being drawn in the register
Remember the coordinates. 1 to 6 are registers in which the cache X coordinates and in-cache X coordinates of the left end and right end of the selected cache X coordinate are stored in the order of in-cache y coordinate 0 and 2, respectively.

In this example, register 1 stores cache X coordinate 2 and cache internal coordinate O (hereinafter abbreviated as 2-0).
3-0. 1-2° for register 3, 3 for register 4
-○, register 5 is 1-1. The register 6 stores 3-0, respectively. The counter 7 is loaded with the minimum value of the cache X coordinate (1 in this example). Register 8 stores the maximum value of the cache X coordinate (3 in this example),
Register 9 is loaded with 1.

From the output of the system register 10, the outputs of registers J and 2 are first enabled. This output and the output of the counter 7 are compared by comparators 11 and 12. In this example, since the comparator 11 has A-2°B=1, A>B is "L" and the others are "H", and the comparator 12 is A= 1. B=2
Therefore, A<B is output as L and the others are output as "H".) Based on the result and the output of registers 1 and 2, in this example, the encoder 14 outputs all "L" since Dl is L, and the encoder 14 outputs "L", and encoder 14 outputs "L" as Dl is L. Since DO is “L”, the driver 15 outputs all “H”),
Based on the result, the data lines of the cache 16 are determined (all "L" in this example).

With the output of the shift register 18, the (0,
O), (1, O), and (2, 0) are selected and latched at the rising edge of the clock. At the same time, the shift register 10 enables the outputs of the next registers 3 and 4, and performs the next stage calculation. When the calculation is performed up to the final stage, the flip-flop 17
The clock is masked until the control signal line 20 is asserted to indicate that the data has been operated and the data in the cache has been completed, and the control signal line 21 is asserted to L, indicating that the transfer has been completed. The register 4 stores the y coordinates, and the y coordinates of the counter 7 are used to write into the frame memory.

When the transfer of the data in the cache 16 is completed, the output of the shift register 1.0 becomes H, so the value of the counter 7 is incremented, and the same calculation as above is performed. The value of counter 7 is compared with the value of register 8 by comparator 8, and if the value of counter 7 becomes larger,
By masking the clock and using the control signal line 22, ti
Notify the end of calculation. Further, registers 1 to 6, 8 to 9. This is the sequence until the initial setting of the counter 7 is completed.

FIG. 4 shows the order in which the areas painted and 5C written in the frame memory are written in as described above. In this example, the same pattern as in the conventional example (FIG. 5) is completed by writing to the frame memory six times, which is approximately twice as fast as the conventional example.

Effects of the Invention As described above, according to the present invention, by adding a simple circuit, it is possible to fill an area at high speed with a minimum number of frame memory accesses, which is extremely useful in practice. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an area filling generation circuit in an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the correspondence between coordinates on the display, coordinates in the cache, and coordinates in the cache. is a truth value diagram of an encoder used in an embodiment of the present invention, FIG. 4 is an explanatory diagram showing access to the frame memory when filling an area according to an embodiment of the present invention, and FIG. FIG. 7 is an explanatory diagram showing access to a frame memory when filling an area according to a conventional example. 1-6...Register, 7...Counter, 8-9...Register, 10...Shift register, 11-13... Comparator, 14.15... Encoder, 16...
··cache. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Figure 40 No. 5

Claims (1)

[Claims] In a graphic display device that temporarily stores drawing pixels in a buffer memory of multiple rows and multiple columns and writes them to a frame memory, coordinates of the left end and right end of a filled area calculated for each y coordinate are stored for the number of columns of the buffer memory. a register group, a register that stores the rightmost coordinate among the rightmost coordinates stored in the register group, a counter that indicates the x-coordinate of the buffer memory that is being filled, and a register that determines whether the area is a filled area. from the output of the group and the output of the counter to the buffer.
1. An area filling generation circuit comprising means for calculating for each row of memory.