JPH01303743A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit precipitation of Si at a contact part and to contrive a reduction in Si residues at the time or etching on a wiring pattern in the forming process of a metal film for wiring by a method wherein a pure Al film of a desired film thickness is adhered by a sputtering deposition method and ions are implanted in the Al film in such a way that the film has a specified content of Si. CONSTITUTION:A pure Al film 3 is formed by a sputtering deposition method and thereafter, Si ions are implanted in the whole surface of the film 3 to form an Al-Si alloy film for wiring which has a mean Si concentration of 1 to 2% in the vicinity of the lower interface of the film 3. Thereby, etching residues at the time of formation of a wiring pattern subsequent to the formation of the alloy film are reduced and at the same time, an increase in a contact resistance at a contact part due to precipitation of excessive Si subsequent to a heat treatment is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device in which wiring is formed using an aluminum-silicon alloy film.

[Conventional technology]

It is well known that an M-St alloy film is often used for wiring that comes into contact with a silicon substrate of a semiconductor device at a contact portion and passes over an insulating film that covers the substrate.

If pure M is used for wiring, M
In the area where the wiring and the substrate St are in contact, the subsequent heat treatment such as sintering causes M and the substrate S+ to interdiffuse, and in particular, the substrate Si has a solid solubility limit in M at the heat treatment temperature, that is, 0.25 weight at 400°C. %, 0.5% by weight at 450°C
, M is supplied to 0.8% by weight at 500°C, and alloyed M enters the substrate where St is consumed in the form of a spike, and if the pn junction is shallow, it penetrates the pn junction and causes junction breakdown, causing a short circuit. , leading to leaks, etc.

Therefore, by adding a small amount of A7-Si alloy containing 1 to 2% by weight of M, that is, about 1 to 2 atomic%, it is possible to suppress the bond failure due to alloy spikes. Also,
The addition of Si increases the mean time to failure (MTF) due to electromigration silane, which also has the advantage of increasing reliability as a wiring.

[Problem to be solved by the invention]

On the other hand, the disadvantage of adding Si to M is that excess Si, which exceeds the solubility, usually precipitates at the grain boundaries of M, but depending on the heat treatment conditions, it can be formed as bulk Si precipitates by solid phase epitaxial growth. Particularly, it often precipitates on the stepped portions and contact portions of wiring, and if it forms on the wiring portions, it may cause disconnection of the wiring.

This is because stress is locally applied to the place where Si is precipitated, making dislocations more likely to occur. When deposited on the contact portion, since St contains M and is p-type S+, the ohmic properties with the n diffusion layer are likely to deteriorate, causing an increase in contact resistance.

Furthermore, when the contact hole becomes 1-square reduction, the ratio of precipitated Si covering the contact increases, so the resistance increases rapidly, and in the worst case, the Si precipitated grains cause a contact failure of about 10Ω. The diameter is large and 1
This is because it will be about -. In addition, it is known that Si precipitation has a negative effect on MTF due to electromigration, and there are reports that the electromigration silane resistance returns to the same level as M.

Next, as an example, FIG. 2 shows the distribution of Si in the depth direction of the A7-S+ alloy film immediately after sputtering. Sputtering was performed by heating the substrate using an A7-1.2% Si alloy target, and the film thickness was 1 μm.

As shown in the figure, Si is locally highly concentrated at the interface with the substrate. This increases as the substrate temperature increases.
This is because i tends to segregate on the surface and interface of the film. If the substrate is not heated, St is distributed almost uniformly in the film. However, in this case, it cannot be carried out because the problem arises that an overhanging covering shape occurs at the step part, resulting in a reduction in step coverage. Since the content of St has increased in the etching process, there have been problems in that it remains as a residue after etching the wiring pattern and that the Si precipitates described above become more agglomerated.

The object of the present invention is to eliminate the above-mentioned drawbacks, to prevent the formation of alloy spikes between the Si substrate and the wiring metal film, and to prevent the formation of alloy spikes between the wiring metal film and the Si substrate.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not leave any residue of t and does not cause an increase in contact resistance at a contact portion with an n4 diffusion layer.

[Means to solve the problem]

In order to solve the above problems, the present invention
When manufacturing a semiconductor device having wiring made of a silicon alloy film, after forming a pure aluminum film by sputter deposition, silicon ions are implanted into the entire surface of the aluminum film to form a 1 to 2 c/G near the lower interface. It is assumed that an aluminum-silicon alloy film for wiring is formed having an average silicon concentration of .

[Effect]

The silicon concentration at the lower interface of the kl-Si alloy wiring can be increased to the desired 1 to 2% by ion implantation, which reduces etching residue during subsequent wiring pattern formation and eliminates excess Si after heat treatment. Reduces increase in contact resistance at the contact portion due to precipitation. In addition, A111I is made amorphous due to irradiation damage during Si ion implantation, thereby suppressing the growth of M grain size and suppressing the formation of hillocks.

〔Example〕

FIG. 1 fat to [0] sequentially shows the wiring forming process of an embodiment of the present invention, and shows a 5iOz film 2 formed on a Si substrate 1.
An opening 4 is made in the contact part, and first a pure M film 3 with a thickness of 10,000 is deposited using a normal magnetron baffter device (Figure a). By heating the back surface of the substrate 1 to about 200° C., it is possible to improve the step coverage of the adhesive at the contact portion having a high aspect ratio. Next, using SlFm as the ion source gas, S
Acceleration voltage 500~600kV, dose I3~
Ion implantation is performed under the condition of 4X10” (J-”) (Figure b
). In this case, by using a high current ion implanter,
Since the cooling efficiency can be increased, the wafer temperature during processing can be kept within 100°C. Furthermore, if the rotational ion implantation method is used, it is possible to reduce the shadow effect due to the step difference in the contact portion, etc., and it is possible to achieve a uniform dose within the plane without depending on the step difference. Under the above implantation conditions, the projected range (RP) of ions is #kJ0.65u and the standard step difference (ΔRP) is approximately 0.35μ, so the film 3 after implantation shown in Figure (C)
The area near the interface with the Si substrate 1 or the Si film 2 of 1 is S.
i concentration is about 1%, Si atomic number density is about 6 X IQ
“ell −” and the peak value is 1 at R1−.
．． It will be about 6%. In this way, abnormal segregation at the interface can be reduced, and as a result, it is possible to prevent an increase in contact resistance due to Si precipitation and to reduce Si residue during etching. Furthermore, the M film 31 becomes amorphous due to irradiation damage during ion implantation, making it possible to suppress grain growth and reducing hillocks. Although the above embodiments particularly focus on the advantages that arise in the case of one-layer wiring, it also has the remarkable advantage of reducing through-hole resistance in multi-layer wiring such as M two-layer wiring. Since it is dull, Si precipitation becomes a problem at the contact surface with the first layer USI wiring. In A7-3i produced by ordinary sputter deposition, there is segregation of Si also on the upper surface of M, as shown in FIG. However, since the Si concentration on the upper surface of the A7-5i alloy film 31 formed by the ion implantation is very low and falls at the foot of the Gaussian distribution, precipitation of St is unlikely to occur, and good through-hole resistance can be obtained.

〔Effect of the invention〕

According to the present invention, in the process of forming a metal film for wiring, a pure M film of a desired thickness is first deposited by sputter deposition, and the &si ions are added to the A7 film so that the average St content near the lower interface is 1. By implanting ions to a concentration of about 2%, abnormal segregation of Si is suppressed, especially in the contact portion, and an increase in contact resistance and Si residue during wiring pattern etching are reduced. Furthermore, the crystal grain growth of M is inhibited due to the slight amorphization caused by radiation damage during ion implantation, making it possible to reduce hillocks. Also,
In M multilayer wiring, the Si concentration at the upper surface of the lower JiAJ-3i wiring is very low, so the precipitation of Si in the through holes that connect with the upper layer dull film can be ignored, resulting in good contact resistance. There is also the advantage that it becomes possible to obtain

[Brief explanation of the drawing]

Figure 1 + al ~ (C1 is a cross-sectional view sequentially showing the wiring forming process of one embodiment of the present invention, Figure 2 is S i f1 in the thickness direction immediately after sputter deposition of an A7-1.2% Si alloy film
It is a 4 degree distribution map. 1: Si substrate, 2: 5ift film, 3: Pure M film, 31
:A77 layer diagram Figure 2

Claims (1)

[Claims] 1) When manufacturing a semiconductor device having wiring made of an aluminum-silicon alloy film, a pure aluminum film is formed by sputter deposition, and then silicon ions are implanted into the entire surface of the aluminum film to form a layer near the lower interface. A method for manufacturing a semiconductor device, comprising forming an aluminum-silicon alloy film for wiring having an average silicon concentration of 1 to 2%.