JPH01302791A - Buried structure semiconductor laser - Google Patents

Buried structure semiconductor laser

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Publication number
JPH01302791A
JPH01302791A JP21936188A JP21936188A JPH01302791A JP H01302791 A JPH01302791 A JP H01302791A JP 21936188 A JP21936188 A JP 21936188A JP 21936188 A JP21936188 A JP 21936188A JP H01302791 A JPH01302791 A JP H01302791A
Authority
JP
Japan
Prior art keywords
layer
current
type
buried
semiconductor laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21936188A
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Japanese (ja)
Other versions
JP2780275B2 (en
Inventor
Susumu Asata
麻多 進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Publication date
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Publication of JPH01302791A publication Critical patent/JPH01302791A/en
Application granted granted Critical
Publication of JP2780275B2 publication Critical patent/JP2780275B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To reduce leak current to almost zero, and realize oscillation of high efficiency by arranging a band gap barrier layer between a current flowing part and a current blocking layer, which barrier layer has always a forbidden bandwidth larger than that of an active layer and that of a clad layer. CONSTITUTION:A mesa type current flowing part, in which an active layer 11 is sandwiched by a P-type clad layer 12 and an N-type clad layer 13, is filled with a current blocking layer 14 composed of a semiconductor layer having a deep impurity level. A current blocking layer 15, in which forbidden bandwidth of the parts in contact with the region 11 and the clad layer 12 is always larger than that of region 11 and that of the clad layer 12, is formed. Even in the case where the difference of the forbidden bandwidth at the interface of the part 15 is small, the interface sufficiently operates as a barrier, if only the difference is room temperature energy 0.025eV or more. As a result, leak current component is remarkably reduced. Thereby the leak current becomes almost zero, and oscillation of high efficiency is realized.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光通信や光情報処理に用いられる半導体レーザ
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor laser used in optical communications and optical information processing.

(従来の技術とその問題点) 半導体レーザは光通信や光情報処理に用いられるキーデ
バイスの一つであり、高速の変調特性を持ち、かつ高い
効率で発振することが期待されている。しかし、従来の
半導体レーザでは上記2つの特性をともに満足すること
が困難であった。以下、従来製作されてきた半導体レー
ザの問題点を先ず述べ、次にこれらの問題点を改魯する
目的で試みられている第2の従来技術の残されている問
題点について説明する。
(Prior art and its problems) Semiconductor lasers are one of the key devices used in optical communications and optical information processing, and are expected to have high-speed modulation characteristics and oscillate with high efficiency. However, it has been difficult for conventional semiconductor lasers to satisfy both of the above two characteristics. Hereinafter, the problems of conventionally manufactured semiconductor lasers will be described first, and then the remaining problems of the second conventional technique, which has been attempted to overcome these problems, will be described.

従来製作されている代表的な半導体レーザとして、2重
溝平面埋込み構造半導体レーザ(DoubleChan
nel Planar Buried Heteros
tructure La5erDiode:略称DC−
PBHLD)があり、ジャーナル、オブ、ライトウェー
ブ・テクノロジー、LT−1巻、1983年3月号、1
95−202頁に詳述されている。この半導体レーザは
、第2図(a)のように溝部分をpnpn+f!成にし
、埋込み界面に形成されるpn接合の接合電位により電
流を阻止するようになっている。この構造に代表される
pn接合の接合電位による電流阻止構造は接合に電圧が
直接印加されるため、接合への印加電圧が高く接合を横
切って流れる電流が大きくなりやすい点、及びpn接合
が10pF以上の静電容量を有するため10Gb/s近
い高速変調は困難であるという問題点があった。
A typical semiconductor laser manufactured conventionally is a double-groove planar buried structure semiconductor laser (DoubleChan).
nel Planar Buried Heteros
Structure La5er Diode: Abbreviation DC-
PBHLD), Journal of Lightwave Technology, Volume LT-1, March 1983 Issue, 1
Details are given on pages 95-202. This semiconductor laser has a groove portion of pnpn+f! as shown in FIG. 2(a). The current is blocked by the junction potential of the pn junction formed at the buried interface. In the current blocking structure using the junction potential of a p-n junction, which is typified by this structure, voltage is directly applied to the junction, so the voltage applied to the junction is high and the current flowing across the junction tends to be large, and the p-n junction is 10 pF. There is a problem in that high-speed modulation of nearly 10 Gb/s is difficult because of the capacitance above.

次に、これらの問題点を改善するため、図2(b)のよ
うに活性領域の両脇を深い準位をつくる不純物を含んだ
半絶縁性半導体層で埋込んだ半導体レーザが開発されて
いる。
Next, in order to improve these problems, a semiconductor laser was developed in which both sides of the active region are buried with semi-insulating semiconductor layers containing impurities that create deep levels, as shown in Figure 2(b). There is.

この半導体レーザの作製例は、エレクトロニクス・レタ
ーズ(Electron、 Lett、 22巻(19
86年1214頁)に記載されている。この従来の第2
の半導体レーザにおいては、p層とn層とが高抵抗埋込
層を介しているため、従来の第1の半導体レーザに比べ
低容量で高速変調特性が大幅に改善されている。しかし
、この従来素子では、素子に印加する電圧を高くすると
、埋込み層に電流が流れ発振効率が減少する問題点があ
った。
A fabrication example of this semiconductor laser is described in Electronics Letters (Electron, Lett, Vol. 22 (19
(1986, p. 1214). This conventional second
In this semiconductor laser, since the p layer and n layer are interposed through a high-resistance buried layer, the capacitance is low and the high-speed modulation characteristics are significantly improved compared to the conventional first semiconductor laser. However, this conventional element has a problem in that when the voltage applied to the element is increased, current flows through the buried layer and the oscillation efficiency decreases.

本発明の目的は、上記の従来の問題点である埋め込み層
中の電流を殆ど零にし、高速変調特性および発振効率と
もに優れた半導体レーザを提供することである。
An object of the present invention is to reduce the current in the buried layer to almost zero, which is the problem with the conventional art, and to provide a semiconductor laser that has excellent high-speed modulation characteristics and oscillation efficiency.

(問題点を解決するための手段) 本発明は、活性領域の上側と下側を各々第1導電形クラ
ツド層と第2導電形クラツド層とで挟んだメサ状の電流
通電部と、電流通電部の両側を半導体からなる電流阻止
層で埋込んだ構造を有する埋込み構造半導体レーザにお
いて、前記活性領域と少なくとも一方の導電形の前記ク
ラッド層とに接する位置に、禁制帯幅が前記活性領域お
よびクラッド層の禁制帯幅よりも常に大きいバンドギャ
ップバリア層を前記電流通電部と前記電流阻止層の間に
設けた構造を持つことが特徴である。
(Means for Solving the Problems) The present invention provides a mesa-shaped current-carrying portion in which the upper and lower sides of an active region are sandwiched between a first conductivity type cladding layer and a second conductivity type cladding layer, and a current-carrying portion. In a buried structure semiconductor laser having a structure in which both sides of a part are buried with current blocking layers made of a semiconductor, a forbidden band width is formed in a position where the active region and the cladding layer of at least one conductivity type are in contact with the active region and the cladding layer of at least one conductivity type. It is characterized by having a structure in which a bandgap barrier layer, which is always larger than the forbidden band width of the cladding layer, is provided between the current carrying part and the current blocking layer.

第2の発明は、前記バンドギャップバリア層が互いに格
子定数の異なる膜を積層した多重膜構造を持つことが特
徴である。
A second invention is characterized in that the bandgap barrier layer has a multilayer structure in which films having different lattice constants are laminated.

(発明の作用・原理) 本発明の作用・原理について図面を参照しながら説明す
る。
(Operation/Principle of the Invention) The operation/principle of the present invention will be explained with reference to the drawings.

本発明の半導体レーザは、第1図に示したように、活性
領域11をp形りラッド層12とn形りラッド層13と
で挟んだメサ状の電流通電部を、深い不純物準位を有す
る半導体層からなる電流阻止層14で埋込み、かつ少な
くとも活性領域11およびp形りラッド層12と接する
部分の禁制帯幅が、活性領域11およびp形りラッド層
12の禁制帯幅よりもそれぞれの部分において常に大き
な電流阻止層部分15を設けた点が特徴である。16は
基板、17は電極である。これに対し、従来の第1の半
導体レーザでは、第2図(a)のように活性層11、p
形りラッド層12)n形りラッド層からなるメサ状電流
通電部をp形埋込み層21で埋め込んだ基本構造をもつ
。このとき、活性領域以外を流れるもれ電流は、印加電
圧がp形埋込^層21とn形りラッド層13に殆ど直接
印加されるため、pn接合を横切る電流23が、無視出
来ない程度になる。特にn形埋込み層22が存在する場
合、p形埋込み層21とn形りラッド層13の層構成が
npn )ランジスタ作用によりもれ電流を増幅する恐
れがあった。このため、p形埋込み層21中を2重溝の
外側へ流れる電流24を設けてpn接合への電圧印加を
緩和する工夫がなされている。しかし2重溝の外側へ流
れる電流24がもれ電流として増える問題点が従来あっ
た。また、埋込み層のpn接合容量が大きいため素子容
量を小さくできなかった。。
As shown in FIG. 1, the semiconductor laser of the present invention has a mesa-shaped current-carrying portion in which an active region 11 is sandwiched between a p-type rad layer 12 and an n-type rad layer 13, and a deep impurity level. The forbidden band width of the current blocking layer 14 made of a semiconductor layer having a semiconductor layer and at least the part in contact with the active region 11 and the p-type rad layer 12 is smaller than the forbidden band width of the active region 11 and the p-type rad layer 12, respectively. The feature is that a large current blocking layer portion 15 is always provided in the portion. 16 is a substrate, and 17 is an electrode. On the other hand, in the conventional first semiconductor laser, as shown in FIG. 2(a), the active layer 11, p
Shaped Rad Layer 12) It has a basic structure in which a mesa-shaped current carrying part made of an n-shaped rad layer is buried with a p-type buried layer 21. At this time, since the applied voltage is almost directly applied to the p-type buried layer 21 and the n-type rad layer 13, the leakage current flowing outside the active region is a non-negligible amount of current 23 that crosses the p-n junction. become. In particular, when the n-type buried layer 22 is present, the layer structure of the p-type buried layer 21 and the n-type rad layer 13 may amplify leakage current due to transistor action. For this reason, an attempt has been made to provide a current 24 flowing through the p-type buried layer 21 to the outside of the double trench to reduce the voltage applied to the pn junction. However, there has been a conventional problem that the current 24 flowing to the outside of the double groove increases as a leakage current. Furthermore, since the pn junction capacitance of the buried layer is large, the element capacitance cannot be reduced. .

第2の従来例では第2図(b)のように深い不純物準位
を有する電流阻止層14を埋め込んだ構造が形成されて
いる。この結果、電圧は電流阻止層中に順次印加される
ため、接合容量に関する問題点は大幅に改善された。し
かし第2の従来例では、電流阻止層の禁制帯幅はp型ク
ラッド層やn形りラッド層と等しく、かつ電子捕獲型の
深い不純物準位を有する半絶縁性半導体が電流阻止層と
して使われていた。、この場合、電流阻止層に用いた半
導体層単独では、極めて高抵抗であるにもかかわらず、
第2図(b)のようなレーザ構造中では全電流の105
前後のもれ電流24がある問題点が残されていた。この
もれ電流25の発生原因は、電流阻止層14のp形りラ
ッド層12と接する近傍において、不純物に捕獲された
電子の負電荷に向けてp形りラッド層12中の正孔が引
きよせられ、正孔濃度とともに電子濃度も高い領域がp
形りラッド層両脇に生じるためである。即ち正孔が不純
物に捕獲されないことから起因している。
In the second conventional example, a structure is formed in which a current blocking layer 14 having a deep impurity level is embedded as shown in FIG. 2(b). As a result, the problem of junction capacitance is significantly improved since the voltage is applied sequentially across the current blocking layers. However, in the second conventional example, the forbidden band width of the current blocking layer is equal to that of the p-type cladding layer or the n-type cladding layer, and a semi-insulating semiconductor having a deep electron-trapping impurity level is used as the current blocking layer. I was worried. In this case, although the semiconductor layer used as the current blocking layer alone has extremely high resistance,
In the laser structure as shown in Fig. 2(b), the total current is 105
The problem of front and rear leakage current 24 remained. The cause of this leakage current 25 is that holes in the p-type rad layer 12 are drawn toward the negative charges of electrons captured by impurities in the vicinity of the current blocking layer 14 in contact with the p-type rad layer 12. The region where the electron concentration is high as well as the hole concentration is p
This is because it occurs on both sides of the shaped rad layer. That is, this is due to the fact that holes are not captured by impurities.

本発明では、このもれ電流の発生原因を取除くため、p
形りラッド層12および活性領域11中の高濃度の正孔
が電流阻止層中に流入することを妨げかつn形りラッド
層13や活性領域11からの電子の流入を防ぐ層構造を
本素子に導入した。すなわち、本発明では少なくとも正
孔が流入する恐れのある領域近傍において、禁制帯幅が
P形りラッド層12や活性領域11の禁制帯幅よりも常
に大きい電流阻止層領域としてバンドギャップバリア層
15を導入した。これに加えてn型クラッド層からの電
子の流入も減少させるためn型クラッド層と接する領域
に対しても、禁制帯幅がn型のクラッド層の禁制帯幅よ
りも大きい薄膜バンドギャップバリア層15を設けると
、もれ電流を更に減少できる。このバンドギャップバリ
ア層15界面における禁制蛍輻差はわずかなものでも室
温の温度エネルギー0.025eV程度以上あれば十分
バリアとして働くため、もれ電流成分24は極めて減少
する。
In the present invention, in order to eliminate the cause of this leakage current, p
The present device has a layer structure that prevents high-concentration holes in the shaped rad layer 12 and active region 11 from flowing into the current blocking layer and prevents electrons from flowing in from the n-shaped rad layer 13 and the active region 11. It was introduced in That is, in the present invention, the bandgap barrier layer 15 is used as a current blocking layer region whose forbidden band width is always larger than the forbidden band width of the P-shaped rad layer 12 and the active region 11, at least in the vicinity of the region where holes may flow. introduced. In addition to this, in order to reduce the inflow of electrons from the n-type cladding layer, a thin bandgap barrier layer with a forbidden band width larger than that of the n-type cladding layer is also applied to the region in contact with the n-type cladding layer. 15, the leakage current can be further reduced. Even if the difference in forbidden fluorescence at the interface of the bandgap barrier layer 15 is small, if the temperature energy at room temperature is about 0.025 eV or more, it will function as a sufficient barrier, so the leakage current component 24 will be extremely reduced.

また正孔捕獲型の深い不純物準位を有する半導体を電流
阻止層14に用いた場合も、同様に捕獲されない電子が
流入する恐れのある領域近傍に、禁制帯幅のより大きな
バンドギャップバリア層15を設けてやればよい。すな
わち電流阻止層が活性領域及びn形りラッド層と接する
部分にノ、<ンドギャップバリア層を設ければ、従来に
比べてもれ電流を減少できる。更にもれ電流低域をより
効果的にするためにはそのバンドギャップバリア層15
を、p型クラッド層を含めた電流通電部の全面に設けて
やればよい。
Furthermore, when a hole-trapping type semiconductor having a deep impurity level is used for the current blocking layer 14, the bandgap barrier layer 15 with a larger forbidden band width is similarly placed near the region where uncaptured electrons may flow. All you have to do is set it up. That is, if a gap barrier layer is provided in a portion where the current blocking layer contacts the active region and the n-type rad layer, leakage current can be reduced compared to the conventional method. Furthermore, in order to make the leakage current low range more effective, the band gap barrier layer 15
may be provided over the entire surface of the current carrying part including the p-type cladding layer.

次に本発明の第2の発明の作用について説明する。埋込
み構造半導体レーザとして代表的なInGaAsP/I
nP系半導体レーザに本発明のバンドギャップバリア層
15を導入しようとするとき、クラッド層のInPより
禁制帯の大きな材料としてInGaPが考えられる。し
かし、InGaPの格子定数はGa成分が増えるにつれ
InPの格子定数より減少するため、膜成長において転
位が生じ厚膜を成長するのが難しい問題点があった。本
発明はバンドギャップバリア層構造を多層膜構造とする
ことで上記の問題点を軽減しようとするものである。す
なわち、電流通電部側にInPより広禁制帯幅で格子定
数がInPより小さなInGaP層の薄膜を形成し、引
きつづき格子定数の大きな層と小さな層を組み合せ多層
構造にすることで、転位の発生を回避することができる
。すなわち、多層構造の場合、格子不整合の歪みを隣接
層間で吸収するファクターがあるため、転位の少ない膜
成長ができる。
Next, the operation of the second aspect of the present invention will be explained. InGaAsP/I is a typical buried structure semiconductor laser.
When introducing the bandgap barrier layer 15 of the present invention into an nP-based semiconductor laser, InGaP can be considered as a material with a larger forbidden band than InP for the cladding layer. However, since the lattice constant of InGaP decreases from that of InP as the Ga content increases, dislocations occur during film growth, making it difficult to grow a thick film. The present invention attempts to alleviate the above-mentioned problems by forming the band gap barrier layer structure into a multilayer film structure. That is, by forming a thin film of InGaP with a wider forbidden band width and smaller lattice constant than InP on the current-carrying part side, and then creating a multilayer structure by combining layers with large and small lattice constants, dislocations can be generated. can be avoided. That is, in the case of a multilayer structure, there is a factor that absorbs strain due to lattice mismatch between adjacent layers, so that film growth with fewer dislocations can be achieved.

以下、本発明について実施例をあげ更に詳しく説明する
Hereinafter, the present invention will be described in more detail with reference to Examples.

(実施例1) 本発明の第1の実施例の概略構造は第1図のものと同じ
である。本実施例では先ずn形InP基板16の上にn
形InPクラッド層13、波長1.3pm組成InGa
AsP活性層11、p形InPクラッド層12を順次成
長し、通常のエツチング工程に従って深さ約2.5pm
幅10μmの溝を活性領域幅1.5μmの逆メサ状電流
通電部の両側に形成した。次いでバンドギャップバリア
層15としてInPの禁制帯幅1,35eVよりも大き
な禁制帯幅を持つInGaP層をメサ状電流通電部の側
壁に成長した。InGaPの膜厚は格子定数の不整合下
での許容できる範囲の厚さに成長した。本実施例では禁
制帯幅が1.7eVのIn。、5Gao、、sP層を成
長し膜厚は0.05pmであった。成長方法は気相成長
法を用いた。この成長方法においては、結晶面による成
長速度が異なる特性があるため、溝の側面に選択的に成
長が可能である。本実施例では逆メサ形状電流通電部の
p型りラッド層12部分に露出させた結晶面は成長速度
の大きなA面であり、一方素子表面等は成長速度の極め
て遅い(001)面であるため、InGaPのメサ側面
への選択成長が容易に行なえた。
(Embodiment 1) The schematic structure of the first embodiment of the present invention is the same as that in FIG. In this embodiment, first, an n-type InP substrate 16 is
InP type cladding layer 13, wavelength 1.3pm composition InGa
An AsP active layer 11 and a p-type InP cladding layer 12 are sequentially grown and etched to a depth of about 2.5 pm according to a normal etching process.
Grooves with a width of 10 μm were formed on both sides of an inverted mesa-shaped current carrying portion with an active region width of 1.5 μm. Next, as a band gap barrier layer 15, an InGaP layer having a forbidden band width larger than the forbidden band width of InP of 1.35 eV was grown on the side wall of the mesa-shaped current carrying part. The InGaP film was grown to a thickness within an acceptable range under lattice constant mismatch. In this example, In has a forbidden band width of 1.7 eV. , 5Gao, sP layer was grown and the film thickness was 0.05 pm. A vapor phase growth method was used as the growth method. This growth method has a characteristic that the growth rate differs depending on the crystal plane, so growth can be selectively performed on the side surfaces of the groove. In this example, the crystal plane exposed in the p-type rad layer 12 portion of the inverted mesa-shaped current carrying part is the A-plane, which has a high growth rate, while the surface of the element, etc., is the (001) plane, which has an extremely slow growth rate. Therefore, selective growth of InGaP onto the mesa side surface was easily performed.

その後、第2の従来例と同様に、電子捕獲型の深い不純
物準位を有する鉄(Fe)をドープしたInPを溝全面
に埋込み平面埋込み形の半導体レーザを作製した。
Thereafter, similarly to the second conventional example, InP doped with iron (Fe) having a deep electron-trapping impurity level was buried all over the trench to produce a planar buried type semiconductor laser.

この結果1本実施例では第3図実線31のように、もれ
電流の全電流に占める割合(もれ電流比)は、活性領域
の電流密度が2KA/cmz付近で約2%であることが
計算機シミュレーションにより示された。このもれ電流
比は第3図破線41に示す第1の従来素子のもれ電流比
見積り値約30%や、第3図−点鎖線42に示す第2の
従来素子のもれ電流比見積値約8%に比べ太幅に減少し
ており、実験でももれ電流が小さいことが確認された。
As a result 1, in this example, as shown by the solid line 31 in Figure 3, the ratio of leakage current to the total current (leakage current ratio) is approximately 2% when the current density in the active region is around 2KA/cmz. was shown by computer simulation. This leakage current ratio is approximately 30%, which is the estimated leakage current ratio of the first conventional element shown by the broken line 41 in FIG. This is a significant decrease compared to the value of about 8%, and experiments have confirmed that the leakage current is small.

なお本実施例ではInGaP層15およびInP電流阻
止層には、電子捕獲型のFe不純物をドープし、そのト
ラップ濃度はいずれも5 X 10110l5と設定し
た。また、このトラップ濃度を2 X 1015cm−
3から2×1016cm−3まで変えた場合ももれ電流
比は同様に小さかった。なおワイドギャップ電流阻止層
部分はFe以外の電子捕獲型の不純物をドープしても良
いし、アンドープでも良い。この結果本実施例では従来
に比べ高効率で発振ししかも高速変調が可能となった。
In this example, the InGaP layer 15 and the InP current blocking layer were doped with electron-trapping type Fe impurities, and the trap concentration was set to 5 x 10110l5 in both cases. Also, this trap concentration is set to 2 × 1015 cm−
When changing from 3 to 2×10 16 cm −3 , the leakage current ratio was similarly small. Note that the wide gap current blocking layer portion may be doped with an electron-trapping type impurity other than Fe, or may be undoped. As a result, in this embodiment, it is possible to oscillate with higher efficiency than in the prior art and to perform high-speed modulation.

(実施例2) 第4図は第2の実施例を示す素子概略断面図である。実
施例1とは基本構造は同じであるが、電流阻止層44の
半導体層が電子捕獲型のかわりに正孔捕獲型となってい
る。また、p形基板、およびクラッド層のp形とn形の
導電形が実施例1の場合と入替っている。正孔捕獲型の
深い不純物として本実施例ではTiをドープした。この
とき、nクラッド層13と活性領域11の(I′llI
壁にInGaP層の薄膜を成長し5、実施例1と同じく
良好な電流ブロッキング特性が得られた。また、Tiの
替わりにCoやCrをドープした場合、更にはアンドー
プの場合でももれ電流が不さいことが確認された。
(Example 2) FIG. 4 is a schematic sectional view of an element showing a second example. The basic structure is the same as that of Example 1, but the semiconductor layer of the current blocking layer 44 is of the hole trap type instead of the electron trap type. Furthermore, the p-type and n-type conductivity types of the p-type substrate and the cladding layer are switched from those in the first embodiment. In this example, Ti was doped as a hole-trapping deep impurity. At this time, (I'llI
A thin film of InGaP layer was grown on the wall 5, and as in Example 1, good current blocking properties were obtained. Furthermore, it was confirmed that the leakage current is low when Co or Cr is doped instead of Ti, and even when undoped.

なお上記実施例1及び2ではバンドギャップバリア層1
5を電流阻止層44の側壁部分に形成したが、各々p形
りラッド層及び活性層とn形りラッド居及び活性層と接
する側壁部分のみに設ければ発明の効果は充分得られる
Note that in Examples 1 and 2 above, the band gap barrier layer 1
5 is formed on the side wall portion of the current blocking layer 44, but the effects of the invention can be sufficiently obtained if they are provided only on the side wall portions in contact with the p-type rad layer and the active layer, and the n-type rad layer and the active layer, respectively.

(実施例3) 第5図は第3の実施例を示す素子概略断面図である。実
施例1とは基本構造は同じであるが、バンドギャップバ
リア層15をメサ両脇の溝全面に成長した点が異なって
いる。成長方法は有機金属気相成長(MOCVD)法を
用いた。この成長方法においては、結晶面による成長速
度依存が小さいため、溝の全面に成長が可能である。本
実施例では逆メサ形状電流通電部の溝全面に、InGa
Pの成長が容易に行なえた。その後、第2の従来例と同
様に、電子捕獲型の深い不純物準位を有する鉄(Fe)
をドープしたInPを溝全面に埋込み平面埋込み形の半
導体レーザを作製した。
(Example 3) FIG. 5 is a schematic cross-sectional view of an element showing a third example. The basic structure is the same as that of Example 1, but the difference is that the band gap barrier layer 15 is grown on the entire surface of the groove on both sides of the mesa. The growth method used was metal organic chemical vapor deposition (MOCVD). In this growth method, the dependence of the growth rate on the crystal plane is small, so growth can be performed over the entire surface of the groove. In this example, the entire groove surface of the reverse mesa-shaped current carrying part is made of InGa
The growth of P was easy. After that, similar to the second conventional example, iron (Fe) having a deep electron-trapping impurity level is
A planar buried type semiconductor laser was fabricated by filling the entire groove with InP doped with .

この結果、本実施例では第3図実線32のように、もれ
電流の全電流に占める割合(もれ電流比)は、活性領域
の電流密度が2KA/cmz付近で1%よりも小さく殆
ど零であることが計算機シミュレーションにより示され
た。このもれ電流比は第3図破線41に示す第1の従来
素子のもれ電流比見積り値約30%や、第3図−点鎖線
42に示す第2の従来素子のもれ電流比見積値約8%に
比べ太幅に減少しており、実験でももれ電流が小さいこ
とが確認された。なお本実施例ではInGaP層15お
よびInP電流阻止層には、電子捕獲型のFe不純物を
ドープし、そのトラップ濃度はいずれも5×1015c
m−3と設定した。また、このトラップ濃度を2 X 
10110l5から2 X 1016cm−3まで変え
た場合ももれ電流比は同様に小さかった。なおバンドギ
ャップ電流阻止層部分はFe以外の電子捕獲型の不純物
をドープしても良いし、アンドープでも良い。この結果
本実施例では従来に比べ高効率で発振ししかも高速変調
が可能となった。
As a result, in this example, as shown by the solid line 32 in FIG. 3, the ratio of the leakage current to the total current (leakage current ratio) is less than 1% when the current density of the active region is around 2KA/cmz. Computer simulations showed that it is zero. This leakage current ratio is approximately 30%, which is the estimated leakage current ratio of the first conventional element shown by the broken line 41 in FIG. This is a significant decrease compared to the value of about 8%, and experiments have confirmed that the leakage current is small. In this example, the InGaP layer 15 and the InP current blocking layer are doped with electron-trapping Fe impurities, and the trap concentration is 5×10 15 c.
It was set as m-3. Also, this trap concentration is 2×
When changing from 10110l5 to 2 x 1016cm-3, the leakage current ratio was similarly small. Note that the bandgap current blocking layer portion may be doped with an electron-trapping type impurity other than Fe, or may be undoped. As a result, in this embodiment, it is possible to oscillate with higher efficiency than in the prior art and to perform high-speed modulation.

(実施例4) 第6図は第4の実施例を示す素子概略断面図である。実
施例3とは基本構造は同じであるが、電流阻止層44の
半導体層が電子捕獲型のかわりに正孔捕獲型となってい
る。また、p形基板、およびクラッド層のp形とn形の
導電形が実施例1の場合と入替っている。正孔捕獲型の
深い不純物として本実施例ではTiをドープした。この
とき、nクラッド層13と活性領域11の側壁にInG
aP層の薄膜を成長し、実施例1と同じく良好な電流ブ
ロッキング特性が得られた。またTiの替りに少なくと
もCo、 Crのいずれかをドープした場合、更にはア
ンドープの場合でももれ電流が小さいことが確認された
(Example 4) FIG. 6 is a schematic sectional view of an element showing a fourth example. The basic structure is the same as that of Example 3, but the semiconductor layer of the current blocking layer 44 is of the hole trap type instead of the electron trap type. Furthermore, the p-type and n-type conductivity types of the p-type substrate and the cladding layer are switched from those in the first embodiment. In this example, Ti was doped as a hole-trapping deep impurity. At this time, InG is formed on the sidewalls of the n-cladding layer 13 and the active region 11.
A thin film of the aP layer was grown, and as in Example 1, good current blocking properties were obtained. It was also confirmed that the leakage current was small when at least one of Co and Cr was doped instead of Ti, and even when undoped.

(実施例5) 第7図は第2の発明の実施例を示す素子概略断面図であ
る。本実施例の基本構造は実施例3の基本構造(第5図
)と同じであるが、バンドギャップバリア層15が多重
膜構造71からなっている点が異なっており、特徴点で
ある。バンドギャップバリア層15材料としてInGa
P層とInP層を用いた。InGaP層はInP層と格
子不整合があるが、例えばIno、6Gao、4P組成
の場合ワイドギャップ層は約0.015μmまでの膜厚
であれば転位なし5て繰り返し積層することが可能であ
る。本実施例では成長方法として有機金属気相成長法を
用い、In。、6Gao、4P層とInP層とを0.0
111mづつ10層を交互に成長した。本実施例では、
この後p形で低濃度のInP層を電流阻止層14として
溝に埋込み平坦埋込み構造の半導体レーザを作製した。
(Embodiment 5) FIG. 7 is a schematic sectional view of an element showing an embodiment of the second invention. The basic structure of this example is the same as that of Example 3 (FIG. 5), but the difference is that the bandgap barrier layer 15 is composed of a multilayer structure 71, which is a distinctive point. InGa as the material of the band gap barrier layer 15
A P layer and an InP layer were used. Although the InGaP layer has a lattice mismatch with the InP layer, for example, in the case of Ino, 6Gao, and 4P compositions, the wide gap layer can be repeatedly stacked without dislocations 5 as long as the thickness is up to about 0.015 μm. In this example, metal organic vapor phase epitaxy is used as the growth method, and In. , 6Gao, 4P layer and InP layer are 0.0
Ten layers of 111 m each were grown alternately. In this example,
Thereafter, a p-type, low concentration InP layer was used as the current blocking layer 14 and buried in the trench to produce a semiconductor laser having a flat buried structure.

この結果、本実施例の半導体レーザのもれ電流は発振閾
電流値付近で十分小さく、かつ転位等による発振閾電流
値の劣化等が見られない良好な素子特性が得られた。ま
た、本実施例の電流阻止層14には半絶縁InP層を用
いても勿論よい。本実施例ではn形InP基板の例を示
したがp形InP基板の場合も同時に多重膜構造バリア
層15がもれ電流低域に有効であった。上記実施例1〜
5では、活性領域に波長1.3pmで発振する組成のI
nGaAsPを用いたがこの組成に限定されないのは明
らかである。
As a result, the leakage current of the semiconductor laser of this example was sufficiently small near the oscillation threshold current value, and good device characteristics were obtained in which no deterioration of the oscillation threshold current value due to dislocation or the like was observed. Furthermore, it goes without saying that a semi-insulating InP layer may be used as the current blocking layer 14 in this embodiment. In this embodiment, an example of an n-type InP substrate was shown, but the multilayer structure barrier layer 15 was also effective in reducing the leakage current in the low range in the case of a p-type InP substrate. Above Example 1~
5, the active region contains I having a composition that oscillates at a wavelength of 1.3 pm.
Although nGaAsP was used, it is clear that the composition is not limited to this.

また上記実施例では、気相成長法による選択的膜形成の
例を示したが、成長方法は気相成長法に限らずガスソー
ス分子線エピタキシャル成長などの他の成長法を用いて
もよい。
Further, in the above embodiments, an example of selective film formation by vapor phase epitaxy was shown, but the growth method is not limited to vapor phase epitaxy, and other growth methods such as gas source molecular beam epitaxial growth may be used.

更に、上記実施例では、InP基板上のInGaAsP
/InP材料系が用いられたが、GaAs基板上のAl
GaAs/GaAs材料系やAIGaInP/GaIn
P材料系についても同様に適用が可能である。
Furthermore, in the above embodiment, InGaAsP on the InP substrate
/InP material system was used, but Al on GaAs substrate
GaAs/GaAs material system and AIGaInP/GaIn
The same applies to P material systems.

(発明の効果) 本発明の半導体レーザは、従来素子に比べもれ電流を殆
ど零にでき従って高効率で発振し、かつ従来素子の改善
目的であった低容量化による高速変調も可能であり、光
通信や光情報処理の光源素子に適する。
(Effects of the Invention) The semiconductor laser of the present invention can reduce leakage current to almost zero compared to conventional elements, and therefore oscillates with high efficiency, and is also capable of high-speed modulation due to lower capacitance, which was an improvement over conventional elements. , suitable for light source elements for optical communication and optical information processing.

【図面の簡単な説明】 第1図は本発明の埋込み半導体レーザの第1の発明の素
子構造を示す斜視図、第2図(a)は第1の従来素子の
概略構造を示す断面図、第2図(b)は第2の従来素子
の概略構造を示す断面図、第3図は本発明素子、第1の
従来素子、第2の従来素子のもれ電流量と活性領域電流
密度の関係の計算機シミュレーション結果を示す図、第
4図は第2の実施例の素子(14造を示す概略断面図、
第5図は第3の実施例の素子概略断面図、第6図は第4
の実施例の素子概略断面図、第7図は第2の発明の実施
例の素子概略断面図である。 11・・・活性領域、12・・・p形りラッド層、13
・・・n形りラッド層、14・・・電流阻止層、15・
・・バンドギャップバリア層、16・・・n形基板、1
7・・・電極、21・・・p形埋込層、22・・・n形
埋込層23、24・・・第1の従来素子のもれ電流経路
、25・・・第2の従来素子のもれ電流経路、31・・
・本発明の実施例1の素子のもれ電流・電流密度関係、 32・・・本発明の実施例3の素子のもれ電流・電流密
度関係 41・・・第1の従来素子のもれ電流・電流密度関係4
2・・・第2の従来素子のもれ電流・電流密度関係、4
3・・・p型基板、44・・・正孔捕獲形の電流阻止層
71・・・多重膜構造。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing the device structure of the first invention of the embedded semiconductor laser of the present invention, FIG. 2(a) is a sectional view showing the schematic structure of the first conventional device, FIG. 2(b) is a cross-sectional view showing the schematic structure of the second conventional device, and FIG. 3 shows the amount of leakage current and active region current density of the device of the present invention, the first conventional device, and the second conventional device. 4 is a schematic cross-sectional view showing the element of the second embodiment (14 structures,
FIG. 5 is a schematic cross-sectional view of the device of the third embodiment, and FIG. 6 is the device diagram of the fourth embodiment.
FIG. 7 is a schematic sectional view of an element according to the second embodiment of the invention. 11... Active region, 12... P-type rad layer, 13
... n-shaped rad layer, 14 ... current blocking layer, 15.
... Bandgap barrier layer, 16... N-type substrate, 1
7... Electrode, 21... P-type buried layer, 22... N-type buried layer 23, 24... Leakage current path of first conventional element, 25... Second conventional element Element leakage current path, 31...
・Leakage current/current density relationship of the element of Example 1 of the present invention, 32...Leakage current/current density relationship of the element of Example 3 of the present invention 41...Leakage of the first conventional element Current/current density relationship 4
2... Leakage current/current density relationship of second conventional element, 4
3...p-type substrate, 44...hole-trapping type current blocking layer 71...multilayer structure.

Claims (2)

【特許請求の範囲】[Claims] (1)活性領域の上側と下側を各々第1導電形及び第2
導電形のクラッド層により挟んだメサ状の電流通電部と
、電流通電部の両側を半導体からなる電流阻止層で埋込
んだ構造を有する埋込み構造半導体レーザにおいて、前
記活性領域と少なくとも一方の導電形の前記クラッド層
とに接する位置に、禁制帯幅が前記活性領域およびクラ
ッド層の禁制帯幅よりも常に大きいバンドギャップバリ
ア層を前記電流通電部と前記電流阻止層の間に設けたこ
とを特徴とする埋込み構造半導体レーザ。
(1) The upper and lower sides of the active region are connected to the first conductivity type and the second conductivity type, respectively.
In a buried structure semiconductor laser having a structure in which a mesa-shaped current carrying part is sandwiched between conductive type cladding layers and a current blocking layer made of a semiconductor is buried on both sides of the current carrying part, the active region and at least one conductive type are buried. A band gap barrier layer having a forbidden band width that is always larger than the forbidden band width of the active region and the cladding layer is provided between the current carrying part and the current blocking layer at a position in contact with the cladding layer. A buried structure semiconductor laser.
(2)特許請求の範囲第1項記載のバンドギャップバリ
ア層が互いに格子定数の異なる膜を積層した多重膜構造
からなることを特徴とする埋込み構造半導体レーザ。
(2) A buried structure semiconductor laser characterized in that the bandgap barrier layer according to claim 1 has a multilayer structure in which films having different lattice constants are laminated.
JP63219361A 1988-02-02 1988-08-31 Embedded semiconductor laser Expired - Fee Related JP2780275B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2319088 1988-02-02
JP63-42758 1988-02-24
JP4275888 1988-02-24
JP63-23190 1988-02-24

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541559A (en) * 1991-08-06 1993-02-19 Nec Corp Semiconductor laser
JP2010129743A (en) * 2008-11-27 2010-06-10 Fujitsu Ltd Optical semiconductor device
JP2010206082A (en) * 2009-03-05 2010-09-16 Fujitsu Ltd Semiconductor element and method of producing the same
JP2010219102A (en) * 2009-03-13 2010-09-30 Opnext Japan Inc Semiconductor laser device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228693A (en) * 1985-04-02 1986-10-11 Fujitsu Ltd Semiconductor light emitting device
JPS61230388A (en) * 1985-04-05 1986-10-14 Fujitsu Ltd Buried type semiconductor laser
JPS6249687A (en) * 1985-08-29 1987-03-04 Fujitsu Ltd Semiconductor laser

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228693A (en) * 1985-04-02 1986-10-11 Fujitsu Ltd Semiconductor light emitting device
JPS61230388A (en) * 1985-04-05 1986-10-14 Fujitsu Ltd Buried type semiconductor laser
JPS6249687A (en) * 1985-08-29 1987-03-04 Fujitsu Ltd Semiconductor laser

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541559A (en) * 1991-08-06 1993-02-19 Nec Corp Semiconductor laser
JP2010129743A (en) * 2008-11-27 2010-06-10 Fujitsu Ltd Optical semiconductor device
JP2010206082A (en) * 2009-03-05 2010-09-16 Fujitsu Ltd Semiconductor element and method of producing the same
JP2010219102A (en) * 2009-03-13 2010-09-30 Opnext Japan Inc Semiconductor laser device
US8270446B2 (en) 2009-03-13 2012-09-18 Oclaro Japan, Inc. Semiconductor laser device

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