JPH01302390A - Image display circuit - Google Patents

Abstract

PURPOSE:To decrease the load of a host CPU by writing data to designate a display sequence from the host CPU to a data storage area beforehand, successively reading the data from a first address to a last address with a reading means, and generating a display signal. CONSTITUTION:Display sequence data to designate the display sequence to the data storage area of a memory 2 are written from a host CPU 5 beforehand. The display sequence data written to the data storage area of the memory 2 are successively read from the first address to the last address by a reading means 35, and the display signal is generated. Consequently, only by writing display instruction data to the data storage area first by means of the host CPU 5, a display control part 3 is action-controlled by the reading means 35 thereafter. Thus, the host CPU 5 can continue a main processing thereafter, and the processing load can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image display circuit, and particularly relates to an image display circuit that reduces the burden on a host/II processing device.

[Conventional technology]

As shown in FIG. 11, a conventional image display circuit 1 of this type includes a display memory 2 that stores a plurality of screen data and has an attribute area that is a data storage area that stores display instruction data; The display control section 3 generates a display signal according to display instruction data in the attribute area of the memory 2.

As shown in FIG. 12, the display memory 2 has an attribute (attribute) that stores screen (2) data, screen (2) data, screen (2) data, and display instruction data.
It is composed of A and A. The display control section 3 includes a display controller 30, buffers 31 and 32, and an arbitration circuit 33.

The display controller 30 of the display control section 3 reads screen data from the display memory 2 and forms a display signal in accordance with display instruction data written in the attribute area AA. The display controller 30 and buffer 32 in the display control section 3 are connected to the pass line 4. Said buffer 31 and buffer 32
is connected to the display memory 2, and is connected to the arbitration circuit 3.
3, the display memory 2 is connected to the pass line 4 via the buffer 32 and to the display controller 30 via the buffer 3I.

The pass line 4 includes a host arithmetic processing unit (CPU).
5 and a main memory 6 are connected.

In such an image display circuit 1, the display controller 30 of the display control section 3 reads the contents of the attribute area AA of the display memory 2 every time a vertical synchronization signal is output.
Screen data according to the display instruction data written in the attribute area AA is read out from the display memory 2 to generate a display signal.

Here, when attempting to change the display screen, the CPU 5 causes the display controller 30 to attribute display instruction data of the screen data to be displayed in the attribute area AA of the display memory 2 in synchronization with the vertical synchronization signal.
It is necessary to write to area AA before reading it. 13th
The figure is a time chart shown to explain the operation of the image display circuit I.

When the vertical synchronization signal is output at time L1, the display controller 30 reads the attribute area AA at time t2, and displays screen 2 on the display screen according to the display instruction data of the attribute area AA at time t. Also, when the vertical synchronization signal is output at time t4, the time is also displayed on the controller 30.
reads the attribute area AA, and at time t6 displays the screen ■ on the display screen according to the display instruction data of the attribute area AA.

Next, at the clock time, the CPU 5 writes display instruction data in the attribute area AA so as to display the screen 2 in synchronization with the vertical synchronization signal. At this time, display controller 3
0 has already displayed the screen ■ at time t, so it does not change even if there is writing in the attribute area I area AA.

Furthermore, when a vertical synchronization signal is output at the time, the content is displayed in the attribute H area AA at the time controller 30.
is read and the display instruction data is on the screen ■, so the time is also. The screen ■ will be displayed. During this display,
At time tll, the CPU 5 writes the contents of the attribute area AA so that the screen ■ is displayed.

Then, when the vertical synchronization signal is output at time tit, time t
At time t13, the display controller 30 reads the contents into the attribute area AA, and since the display instruction data is the screen ■, the screen ■ will be displayed at time t14.

As described above, in the conventional image display circuit 1, when changing the display signal output from the display controller 30, the host CPU 5 needs to rewrite the display instruction data written in the attribute area AA one by one.

(Problems to be Solved by the Invention) In the case of the conventional image display circuit 1, when changing the display screen, the host CPU 5 needs to rewrite the contents of the attribute area AA one by one. etc., the host CPU 5 must execute both display switching processing and main processing.
The disadvantage is that the processing load increases. Furthermore, in the case of the image display circuit 1, if the interrupt processing is masked and heavy processing is performed during the main processing of the host CPU 5, the screen cannot be switched in a desired state.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide an image display circuit that reduces the burden on a host CPU.

[Means to solve the problem]

In order to achieve the above object, an image display circuit according to the present invention includes a memory that stores screen data and has a data storage area that stores display instruction data; and a display side unit 210 that generates a display signal using a display unit, wherein display order data specifying a display order is stored in a data storage area of the memory, and the display control unit stores display order data that specifies a display order in a data storage area of the memory, and the display control unit The present invention is characterized in that it is provided with reading means for sequentially reading out the display order data written in the storage area from the first address to the last address.

Further, another image display circuit of the present invention includes a memory having a data storage area for storing screen data and display instruction data, and a display signal in response to the display instruction data in the data storage area of the memory. an image display circuit comprising: a display control unit that generates display order data that specifies a display order in a data storage area of the memory; The present invention is characterized in that it is provided with reading means for sequentially reading display order data from a predetermined address to a predetermined address larger than this address.

In addition, still another image display circuit of the present invention includes a memory that stores screen data and has a data storage area that stores display instruction data, and that displays data according to the display instruction data in the data storage area of the memory. an image display circuit comprising: a display control unit that generates a control signal; display order data that specifies a display order is stored in a data storage S area of the memory; reading means for sequentially reading display control data written in the area from a predetermined address to a predetermined address larger than this address; and a display number for determining the number of times a display signal is displayed based on the display control data read by the reading means. The present invention is characterized by comprising a specifying means.

The display count designating means used in still another image display circuit of the invention may include a memory that stores display count data.

[Effect]

The first image display circuit writes display order data specifying a display order into the data storage area of the memory from the host 1-CPU in advance, and reads the display written into the data storage area of the memory by the reading means. The sequential data is sequentially read from the first address to the last address to form a display signal. As a result, the host CPU only needs to first write the display instruction data in the data storage area, and then the reading means controls the operation of the display control section. Therefore, the host CPU can continue the main processing from now on.

The second image display circuit writes display order data specifying a display order into the data storage area of the memory from the host CPU in advance, and also sends a reading start address and a reading end address to the reading means from the host CPU. The display order data written in the data storage area of the memory is read in advance by the reading means from the reading start address to the reading end address to form a display signal. In this case, all that is required is to first write the display instruction data to the data storage area and the read start address and read end address to the read means, and then the read means will control the operation of the display control unit. The CPU can then continue with the main processing.

The third image display circuit writes display order data specifying a display order in the data storage area of the memory in advance from the host CPU, and also sends a read start address and a read end address to the read means from the host CPU. This is written in advance, and data on the number of times of display is also stored in the memory. Then, the display order data written in the data storage area of the memory is sequentially read out by the reading means from the reading start address to the reading end address to form a display signal. At this time, the number of times each display signal is displayed is controlled by the display number specifying means. This allows the host CPU
In this case, all that is required is to first write the display instruction data in the data storage area, the read start address and read end address in the read means, and the number of display times in the memory, and then the display control section is controlled by the read means. become. Therefore, the host CPU can continue the main processing from now on.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In the following description, the same components as those of the image display circuit shown in FIG. 11 are given the same reference numerals, and the description thereof will be omitted.

FIG. 1 is a block diagram showing a first embodiment of an image display circuit according to the present invention. FIG. 2 is an explanatory diagram showing a memory map of the display memory used in the second embodiment. FIG. 3 is a time chart shown to explain the operation of the second embodiment.

The first embodiment of the image display circuit shown in FIG. 1 differs from the circuit shown in FIG.
), the data of a plurality of screens is stored, and the display order is specified in the attribute area A, which is the data storage area of the display memory 2, as shown in FIG. 2(B). The display control unit 3 stores the display control data written in the attribute area A of the display memory 2 at the first address (000
FI) to last (7) 7 F reply ((n-1) 100
The point is that a reading means 35 is provided for sequentially reading up to HI,
Other configurations remain unchanged.

This reading means 35 includes an address adder 351 and a buffer 3 between the display controller 30 and the buffer 31.
52 and the address adder 3.
51, and an n-ary counter 354 that counts the vertical synchronizing signal VD from the display controller 30 and provides count data as the counting result to the multiplier 353. Further, the address adder 351 is a circuit that operates only when the display controller 30 reads the attribute area A, and simply passes through at other times.

The operation of the first embodiment configured in this way will be explained.

First, it is assumed that the circuit elements of each part are in an initial state. Here, when the display controller 3o outputs the vertical synchronizing signal VD at time 121 as shown in FIG.
At step 21, the karashito value (0) is given to the multiplier 353 as shown in FIG. 3(e). The multiplier 353 is
As shown in FIG. 3(r), the multiplication output (0O
OH) is output. As a result, the display controller 30 via the multiplier 353 at time i, 22 (see FIG. 2)
-B) reads the address (0008 to 0FFH) into the attribute area of the display memory 2. Since the display order data instructs to display the screen A display signal is formed from the data on the screen 2 of the display memory 2 in A), and the screen 2 is displayed from the time screen 23 as shown in FIG. 3(c).

When the display controller 30 outputs the vertical synchronizing signal VD again at time t24 as shown in FIG. 3(a), the n-ary counter 354 of the reading means 35 counts and
At step 24, the count value [1] is given to the multiplier 353 as shown in FIG. 3(e). The multiplier 353 is
As shown in FIG. 3(f), the multiplication output (10
0H) is output.

As a result, the display controller 3
0 is the address (1008 to IFFH) of the attribute area A of the display memory 2 in FIG. 2(B) at time t25.
), the display order data instructs to display screen ■, so the display controller 3
0 forms a display signal from the data on the screen ■ of the display memory 2 in FIG. 2(A), and displays the screen ■ from time t26 as shown in FIG. 3(c).

Further, when the display controller 30 outputs the vertical synchronizing signal VD at time t27 as shown in FIG. 3(a), the n-ary counter 354 of the reading means 35 counts and
At step 27, the count value [2] is given to the multiplier 353 as shown in FIG. 3(e). The multiplier 353 is
As shown in FIG. 3(f), at time t27, the multiplication output (2
00H) is output. As a result, the display controller 30 operates via the multiplier 353 at time t28 as shown in FIG.
B) Read the address (20011 to 2FFH) of the attribute area A of the display memory 2. As a result, since the display order data instructs to display the screen ■, the display controller 30 forms a display signal from the data of the screen ■ in the display memory 2 of FIG. As shown in Figure (c), the screen ■ is displayed from time t29.

Operating in this way, the n-ary counter 354 sequentially displays the screen according to the counter output value.

Furthermore, when the display controller 30 outputs the vertical synchronization signal VD at time t3n as shown in FIG. 3(a),
The n-ary counter 354 of the reading means 35 counts, and provides the count value [n-1] to the multiplier 353 at time t3n, as shown in FIG. 3(e). The multiplier 35
3 outputs the multiplication output [(n-1) $100H) at time t3n, as shown in FIG. 3(f). This results in
The display controller 30 uses the multiplier 353 at time t3.
At n+1, the address of the attribute right page area A of the display memory 2 in FIG. 2(B) ((n-1) 100H to n
*100B-1) is read. As a result, since the display order data instructs to display the screen ■, the display controller 30 forms a display signal from the data of the screen ■ in the display memory 2 of FIG. As shown in Figure (c), the screen ■ is displayed from time t3n+2.

This first embodiment operates as described above.

Then, once the host CPU 5 writes data into the attribute area A of the display memory 2, the reading means 35
operates to perform display, so the host CPU 5 can perform other processing.

FIG. 4 is a block diagram showing a second embodiment of the image display circuit according to the present invention. FIG. 5 is an explanatory diagram showing a memory map of the display memory used in the second embodiment. FIG. 6 is a time chart shown to explain the operation of the second embodiment.

The second embodiment differs from the first embodiment in that the display control unit 3 transfers the display control data written in the attribute area A of the display memory 2 from a predetermined address to a predetermined address larger than the predetermined address. The only difference is that a reading means 35A is provided for sequentially reading up to the addresses of , and there is no other change in the configuration.

That is, the reading means 35A reads the n-ary counter 354.
Let A be in a format that allows the value of the start of counting to be set, and its n
The output of the decimal counter 354A is sent to the multiplier 353 and the comparator 35.
5 and compares it with the reference data (counting end value, predetermined end address) from the latch circuit 356 in the comparator 355, and if a match is detected in the comparator 355, it connects to the load terminal of the n-ary counter 354A. Latch circuit 3
56 to set a counting start value in the n-ary counter 354A, a start register 357 that causes the latch circuit 356 to latch counting end data, and provides the n-ary counter 354A with a count start value; An end register 358 that provides reference data to the circuit 356 is connected to the pass line 4, and the CPU 5
It is configured to be more readable and writable. Also, the fifth
The contents of the display memory 2 in the figure are unchanged from those in FIG. 2.

The operation of the second embodiment configured in this way will be explained.

First, the host CPU 5 starts the start register 357.
The counting start value (predetermined starting address) is stored in end register 3.
Count end values (predetermined end addresses, reference data) are set in 58, respectively. Then, n-ary counter 3
The counting start value is set in 54A. here,
It is assumed that the count start value written in the start register 357 and set in the n-ary counter 354A is (1). Also written to the end register 358,
The latched count end value of the launch circuit 356 is (3)
shall be.

In this state, the display controller 30 outputs the vertical synchronizing signal VD at time t51 as shown in FIG. 6(a).
is output, the n-ary counter 35 of the reading means 35
4A counts and provides the count value [1] to the multiplier 353 at time t5] as shown in FIG. 6(e).

The multiplier 353 operates at time t as shown in FIG. 3(f).
At step 51, the multiplication output (100u) is output. This results in
The display controller 30 uses the multiplier 353 at time t5.
2, the addresses (10011 to IFFI+) to the attribute area of the display memory 2 shown in FIG. 5(B) are read.

As a result, since the display order data instructs to display the screen
A display signal is formed from the data on the screen ■ of the display memory 2 in A), and the screen ■ is displayed from time t53 as shown in FIG. 6(C).

When the display controller 30 outputs the vertical synchronizing signal VD again at time t54 as shown in FIG. 6(a), the n-ary counter 354A of the reading means 35 counts, ), the count value [2] is given to the multiplier 353. The multiplier 353 generates a multiplication output (2) at time t54 as shown in FIG.
00H) is output. As a result, the display controller 30 operates via the multiplier 353 at time t55 as shown in FIG.
B) Read the address (200H to 2FFH) of the attribute area A of the display memory 2. As a result, since the display order data instructs to display the screen ■, the display controller 30 forms a display signal from the data of the screen ■ in the display memory 2 of FIG. figure(
As shown in c), the screen ■ is displayed from time t26.

Further, when the display controller 30 outputs the vertical synchronizing signal VD at time t57 as shown in FIG. 3(a), the n-ary counter 354A of the reading means 35 counts, ), the count value [3] is given to the multiplier 353. As shown in FIG. 3(f), the multiplier 353 produces a multiplication output (
3008) is output. As a result, the display controller 30 reads the address (300H to 3FFll) into the attribute area of the display memory 2 in FIG. 5(B) at time t5B via the multiplier 353. This results in
Since the display order data instructs to display the screen ■, the display controller 30 forms a display signal from the data of the screen ■ in the display memory 2 in FIG.
As shown in Figure (c), the screen ■ is displayed from time t59. At this time, the comparator 355 detects that the count data [3] of the n-ary counter 354A matches the count end value [3], and the output is sent to the n-ary counter 354A.
and the launch circuit 356. As a result, the n-ary counter 354A again changes the counting start value to [0].
], and the latch circuit 356 also receives the counting end value [3
] will be set.

In this way, the n-ary counter 354A starts counting from the beginning again. This second embodiment operates as described above. Then, the host CPU 5
Once written to the attribute 9M area A of the display memory 2, and also written the count start value to the start register 357 and the count end value to the end register 358, the reading means 35 operates from then on to execute the display. , the host CPU 5 can execute other processes. In addition, this second embodiment also uses the display start address (
address) and display end address (address) can be arbitrarily set.

FIG. 7 is a block diagram showing a third embodiment of the image display circuit according to the present invention. FIGS. 8 and 9 are explanatory diagrams showing memory maps of the display memory used in the second embodiment. FIG. 10 is a time chart shown to explain the operation of the second embodiment.

The third embodiment differs from the second embodiment in that the display control unit 3 transfers the display control data written in the attribute area A of the display memory 2 from a predetermined address to a predetermined address larger than the predetermined address. The present invention is provided with a readout means 35A for sequentially reading up to the addresses of , and a display number designation means 36 for designating the number of times the display signal is displayed based on the display order data read by the readout means 35A, and there are no other changes in the configuration. .

The display number specifying means 36 includes an n-ary counter 361;
It is composed of a display number latch 362 and a comparator 363 that matches the output from the n-ary counter 361 with the output from the display number lunch 362. The display count designating means 36 is an n-ary counter 361 that simply counts the vertical synchronization number J3 VD from the display controller 30.
The count value output from and the display count latch 362
A comparator 363 compares the display count data from the n-base counter 354A with the display count data from the n-base counter 354A, and resets the n-base counter 361 when they match. The address of the launch 362 is configured to be controlled. In this way, the reading means 35A does not count up until the screen has been displayed a predetermined number of times from the display number specifying means 36, so the display controller 30 outputs the same screen for the specified number of times. will be done. The display memory shown in FIG. 8 is the same as that shown in FIG. Further, the display count latch 362 is as shown in FIG.

The operation of the third embodiment configured in this way will be explained.

First, the host CPU 5 starts the start register 357.
The counting start value (predetermined starting address) is stored in end register 3.
Count end values (predetermined end addresses, reference data) are set in 58, respectively. Further, the host CPU 5 sets the display count data in the display count latch 362. Then, the counting start value is set in the n-ary counter 354A. Here, the start register 35
It is assumed that the count start value written in the number 7 and set in the n-ary counter 354A is [1].

Further, it is assumed that the count end value written to the end register 358 and latched by the launch circuit 356 is [3].

First, it is assumed that the circuit elements of each part are in an initial state. Here, when the display controller 30 outputs the vertical synchronization signal VD at time t81 as shown in FIG. 10(a),
The n-ary counter 361 counts up. At this time, since the display count data [1] at the address (0) in FIG. 9 is given from the display count latch 362 in FIG. 9 to the comparator 363, the output from the n-ary counter 361 and the display count are The display count data [1] from the latch 362 matches, the n-ary counter 361 is cleared, and
The n-ary counter 354A is counted and amplified. As a result, the n-ary counter 354A supplies its count value [1] to the multiplier 353 at time 181 as shown in FIG.
Address (1) is given to , as shown in Figure 1O (g). As a result, the display count data [2] is output from the display count latch 362 to the comparator 3, as can be seen from FIG.
It is given to 63. Further, the multiplier 353 has a first
As shown in Figure 0Cf), at time t81, the multiplication output (100
H) is output. As a result, the display controller 30 via the multiplier 353 operates as shown in FIG. 8(B) at time t82.
Address (1) of attribute area A of display memory 2 of
00H to IFFH). As a result, since the display order data instructs to display the screen ■, the display controller 30 forms a display signal from the data of the screen ■ in the display memory 2 of FIG. Figure (c
), the screen ■ is displayed from time t83.

When the display controller 30 outputs the vertical synchronizing signal VD again at time t84 as shown in FIG. 10(a),
The n-ary counter 361 counts up, and the output of the n-ary counter 361 outputs [1]. However, since the display count data from the display count latch 362 supplied to the comparator 363 is [2], there is no match signal from the comparator 363. Therefore, the output of the n-ary counter 354A is [1]. Therefore, at time 184, the count value [1] is given to the multiplier 353 as shown in FIG. 10(e).

The multiplier 353 operates at time L as shown in FIG. 3(r).
At 84, the multiplication output (100H) is output. This results in
The display controller 30 via the multiplier 353 at time t8
5, reads the address (100H to IFFH) of the attribute area A of the display memory 2 in FIG. , a display signal is formed from the data on the screen ■ of the display memory 2 in FIG. 8(A), and the screen ■ is displayed from time t86 as shown in FIG. 3(c).

Further, when the display controller 30 outputs the vertical synchronizing signal VD at time t88 as shown in FIG. 10(a), the n-ary counter 361 counts up. At this time, since the display count data [2] of address (1) is given to the comparator 363 from the display count latch 362 in FIG. The display count data [2] from the latch 362 reaches -, the n-ary counter 361 is cleared, and
The n-ary counter 354A counts up.

As a result, the n-ary counter 354A is set at time t87.
When the count value [2] is given to the multiplier 353 as shown in FIG. 10(e), the display count latch 362 receives the address (2) as shown in FIG. 10(g).
give. As a result, the display count data [1] is applied from the display count latch 362 to the comparator 363, as can be seen from FIG. Furthermore, the multiplier 353
outputs the multiplication output [2008] at time i1J t 87 as shown in FIG. 10(f). As a result, the display controller 30 reads the address (2008-2FF) I) of the attribute area A of the display memory 2 in FIG. 8(B) at time t88 via the multiplier 353. As a result, since the display order data instructs to display the screen
) A display signal is formed from the data on the screen (2) in the display memory 2, and the screen (2) is displayed from time t89 as shown in FIG. 10(c).

In addition, when the display controller 30 outputs the vertical synchronizing signal VD at time t90 as shown in FIG. 10(a), the n-ary counter 361 counts up. At this time, since the display count data [1] at address (2) is given to the comparator 363 from the display count latch 362 in FIG. The display count data [1] from the latch 362 reaches -, and the n-ary counter 361 is cleared, and
The n-ary counter 354A counts up.

As a result, the n-ary counter 354A is set at time t90.
As shown in FIG. 10(e), the count value [
3] is applied to the multiplier 353, an address (3) is applied to the display count latch 362 as shown in FIG. 10(g). As a result, from the display count latch 362,
As can be seen from FIG. 9, the display count data [1] is applied to the comparator 363. Further, the multiplier 353 outputs the multiplication output (
300H) is output. As a result, the display controller 30 reads the address (300H to 3FFH) of the attribute nod HA in the display memory 2 in FIG. Since the display is instructed to be displayed, the display controller 3o forms a display signal from the data on the screen 2 of the display memory 2 in FIG.
As shown in Figure (c), the screen ■ is displayed from time t92.

In this manner, a display signal is output based on the display number data set in the display number latch 362 by the display number specifying means 36, and the display is performed a predetermined number of times. Further, the n-ary counter 354 will display the screen sequentially according to the counter output value.

This third embodiment operates as described above.

Once the host CPU 5 writes the display order data into the attribute area A of the display memory 2 and the display number data into the display number latch 362, the reading means 35A and the display number specifying means 36 operate from then on. Since the display is executed, the host CPU 5 can execute other processing.

〔Effect of the invention〕

As described above, the first image display circuit according to the present invention is
Display order data specifying the display order is written in advance from the host CPU to the data storage area of the memory, and the reading means reads the display order data written to the data storage area of the memory from the first address to the last address. Since the display signal is formed by reading addresses sequentially, the load on the host CPU is reduced, and the screen can be switched reliably, making it very effective for video display and time-division stereoscopic display. It is.

Further, in the second image display circuit according to the present invention, display order data specifying a display order is written in advance from the host CPU to the data storage area of the memory, and the read-out start address and read-out end address are written in the read means in advance. host CPU address
Since the display order data written in the data storage area of the memory is read in advance from the readout start address to the readout end address by the readout means to form the display signal, the host CPU This reduces the burden and is very effective for video display and time-division stereoscopic display. Further, according to the present invention, there is an effect that the range from a predetermined start screen to a predetermined end screen can be set arbitrarily.

Further, in the third image display circuit according to the present invention, display order data specifying the display order is written in advance from the host CPU to the data storage area of the memory, and the readout start address and readout are written in the readout means. Enter the ending address in the host CP
tJ in advance, display count data is written in the display count specifying means 36, and the reading means reads the display order data written in the data storage area of the memory from the read start address to the read end address. Since the display signals are read out sequentially and the number of times the display screen is displayed is controlled by the display number specifying means 36, the load on the host CPU can be reduced.
(and host), the screen can be switched reliably regardless of the weight of the CPU's main processing, and is very effective for displaying moving images and time-division stereoscopic display. Further, according to the present invention,
This has the advantage that it is possible to arbitrarily set the range from a predetermined start screen to a predetermined end screen, and it is also possible to specify the number of times the display screen is displayed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the memory map used in the second embodiment, FIG. 3 is a time chart shown to explain the operation of the second embodiment, and FIG. 4 is a diagram showing the second embodiment of the present invention. 5 is an explanatory diagram of a memory map used in the second embodiment, FIG. 6 is a time chart shown to explain the operation of the second embodiment, and FIG. 7 is a third embodiment of the present invention. FIG. 8 and FIG. 9 are explanatory diagrams of memory maps used in the third embodiment, and FIG. 1O is a time chart shown to explain the operation of the third embodiment.
FIG. 11 is a block diagram showing a conventional example, FIG. 12 is an explanatory diagram of a memory map used in the conventional example, and FIG. 13 is a time chart shown to explain the operation of the conventional example. l...Image display circuit, 2...Display memory, 3...
Display control unit, 35.35A... Reading means, 36...
Display count specification means. Agent Patent Attorney Tomo Murakami - Figure 1 Figure 5 (A) Figure 6 ts+ tb4 f5. tb. Figure 11 Figure 13

Claims (4)

[Claims] (1) A memory that stores screen data and has a data storage area that stores display instruction data, and a display control unit that generates a display signal according to the display instruction data in the data storage area of the memory. In the image display circuit, display order data specifying a display order is stored in a data storage area of the memory, and the display control unit stores display order data written in the data storage area of the memory from the first address to the last address. An image display circuit characterized in that it is provided with a reading means for sequentially reading up to an address. (2) A memory that stores screen data and has a data storage area that stores display instruction data, and a display control unit that generates a display signal in accordance with the display instruction data in the data storage area of the memory. In the image display circuit, display order data specifying a display order is stored in a data storage area of the memory, and the display control unit stores display order data written in the data storage area of the memory from a predetermined address to this address. An image display circuit characterized in that it is provided with reading means for sequentially reading up to a larger predetermined address. (3) A memory that stores screen data and has a data storage area that stores display instruction data, and a display control unit that generates a display signal in accordance with the display instruction data in the data storage area of the memory. In the image display circuit, display order data specifying a display order is stored in a data storage area of the memory, and the display control unit reads the display control data written in the control data storage area of the memory from a predetermined address. 1. An image display circuit comprising: reading means for sequentially reading data up to a predetermined address larger than the address; and display number specifying means for specifying the number of times a display signal is displayed based on the display control data read by the reading means. (4) The image display circuit according to claim 3, wherein the display count designating means includes a memory that stores data on the display count.