JPH01296489A - Sense amplifier - Google Patents

Abstract

PURPOSE:To improve a responding speed by providing a second inverter, whose threshold value is higher than a first inverter, controlling the gate of a transistor to correspond to the respective inverters and charging a digit line. CONSTITUTION:In a sense amplifier 11, an inverter INV3, whose threshold value is higher than an inverter INV1, is provided in addition to the inverter INV1 to be connected to an input point B. Then, a transistor N1 to be controlled by the inverter INV1 is turned on at an early time point in comparison with a transistor N3, which is controlled by the inverter INV3, and turned off at a late time point and the charge of the digit line is executed. Accordingly, during this charge, the transistor N3 is turned on only during a period for the charge of digit parasitic capacity and a charging current is increased. Thus, a charging time is shortened and the responding speed of the sense amplifier is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier that amplifies signals from memory cells, and particularly to a sense amplifier that can improve response speed.

[Prior Art] A circuit shown in FIG. 4 is conventionally known as a sense amplifier that amplifies a weak signal from a memory cell.

The sense amplifier 1 includes selectors Y1 . . . of memory cells M, . The signal of the cell selected by Y2 is input at point B, and its amplified output is output to the output buffer circuit 2. The input signal input through point B is inverted by an inverter INV, and its inverted output V is input to the gate of an N-channel transistor N1. The transistor N1 has a source connected to the point B, and a train connected to a power supply via a P-channel transistor P1 for load. P-channel type one-heran sister P
2 constitutes a pair of current mirrors with the transistor P1. An N-channel transistor N2 whose gate receives a reference voltage V ref is connected between the drain of the transistor P2 and the ground. Transistor P
2. The connection point of N2 is connected to the output end via the inverter ■N■2.

The sense amplifier 1 configured as described above operates as follows. That is, if point B is at the ``0'' level,
Since the output f of the inverter INV becomes high level, the 1-run transistor N1 becomes conductive, and a large current flows through the load transistor P. This power supply is also transmitted to the run transistors P1 to P2 forming a pair of current mirrors. Inverter ■NV2 compares the currents of transistor P2 and transistor N2, and in this case, since the current of transistor P2 is larger, it outputs 'O' level as output take O. On the other hand, point B is '1' ” level, the inverter I NV.

Since the output (2) becomes low level, the transistor N acts in the direction of being cut off, and the current flowing through the load transistors 1 to P2 decreases. Therefore, the current of the transistor P2 also decreases, and the output voltage of the inverter 1N2 is "'1".
Becomes Rubel.

By the way, normally, memory cells M, , M2's desiccilla 1 to
A large parasitic window fLcD+, Co2 exists in the line. This parasitic window fjkco1. CD2 becomes a larger value as the degree of memory integration increases. The influence of this parasitic capacitance will be explained below using FIG. 5. Figure 5 shows
Selection signal V5□ is "l"→゛0', selection signal V5
2 changes from 0"°→Pa]", and the selector changes from ¥1 to Y.
It shows the voltage of each part at the moment when it switches to 2. As the output of memory cell M2, the voltage at point B should originally be input to point B. Due to the influence of parasitic capacitance CD2, the potential at point B temporarily decreases immediately after switching, and due to the charging of CD2, It gradually recovers to its original level.When the level at point B drops once, the output of the inverter INV increases once, and the transistor N becomes conductive, increasing the parasitic capacitance CD2 between the load transistor P1 and the transistor P1. The current continues to flow until charging is completed.In response to this current, the output O of the sense amplifier circuit 1 changes from ``1'' level to ``0'' level.
It falls to the "1" level and returns to the true output level "1" only after the charging of the parasitic capacitance CD2 is completed and the output f of the inverter INV becomes stable (t in the figure).
+, td).

[Problems to be Solved by the Invention] As described above, the response time td of the sense amplifier is determined by the charging time of the parasitic capacitance of the digit line. Therefore, in order to improve the response speed, it is necessary to charge the parasitic capacitance faster. In order to speed up the charging time of the parasitic capacitance, it is better to increase the value of the current flowing through the load transistor P1. For this purpose, for example, the mutual contactance g of the load MOS transistor P1 must be determined. It is possible to increase the

However, if the mutual conductance gm of the load MOS transistor P1 is increased, there is a problem in that the capacitance of the transistor transistor 1 itself at point A increases. For this reason, conventionally it has not been possible to effectively improve the charging time.

At present, as the capacity of semiconductor devices increases, their parasitic capacitance tends to increase, and further improvement in response speed is desired.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a sense amplifier that can effectively increase response speed.

[Means for Solving the Problems] A sense amplifier according to the present invention includes a first inverter that inputs a signal from a memory cell and outputs an inverted signal, and a source that inputs the output of the first inverter to gates 1 to 1. A sense amplifier comprising a first transistor of a first conductivity type connected to the input of the first inverter, and a first load connected between the drain of the first transistor and a power supply, a second inverter having an input having a threshold lower than that of the first inverter or connected to the input of the first inverter; and a second transistor of the first conductivity type connected to the input of the inverter and the train connected to the power supply directly or via a second load.

[Function 6] According to the present invention, a first and a second inverter are provided, and the signal from the memory cell is input to these two inverters respectively, or the second inverter is inputted to the first inverter. Since the threshold value is also small, the first. Each output of the second inverter ■, 1°Vf2 is always ■, l) V
(There is a relationship of 2. Therefore, the first N-channel transistor with f1 as the gate input is always turned on before the second transistor with 2 as the gate input with ■) Therefore, the second transistor is turned on and supplies the charging current only when, after the selector has been switched, the potential on the Tidgit line has dropped significantly and more charging current is required. It acts to increase.

Further, since the second one-heran transistor is turned on later than the first transistor and turned off first, it does not cause any trouble to normal operation. As a result, according to the present invention, the second transistor operates differentially only during the charging period of the parasitic capacitance when switching the selector, thereby shortening the charging time, thereby making it possible to speed up the response time.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a sense amplifier according to an embodiment of the present invention. In addition, in FIG. 1, the same parts as in FIG. 4 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

Sense amplifier of this embodiment] 1 or sense amplifier 1 of Fig. 4
The difference is that an inverter I NV3, a P-channel load transistor P3, and an N-channel transistor N3 are newly added. Inverter I
NV3 (second inverter) is an inverter INV, (
Like the first inverter), the input is connected to point B, which is the input end of the sense amplifier 11, and its inverted output V(2) is connected to the gate of the one-heran transistor N3.

The threshold value V7H2 of this inverter INV3 is set smaller than the threshold value VTI11 of the inverter INVI.

The source of the transistor N3 is connected to the above-mentioned point B, and the train is connected to the train of the transistor P3. The transistors 1 to P3 are connected to the source or power supply, and are connected to the gate or drain.

This circuit constituted by the inverter IN3 and the transistor P3°N is a circuit that operates only when charging the parasitic capacitances CD, . The operation of this sense amplifier 11 will be explained below with reference to FIG. In addition, FIG. 2 shows the selection signal ■s1
is Pa1''→Pa0''', selection signal V32 is 'O'''→''
1" and shows the voltage at each part at the moment when the selector switches from Yl to ¥2. Immediately after switching, when point B, which should originally maintain a high level, drops once, the inverter INV+, INV3 output V ((, V +
2 will rise respectively. Here, inverter I NVl, I
Each threshold value v'ro□, VTI+□ of NV3 is ■□H
Since the relationship is set to be 1>V Tl-12, the potentials of the outputs V() and V(2 always have the relationship V(2<Vr+) as shown in the figure.

The outputs V (
H.

Due to the change in V(2, transistors N, , N3 turn on, respectively, and quickly charge the parasitic capacitance Cn2. In response to this charging current, the output ○ of the sense amplifier 11 changes from the P1' level to "0" once -) However, since the parasitic capacitance is charged by the two transistors N1 and N3, the potential at point B quickly reaches a stable state and returns to the true output "1'" level.

However, since the threshold value VT)+2 of the inverter NV3 is lower than the threshold value VTHI of the inverter INV, the transistor N3 is turned on for the duration t2 only when the point B is significantly lowered. Moreover, it is turned off before the point B becomes stable, and normal circuit operation is not affected at all. In other words, it is turned on only when charging the parasitic capacitance 1C92, and turned off when charging is completed.

This shortens the time required to charge the parasitic capacitance, resulting in a faster sense amplifier.

FIG. 3 shows a sense amplifier according to another embodiment of the invention. This sense amplifier 21 is the sense amplifier shown in FIG.
Remove transistor P3 in , and replace transistor N3 with
The train is directly connected to the power source.

The operating principle is the same as that of the first embodiment, but by configuring it in this way, the charging time for the parasitic capacitance of the digit line can be further shortened by the reduction in the load on the transistor N3. , the speed of the sense amplifier can be further increased.

In addition, the transistor P3 in the circuit of FIG.
Instead, a resistor with an appropriate resistance value may be inserted as a load.

[Effects of the Invention] As explained below, the sense amplifier of the present invention has the first effect.
A second inverter with a threshold value smaller than that of the inverter and a second transistor driven by this inverter are provided, and this second transistor is made conductive only during the charging period of the parasitic capacitance of the Tigit line, so that the parasitic The charging current when charging the capacitor can be increased, and the response speed of the sense amplifier can be effectively improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a sense amplifier according to an embodiment of the present invention,
Fig. 2 is an operating waveform diagram of the sense amplifier, Fig. 3 is a circuit diagram of a sense amplifier according to another embodiment of the present invention, Fig. 4 is a circuit diagram of a conventional sense amplifier, and Fig. 5 is a circuit diagram of the sense amplifier according to another embodiment of the present invention. FIG. 3 is an operational waveform diagram of the amplifier. 1.11.21: Sense amplifier, 2: Output buffer circuit, M, , M2: Memory cell, Y, , Y, 2: Selector,
CD1. CD2; Parasitic capacitance, N, ~N3°P1~P3;
l ~ transistor, I NV, ~T NV3: inverter

Claims (1)

[Claims] (1) The first part inputs the signal from the memory cell and outputs the inverted signal.
an inverter, a first transistor of a first conductivity type whose gate receives the output of the first inverter and whose source is connected to the input of the first inverter, and a drain of the first transistor and a power supply. a first load connected between said first inverter and a second load having a lower threshold than said first inverter and having an input connected to said first inverter input;
an inverter of a first conductivity type, the gate of which receives the output of the second inverter, the source of which is connected to the input of the second inverter, and the drain of which is connected to the power supply directly or through a second load. 2. A sense amplifier characterized by comprising: 2 transistors.