JP2635915B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit provided in a semiconductor integrated circuit for outputting internal data to the outside.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is necessary to drive a large external capacitance, for example, a load capacitance of about 100 pF, by its output. Therefore, in an output buffer circuit that outputs internal data of a semiconductor integrated circuit to the outside,
In order to sufficiently drive such a large load capacitance, the current driving capability of the transistor in the output stage is set to be extremely large.

FIG. 7 is a circuit diagram showing a configuration of a conventional output buffer circuit. Data Dou formed inside the integrated circuit
t 'is supplied to the input node 11 of the output buffer circuit.
During the period when this output buffer circuit is operated, the control signal O
D1 is set at "L" level or control signal OD2 is set at "H" level. When the control signal OD1 is set to the "L" level, the P-channel MOS transistor (hereinafter referred to as P-transistor) 12 is turned on, the N-channel MOS transistor (hereinafter referred to as N-transistor) 13 is turned off, and the node 11 is turned off. The data Dout 'supplied to the gate of the output stage P-transistor 18 is sequentially passed through an inverter comprising a P-transistor 14 and an N-transistor 15 and an inverter comprising a P-transistor 16 and an N-transistor 17. -To be supplied to

On the other hand, when the control signal OD2 is set to the "H" level, the N-transistor 19 is turned on and the P-transistor 20 is turned off, so that the data Dout 'supplied to the node 11 becomes P-d. Through an inverter composed of a transistor 21 and an N transistor 22 and an inverter composed of a P transistor 23 and an N transistor 24, N
It is supplied to the gate of transistor 25.

Here, the sources of the transistors 18 and 25 in the output stage are connected to the node of the positive power supply voltage VDD and the ground voltage V.
The drains are connected to output nodes (output terminals) 26, respectively.

In such an output buffer circuit, one of the transistors 18 and 25 in the output stage is turned on in accordance with the level of the internal data Dout 'supplied to the input node 11, and this output is turned on. Output transistor
The load capacitance 27 connected to the node 26 is charged with the power supply voltage VDD or discharged to the ground voltage VSS.

By the way, in order to charge and discharge the load capacitance 27 with a large current and make the rise and fall of the data Dout of the output node 26 steep, the transistor 18
The element size of 25, for example, the channel width W is increased, and the conductance of each element is set large.

When a semiconductor integrated circuit provided with an output buffer circuit having the above configuration, that is, an integrated circuit (IC) is incorporated in a system, the power supply voltage VDD and the ground voltage VSS are output from the power supply device 30 via wires as shown in FIG. Supplied to the circuit. Therefore, when a large current flows through these wirings due to the effects of the inductances 31 and 32 existing in the wirings of VDD and VSS, large potential fluctuations occur in the power supply voltages VDD and VSS. That is, assuming that an inductance component existing in these wirings is L and a rate of a temporal change of a current flowing through the wirings is di / dt, a potential change ΔV as given by the following equation occurs in the wirings.

ΔV = L · (di / dt) 1 FIG. 8 shows the voltage of each node in the output buffer circuit,
FIG. 4 is a waveform diagram showing a current waveform. In FIG. 8, Va is a voltage waveform of the gate node a of the P transistor 18 in the output stage,
Vb is the voltage waveform of the gate node b of the N transistor 25,
Is is the drain current waveform of the P transistor 18, and It is N
9 shows a drain current waveform of the transistor 25.

As shown, after the level of the internal data Dout 'changes, the gate voltage V
a and Vb change, and the transistors 18 and 25 perform a switching operation. As a result, the drain current Is of the P transistor 18 or the drain current It of the N transistor 25 flows, and this current causes potential fluctuations in the voltages VDD and VSS.

As described above, when data is output from the output buffer circuit, a large current flows in the output stage, causing a potential change in the power supply voltages VDD and VSS inside the IC. Then, this potential fluctuation causes a malfunction in the IC.

A malfunction caused by charging / discharging current with respect to the load capacity is required because an IC is required to have a high speed, and when charging / discharging of the load capacity needs to be performed in a shorter time, a larger current needs to flow. More likely to occur.

The mechanism causing such a malfunction is as follows. The fluctuations in the potentials of VDD and VSS occur inside an IC that outputs data to the outside.
A data input section of this IC, that is, an input buffer circuit (not shown) takes in data supplied from another IC. Therefore, even if the voltages VDD and VSS inside the IC that outputs data fluctuate, the input data to the IC changes.
Data level does not change. This causes a malfunction.

For example, it is assumed that "L" level is supplied as input data. At this time, when the voltage VSS of the IC to which the data is supplied changes in the negative direction,
The input buffer circuit inside the IC which uses this voltage VSS as a reference potential may regard this "L" level input data as "H" level. That is,
Since VSS changes in the direction of the negative polarity, the potential difference between the "L" level of the input data and VSS becomes large, and the "L" level potential of the input data becomes relatively relative to VSS. It has risen. For this reason, even though the input data is at the "L" level, the input buffer circuit reads this as "H" level and transmits it internally. This causes the IC to malfunction. On the contrary, the voltage V
When SS changes in the direction of positive polarity, the input buffer circuit may regard input data at "H" level as "L" level. Such a malfunction also occurs in a sense amplifier circuit or the like to which an intermediate potential read from a memory cell is supplied.

When output data from, for example, a CMOS-IC is supplied to an IC provided with such an output buffer circuit, the "H" level of the input data is set by a P transistor. Since the battery is charged, it reaches almost the same level as the power supply voltage VDD. Therefore, even if the ground voltage VSS fluctuates in the positive polarity direction in the output buffer circuit when the "H" level is supplied as the input data, the "H" level of the input data is changed. Is sufficiently higher than the fluctuating ground voltage VSS, so that it is unlikely that a malfunction occurs in the input buffer circuit or the like.

On the other hand, since the "L" level of the input data is discharged by the N transistor, it reaches almost the same level as the earth voltage VSS. However, when driven by the output of the TTL-IC, the "H" level of the TTL output is output only up to about 3.5V. The “L” level is 0.
It is about 25V. Naturally, CMOS-IC, TTL
It must operate on both inputs of the IC.
Therefore, the circuit threshold voltage of the input buffer circuit is generally
It is set to about 1.5 V. Even if a CMOS-IC is used, if the ground voltage VSS fluctuates in the negative direction while input data at the "L" level is supplied, the input data The potential difference between the "L" level of the data and the ground voltage VSS increases, and the possibility of malfunctions occurring in the input buffer circuit or the like increases.

[0017]

As described above, in the conventional output buffer circuit, when the level of the output data changes, a potential change occurs in the high-potential power supply voltage and the low-potential earth voltage. There is a problem that a malfunction of another circuit is caused by the potential fluctuation of the earth voltage.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an output buffer circuit capable of suppressing a change in power supply potential due to a change in the level of output data. It is in.

[0019]

An output buffer circuit according to the present invention is connected between an output terminal and a first power supply potential supply terminal to output data inside the integrated circuit to the outside of the integrated circuit. A first charge for charging the output terminal toward the first power supply potential when the data is at a first logic level;
A MOS transistor, first control means for controlling a gate potential of the first MOS transistor in response to the data, and a first power supply potential supply terminal connected between the output terminal and a second power supply potential supply terminal. A second MOS transistor that discharges the output terminal toward the second power supply potential when is at a second logic level, and a second MOS transistor that controls a gate potential of the second MOS transistor in response to the data. 2
In the output buffer circuit having the second control means, the second control means is provided independently of the first control means, and the second control means has one end connected to the second MO.
A resistive element connected to the gate of the S transistor; a drain connected to the other end of the resistive element; a source connected to the first power supply terminal; and a gate controlled in response to the data. A third MOS transistor, wherein when the data is at the second logic level, the output terminal is quickly discharged at an early stage of discharging to output the data quickly and is present at the output terminal. The gate of the second MOS transistor is charged through the resistive element in order to suppress the fluctuation of the power supply potential when discharging the capacitance, and the second transistor is charged through the resistive element.
When the gate of the MOS transistor is charged, the current flowing through the resistive element increases in the initial stage, and thereafter decreases so as to be charged.

[0020]

The third MO for setting the gate of the second MOS transistor provided in the output stage to the first power supply potential.
The third MOS transistor is connected by connecting a resistive element between the S transistor and the gate of the second MOS transistor.
The on-state current of the transistor is controlled so that di / d without delaying the rate of change of data at the output terminal.
The value of t is reduced, and the fluctuation of the power supply potential is suppressed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to the present invention. The data Dout 'formed inside the integrated circuit is supplied to the input node 11 of the output buffer circuit. The data Dout 'of the input node 11 is composed of P transistors 12 and 14 and N transistors 13 and 15.
It is supplied to an R gate circuit G1 and a NAND gate circuit G2 comprising P transistors 20, 21 and N transistors 19, 22. The control signal OD1 is supplied to the NOR gate circuit G1.
However, a control signal OD2 is supplied to the NAND gate circuit G2. The output of the NOR gate circuit G1 is a CM comprising a P transistor 16 and an N transistor 17.
The above-mentioned NAND gate circuit G2 is connected to the OS inverter IN1.
Is supplied to a CMOS inverter IN2 comprising a P-transistor 23 and an N-transistor 24.

The output of the inverter IN1 is P at the output stage.
The output of the inverter IN2 is supplied to the gate of the transistor 18 and the gate of the N-transistor 25 in the output stage. The source of the P transistor 18 in the output stage is connected to the node of the power supply voltage VDD, and the drain is connected to the output node 26. Also, the source of the N-transistor 25 in the output stage is
Is the node of the ground voltage VSS, and the drain is the output node.
26 are connected respectively. The output node 26 is connected to a load capacitor 27.

Further, in the circuit of this embodiment, the CMOS
A resistor 28 as a resistive element is connected between the drain of the P transistor 23 in the inverter IN2 and the gate of the N transistor 25 in the output stage. Due to the connection of the resistor 28, the element size of the P transistor 23 is set sufficiently larger than the corresponding element size of the P transistor 23 in the conventional circuit.

In FIG. 1, reference numeral 30 denotes a power supply, and reference numerals 31 and 32 denote inductances existing in the VDD and VSS wirings. In the case of the circuit of this embodiment, the load capacitance 27 is charged and discharged with a large current, and the rising and falling of the data Dout to be output from the output node 26 are sharpened. The element size, for example, the channel width W is increased, and the conductance of each element is set large.

The basic operation of the circuit having the above configuration is the same as the conventional one. That is, when the control signal OD1 is set to the "L" level and the data Dout 'of the "L" level is supplied to the node 11, the output of the NOR gate circuit G1 becomes "H". Level, output of inverter IN1 is "L"
Level. At this time, the P transistor 18 in the output stage is turned on, and the load capacitance 27 connected to the output node 26 is turned on.
Is charged with the power supply voltage VDD, and the output data Dout is “H”.
Set to level.

On the other hand, when the control signal OD2 is set to the "H" level, the data D of the "H" level is applied to the node 11.
When out 'is supplied, the output of the NAND gate circuit G2 goes low and the output of the inverter IN2 goes high. At this time, the N transistor 25 in the output stage is turned on, the load capacitance 27 connected to the output node 26 is discharged to the ground voltage VSS, and the output data Dout is set to the "L" level. You.

Now, consider the case where the output node 26 which has been charged to the power supply voltage VDD in advance is discharged. Immediately after the start of the discharge, the gate voltage of the N-transistor 25 increases, and the output node 26 is discharged via the N-transistor 25. At this time, the output node 26, that is, the N transistor
Until the drain voltage of 25 becomes lower than its gate voltage by the threshold voltage, N-transistor 25 operates in the saturation region. That is, for a predetermined period immediately after the start of discharge, the transistor 25 operates in the saturation region. It is generally well known that the following equation holds between the drain current ID and the drain voltage VD when the MOS transistor operates in the saturation region.

ID = 1/2 · β (VG−VT) ² ... 2 (β = constant, VT = threshold voltage) That is, the value of the drain current ID flowing to the N-transistor 25 in the output stage in the circuit of the above embodiment is It is proportional to the square of the gate voltage VG. For the sake of simplicity, it is assumed that the gate voltage VG of the transistor rises approximately as a linear function of time. At this time, VG
Can be expressed as VG = at (where a is a constant, t
Is time). Substituting this into the above two equations and differentiating with time t, dID / dt is as follows.

DID / dt = β (a ² · ta · VT) 3 That is, dID / dt increases with time t.
However, actually, the gate voltage VG does not rise as a linear function of time, but does not become higher than the power supply voltage, and takes a maximum value in a certain time. Then, since VG = at, t = VG / a.

Therefore, by substituting t = VG / a into the above three equations, the following four equations are obtained. dID / dt = β (a · VG−a · VT) = β · a (VG−VT) 4 This equation is shown in FIG.
a is a straight line. DID / dt with increasing gate voltage
Increases, and when VG-VT becomes the value of A in FIG. 2, dID / dt becomes the value of B. As mentioned above, V
When rising in the relation of G = at, VG-VT and dID
The relationship of / dt is represented by a straight line having a slope of β · a.
Assuming that VG rises with a value larger than a, dID / dt changes in a region above the slope β · a. a
If it rises with a smaller value, dID / dt changes in a region below the slope β · a. For example, VG
= 2a · t, the slope in FIG.
It changes along the straight line a, and when V G -V T reaches the value of A in FIG. 2, d ID / dt becomes twice the value. However, the time required to reach A is t = A / V when VG = at.
a, whereas when VG = 2a · t, t = A / 2
a, which is reduced to half the time.

When the voltage rises at VG = 1 / 2.at, it changes along a straight line having a slope β.1 / 2.a in FIG.
When d reaches the value of A, dID / dt is reduced by half, but the time until it reaches A is t = 2 A / a, which is twice as long.

As described above, if the angle is higher than the slope β · a, the time required to reach A can be short, but dID / dt
Becomes larger, and if it is lower than β · a, dID / dt
Is small, but it takes longer to reach A.

Next, consider the case where the inclination changes at point C in FIG. The slope increases by β · 2a up to the point C, and increases by β · 1/2 · a after the point C. In this case, VG
DID / dt when -VT reaches the value of A is the slope β ·
Since it becomes equal to the case of a and changes above β · a, the time required to reach A is shortened. That is, gay
In the region where the gate voltage is low and dID / dt is small, the gate voltage rise speed is increased, and in the region where dID / dt is large and the gate voltage is high, the gate voltage rise speed is decreased, and the same dID is obtained. The charging speed can be increased while maintaining / dt.

This is realized by the circuit of the above-described embodiment, in which the CM driving the gate of the N-transistor 25 in the output stage is used.
A resistor 28 is connected between the drain of the P transistor 23 in the OS inverter IN2 and the gate of the N transistor 25 in the output stage. With such a configuration, when the gate voltage of the N-transistor 25 in the output stage rises and transitions from the off-state to the on-state, the amount of increase in the current of the N-transistor 25 is small and di / dt is small. The node b is rapidly charged up to the gate voltage, and at a gate voltage where di / dt increases, the node b is slowly charged by the presence of the resistor 28. Therefore, the ratio di / dt of the temporal change of the current flowing through the VSS line when the N transistor 25 is turned on is reduced when the same speed is obtained.
The operating speed can be increased at the same di / dt.

FIG. 3 shows the case where the P transistor 23 is used alone,
FIG. 9 is a characteristic diagram showing the relationship between the drain voltage V D and the drain current ID when the gate voltage V G is used as a parameter for each of the P transistors 23 when the resistor 28 is connected to the drain. In this characteristic diagram, the source is the ground voltage V
The voltage is fixed to SS, and the drain voltage is increased from 0 V in the negative direction.

In the drawing, the solid line is the case of the P transistor 23 alone and corresponds to the conventional circuit, and the broken line is the one of the P transistor 23 in the case of the circuit of the embodiment in which the resistor 28 is connected. In the circuit of the above embodiment, by connecting the resistor 28,
The lower the gate voltage VG, that is, the higher the negative voltage,
P transistor 23 exhibits constant resistance characteristics. In the region where the gate voltage VG is low and the drain voltage VD is high, the drain current ID is suppressed as compared with the case where the resistor 28 is not connected. Conversely, in the region where the drain voltage VD is low, the resistance is low.
As compared with the case where the transistor 28 is not connected, a characteristic that a larger drain current ID flows is obtained. That is, in a region where the conduction resistance of the P transistor 23 having a low gate voltage is small, the characteristics of the resistor 28 connected in series appear more strongly. The above resistance
It goes without saying that the conduction resistance of the P-transistor 23 of this embodiment circuit is smaller than that of the P-transistor 23 of the conventional circuit without the 28.

In FIG. 1, the input of the inverter IN2 becomes "L" level, the P transistor 23 is turned on, and the resistance
When the gate of N-transistor 25 is charged via 28, a current flows according to the characteristics when VG = -5V in FIG. Immediately after the gate of the N-transistor 25 starts to be charged, since the potential difference between the source and the drain of the P-transistor 23 is large, more current flows than in the prior art, and the gate of the N-transistor 25 becomes Charges quickly. When the gate of the N-transistor 25 is charged to a potential equal to or higher than the potential at the intersection of the conventional solid line characteristic at VG = -5V in FIG. , The potential difference between the source and the drain becomes smaller sequentially, the current at the same drain voltage as in the prior art becomes smaller as shown by the broken line, and the gate charging speed of the N transistor 25 becomes slower than in the prior art.

FIG. 4 is a characteristic diagram showing a voltage change of each node in the circuit of the embodiment and the conventional circuit. In the drawing, the characteristics shown by the solid line are those of the conventional circuit, and the characteristics shown by the broken line are those of the circuit of the embodiment. The voltage Vb of the node b in the circuit of the embodiment shown by the broken line is charged more rapidly in the region where the drain voltage is low as compared with the conventional circuit shown by the solid line. Conversely, when the drain voltage increases, the node b is less likely to be charged than in the conventional circuit shown by the solid line.

As a result, the node b is charged more rapidly than in the conventional circuit until the time when the N-transistor 25 reaches a gate voltage at which the N-transistor 25 is sufficiently turned on.
The load capacitance 27 connected to the node 26 is charged more rapidly than in the conventional circuit. However, the peak value of di / dt is not different from the conventional circuit. After the N transistor 25 is sufficiently turned on, the node b is charged more slowly than in the conventional circuit.

Therefore, in the circuit of the above embodiment, the load capacitance 27
Of the discharge current flowing through the N-transistor 25 in the output stage when the discharge speed of the
The value of / dt and the value of the peak current can be made smaller than in the conventional circuit, and the potential fluctuation of the ground voltage VSS can be made smaller than in the conventional circuit. As a result, it is possible to prevent a malfunction of another circuit caused by the potential fluctuation of the earth voltage.

It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified. For example, in the circuit of the above embodiment, the case where the resistor 28 is connected as a resistive element between the drain of the P transistor 23 and the gate of the N transistor 25 has been described. An element can be used.

For example, in the modified circuit shown in FIG. 5A, a depletion type MOS transistor 41 is used as a resistive element instead of the resistor 28.
As shown in the figure, the data Dout 'is input to the gate so that the transistor 41 is turned on when the node b is charged by the power supply voltage VDD.
However, the gate of the transistor 41 has the power supply voltage VDD.
May be supplied. Further, instead of the resistor 28, as shown in FIG.
Source between S transistor 41 and this transistor 41
An N-transistor 42 whose drain and drain are connected in parallel may be provided, or only an N-transistor 42 acting as a resistor may be provided as shown in FIG.

FIG. 6 shows the above-mentioned FIG.
FIG. 4 is a characteristic diagram showing a relationship between a drain voltage V D and a drain current ID of a P transistor 23 corresponding to FIG. 3 when a depletion type MOS transistor 41 as shown in FIG. 3A is used as a resistive element.

In the embodiment shown in FIG. 1, the case where a resistive element, for example, a resistor 28 is connected between the drain of the P transistor 23 and the gate of the N transistor 25 has been described. And P transistor 18
A resistive element may be connected between the gate and the gate. By doing so, the potential fluctuation of the power supply voltage VDD can be reduced, and the characteristics can be further improved.

[0045]

As described above, according to the present invention,
Since the current flowing through the output stage transistor is controlled by using the resistive element, it is possible to suppress the potential fluctuation of the power supply voltage due to the change in the level of the output data. In addition, the level change speed of the output data does not decrease.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to one embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between a gate voltage of a MOS transistor and di / dt in the circuit of the embodiment.

FIG. 3 is a characteristic diagram showing a relationship between a drain voltage and a drain current of each corresponding MOS transistor in the circuit of the embodiment and the conventional circuit.

FIG. 4 is a characteristic diagram showing a voltage change of each node in the circuit of the embodiment and the conventional circuit.

FIG. 5 is a circuit diagram showing a configuration of a modification of the circuit of the embodiment.

FIG. 6 is a diagram showing an MO in the case of using one of the modified circuits of FIG. 5;
FIG. 4 is a characteristic diagram illustrating a relationship between a drain voltage and a drain current of an S transistor.

FIG. 7 is a conventional circuit diagram.

FIG. 8 is a waveform diagram of each node of the conventional circuit.

[Explanation of symbols]

11 ... input nodes, 12, 14, 16, 18, 20, 21, 23 ... P-channel MOS transistors (P transistors), 13, 15,
17, 19, 22, 24, 25, 42 ... N-channel MOS transistor (N transistor), 26 ... signal output node (output terminal), 27 ... load capacitance, 28 ... resistance, 41 ... depletion type MOS transistor G1: NOR gate circuit, G2
... NAND gate circuits, IN1, IN2 ... CMOS inverters.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroto Nakai 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (56) References JP-A-63-136823 (JP, A) 63-5553 (JP, A)

Claims (1)

(57) [Claims] A first power supply potential supply terminal connected to an output terminal for outputting data inside the integrated circuit to the outside of the integrated circuit; and when the data is at a first logic level. A first MOS transistor that charges the output terminal toward the first power supply potential; a first control unit that controls a gate potential of the first MOS transistor in response to the data; And a second MOS connected between the first power supply potential and the second power supply potential, and discharging the output terminal toward the second power supply potential when the data is at the second logic level.
An output buffer circuit comprising: a transistor; and second control means for controlling a gate potential of the second MOS transistor in response to the data, wherein the second control means is different from the first control means. Independently provided, the second control means includes a resistive element having one end connected to the gate of the second MOS transistor, a drain connected to the other end of the resistive element, and a source connected to the second MOS transistor. And a third MOS transistor having a gate controlled in response to the data, and an initial stage of discharging the output terminal when the data is at a second logic level. In order to quickly output the above data and discharge the capacitance existing at the output terminal, and to suppress the fluctuation of the power supply potential when discharging the capacitance existing at the output terminal. It charges the gate of the second MOS transistor, and the second MO through the resistive element
An output buffer circuit characterized in that when charging the gate of the S-transistor, the current flowing through the resistive element increases in the initial stage, and thereafter decreases so as to be charged. .