JPH0715315A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an output buffer circuit capable of suppressing flucutuation in a power supply potential due to the level change in output data. CONSTITUTION:A gate potential of a P-channel MOS transistor(TR) 18 of an output stage is controlled by an output of an inverter IN2 consisting of a P- channel MOS TR 16 and an N-channel MOS TR 17. A gate potential of an N-channel MOS TR 25 at the output stage is controlled by an output of an inverter IN2 comprising a P-channel MOS TR 23, an N-channel MOS TR 24 and a resistor 28 connected between a gate of the MOS TR 25 and a drain of the P-channel MOS TR 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit provided in a semiconductor integrated circuit and outputting internal data to the outside.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is necessary to drive a large external capacitance, for example, a load capacitance of about 100 pF, by its output. Therefore, in the output buffer circuit that outputs the internal data of the semiconductor integrated circuit to the outside,
In order to be able to sufficiently drive such a large load capacitance, the current drive capability of the transistor in the output stage is set extremely large.

FIG. 7 is a circuit diagram showing the structure of a conventional output buffer circuit. Data Dou formed inside the integrated circuit
t'is supplied to the input node 11 of the output buffer circuit.
During the period in which this output buffer circuit is operated, the control signal O
D1 is set to "L" level or control signal OD2 is set to "H" level. When the control signal OD1 is set to "L" level, the P channel MOS transistor (hereinafter referred to as P transistor) 12 is turned on, the N channel MOS transistor (hereinafter referred to as N transistor) 13 is turned off, and the node 11 The data Dout 'supplied to the gate of the output stage P-transistor 18 is sequentially passed through the inverter composed of the P-transistor 14 and the N-transistor 15 and the inverter composed of the P-transistor 16 and the N-transistor 17. -To be supplied to

On the other hand, when the control signal OD2 is set to the "H" level, the N transistor 19 is turned on and the P transistor 20 is turned off, so that the data Dout 'supplied to the node 11 is P. Through the inverter composed of the transistor 21 and the N transistor 22 and the inverter composed of the P transistor 23 and the N transistor 24 in sequence, the N of the output stage
It is supplied to the gate of the transistor 25.

Here, the sources of the transistors 18 and 25 at the output stage are connected to the node of the positive power supply voltage VDD and the ground voltage V, respectively.
Each of them is connected to the node of SS, and the drains thereof are both connected to the output node (output terminal) 26.

In such an output buffer circuit, one of the transistors 18 and 25 in the output stage is turned on according to the level of the internal data Dout 'supplied to the input node 11, and this is turned on. Output transistor
The load capacitance 27 connected to the gate 26 is charged with the power supply voltage VDD or discharged to the ground voltage VSS.

By the way, in order to charge and discharge the load capacitance 27 with a large current to make the rise and fall of the data Dout of the output node 26 steep, the transistor 18,
The element size of 25, for example, the channel width W is increased, and the conductance of each is set large.

When a semiconductor integrated circuit having a so-called output buffer circuit having the above-mentioned structure, that is, an IC, is incorporated in a system, the power supply voltage VDD and the ground voltage VSS are respectively output from the power supply device 30 via wiring as shown in the figure. Supplied to the circuit. Therefore, due to the influence of the inductances 31 and 32 existing in the wirings of VDD and VSS, when a large current flows through these wirings, a large potential fluctuation occurs in the power supply voltages VDD and VSS. That is, assuming that the inductance component existing in these wirings is L and the rate of temporal change of the current flowing in the wirings is di / dt, a potential change ΔV given by the following equation is generated in the wirings.

ΔV = L (di / dt) ... 1 FIG. 8 shows the voltage of each node in the output buffer circuit,
It is a waveform diagram which shows a current waveform. In FIG. 8, Va is the voltage waveform of the gate node a of the P-transistor 18 at the output stage,
Vb is the voltage waveform of the gate node b of the N-transistor 25,
Is is the drain current waveform of the P-transistor 18 and It is N
7 is a drain current waveform of the transistor 25.

As shown in the figure, after the level of the internal data Dout 'changes, the gate voltage V of the transistors 18 and 25 is changed.
a and Vb change, and the transistors 18 and 25 perform a switching operation. As a result, the drain current Is of the P-transistor 18 or the drain current It of the N-transistor 25 flows, and this current causes potential fluctuations in the voltages VDD and VSS.

As described above, when data is output from the output buffer circuit, a large current flows through the output stage, causing potential fluctuations in the power supply voltages VDD and VSS inside the IC. Then, this potential fluctuation causes malfunction of the IC.

The malfunction caused by the charging / discharging current with respect to the load capacitance requires high speed of the IC, and when charging / discharging the load capacitance in a shorter time, a larger current needs to flow. , More likely to happen.

The mechanism that causes such a malfunction is as follows. The potential fluctuations of VDD and VSS occur inside the IC which outputs data to the outside.
The data input section of this IC, that is, an input buffer circuit (not shown) incorporates data supplied from another IC. Therefore, even if the voltages VDD and VSS inside the IC that outputs the data fluctuate, the input data to that IC
Level does not change. This causes a malfunction.

For example, it is assumed that the "L" level is supplied as the input data. At this time, if the voltage VSS of the IC to which this data is supplied changes in the negative direction,
The input buffer circuit inside the IC that uses this voltage VSS as the reference potential may regard this "L" level input data as "H" level. That is,
Since VSS changes in the direction of negative polarity, the potential difference between the “L” level of the input data and VSS becomes large. Considering VSS as a reference, the “L” level potential of the input data is relatively high. It has risen. For this reason, the input buffer circuit reads this as "H" level and transmits it internally even though the input data is at "L" level. This causes the IC to malfunction. On the contrary, the voltage V
When SS changes in the positive direction, the input buffer circuit may consider the input data of "H" level to be "L" level. Such malfunction also occurs in the sense amplifier circuit or the like to which the intermediate potential read from the memory cell is supplied.

When output data from, for example, a CMOS-IC is supplied to an IC provided with such an output buffer circuit, the "H" level of this input data is set by a P-transistor. As it is charged, it reaches almost the same level as the power supply voltage VDD. Therefore, even if the ground voltage VSS fluctuates in the positive direction in the output buffer circuit when the "H" level is supplied as the input data, the "H" level of the input data is obtained. Is sufficiently higher than the changing ground voltage VSS, so that it is unlikely that a malfunction occurs in the input buffer circuit or the like.

On the other hand, since the "L" level of the input data is discharged by the N transistor, it reaches almost the same level as the ground voltage VSS. However, when driven by the output of the TTL-IC, the "H" level of the TTL output is only output up to about 3.5V. The "L" level is 0.
It is about 25V. Of course, CMOS-IC, TTL
It must work for both inputs of the IC.
Therefore, the circuit threshold voltage of the input buffer circuit is generally
The input voltage is set to about 1.5V, and even if the CMOS IC is used, if the ground voltage VSS fluctuates in the negative direction while the "L" level input data is supplied. The potential difference between the "L" level of the input voltage and the ground voltage VSS becomes large, and there is a high possibility that a malfunction will occur in the input buffer circuit or the like.

[0017]

As described above, in the conventional output buffer circuit, when the level of the output data changes, the high-potential side power supply voltage and the low-potential side ground voltage fluctuate. There is a problem that the potential fluctuation of the ground voltage causes malfunction in other circuits.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an output buffer circuit capable of suppressing the fluctuation of the power supply potential due to the level change of the output data. Especially.

[0019]

An output buffer circuit according to the present invention is connected between an output terminal and a first power supply potential supply terminal in order to output data inside the integrated circuit to the outside of the integrated circuit. Charging the output terminal toward the first power supply potential when the data is at a first logic level
Connected to between the output terminal and the second power supply potential supply terminal, and the first control means for controlling the gate potential of the first MOS transistor in response to the data, Is a second logic level, the second MOS transistor discharges the output terminal toward the second power supply potential, and the second MOS transistor controls the gate potential of the second MOS transistor in response to the data. Two
In the output buffer circuit, the second control means is provided independently of the first control means, and one end of the second control means is the second MO.
A resistive element connected to the gate of the S transistor, a drain connected to the other end of the resistive element, a source connected to the first power supply potential supply terminal, and a gate controlled in response to the data. And a third MOS transistor which is present at the output terminal, when the data is at the second logic level, the discharge at the initial stage of the discharge of the output terminal is quickly performed to quickly output the data. The gate of the second MOS transistor is charged through the resistive element and the second element is charged through the resistive element in order to suppress fluctuation of the power supply potential when discharging the capacitance.
When the gate of the MOS transistor is charged, the current flowing through the resistive element is increased in the initial stage, and thereafter, the current is gradually decreased to be charged.

[0020]

A third MO transistor for setting the gate of the second MOS transistor provided in the output stage to the first power supply potential.
By connecting a resistive element between the S-transistor and the gate of the second MOS transistor, the third MOS
The on-current of the transistor is controlled so that the rate of change of data at the output terminal is not delayed and di / d
The value of t is reduced and the fluctuation of the power supply potential is suppressed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to the present invention. The data Dout 'formed inside the integrated circuit is supplied to the input node 11 of the output buffer circuit. The data Dout 'of this input node 11 is NO composed of P-transistors 12 and 14 and N-transistors 13 and 15.
It is supplied to an R gate circuit G1 and a NAND gate circuit G2 including P transistors 20, 21 and N transistors 19, 22. The NOR gate circuit G1 has a control signal OD1.
However, the control signal OD2 is supplied to the NAND gate circuit G2. The output of the NOR gate circuit G1 is a CM including a P-transistor 16 and an N-transistor 17.
The NAND gate circuit G2 is connected to the OS inverter IN1.
Is supplied to the CMOS inverter IN2 composed of the P-transistor 23 and the N-transistor 24, respectively.

The output of the inverter IN1 is P of the output stage.
The output of the inverter IN2 is supplied to the gate of the transistor 18, and is supplied to the gate of the N-transistor 25 of the output stage. The source of the P-transistor 18 in the output stage is connected to the node of the power supply voltage VDD, and the drain is connected to the output node 26. In addition, the source N-transistor 25 source
The ground is the node of the ground voltage VSS, and the drain is the output node.
26 connected to each. A load capacitance 27 is connected to the output node 26.

Furthermore, in the circuit of this embodiment, the CMOS
A resistor 28 as a resistive element is connected between the drain of the P transistor 23 in the inverter IN2 and the gate of the N transistor 25 in the output stage. By connecting the resistor 28, the element size of the P-transistor 23 is set sufficiently larger than the element size of the corresponding P-transistor 23 in the conventional circuit.

In FIG. 1, 30 is a power supply device, and 31 and 32 are inductances existing in the wirings of VDD and VSS. In the case of the circuit of this embodiment, in order to charge and discharge the load capacitance 27 with a large current and make the rising and falling of the data Dout to be output from the output node 26 steep, The element size, for example, the channel width W is increased, and the conductance of each is set large.

The basic operation of the circuit configured as described above is the same as the conventional one. That is, when the control signal OD1 is set to "L" level and the data Dout 'of "L" level is supplied to the node 11, the output of the NOR gate circuit G1 is "H". Level, output of inverter IN1 is "L"
It becomes a level. At this time, the P-transistor 18 in the output stage is turned on, and the load capacitance 27 connected to the output node 26
Is charged with the power supply voltage VDD, and the output data Dout is "H".
Set to level.

On the other hand, when the control signal OD2 is set to "H" level, the data D of "H" level is supplied to the node 11.
When out 'is supplied, the output of the NAND gate circuit G2 becomes "L" level and the output of the inverter IN2 becomes "H" level. At this time, the N transistor 25 of the output stage is turned on, the load capacitance 27 connected to the output node 26 is discharged to the ground voltage VSS, and the output data Dout is set to "L" level. It

Now, consider the case of discharging the output node 26 which has been charged to the power supply voltage VDD in advance. Immediately after starting the discharge, the gate voltage of the N-transistor 25 rises, and the output node 26 is discharged through the N-transistor 25. At this time, the output node 26, that is, the N transistor
The N-transistor 25 operates in the saturation region until the drain voltage of 25 becomes lower than the gate voltage by the threshold voltage. That is, the transistor 25 operates in the saturation region for a predetermined period immediately after the start of discharge. It is generally well known that the following equation holds between the drain current ID and the drain voltage VD when the MOS transistor operates in the saturation region.

ID = 1 / 2β (VG-VT) ² ... 2 (β = constant, VT = threshold voltage) That is, the value of the drain current ID flowing through the N-transistor 25 of the output stage in the above-described circuit is It is proportional to the square of the gate voltage VG. To simplify the explanation, it is assumed that the gate voltage VG of the transistor rises approximately as a linear function of time. At this time VG
Can be represented by VG = a · t (a is a constant, t
Is time). Substituting this into the above equation 2 and differentiating it at time t, dID / dt is as follows.

DID / dt = β (a ² · ta−VT) 3 That is, dID / dt increases with time t.
However, in reality, the gate voltage VG does not rise as a linear function of time, does not exceed the power supply voltage, and takes a maximum value in a certain time. Then, since VG = a · t, t = VG / a.

Therefore, by substituting t = VG / a into the above three equations, the following four equations are obtained. dID / dt = β (aVG-aVT) = βa (VG-VT) ... 4 The graph of these four equations shows that the slope in the characteristic diagram of FIG. 2 is β
It is a straight line of a. As the gate voltage increases, dID / dt
When VG-VT becomes the value of A in FIG. 2, dID / dt becomes the value of B. As mentioned above, V
When rising due to the relationship of G = a · t, VG −VT and dID
The relationship of / dt is represented by a straight line having a slope of β · a.
If VG rises with a value larger than a, dID / dt changes in the region above the slope β · a. a
If the value rises with a smaller value, dID / dt changes in the region below the slope β · a. For example, VG
= 2a · t, the slope in FIG. 2 is β · 2
It changes with the straight line of a, and when the VG-VT reaches the value of A in FIG. 2, dID / dt becomes a double value. However, the time required to reach A is t = A / when VG = a · t
On the other hand, when VG = 2a · t, t = A / 2
a, which is reduced to half the time.

When it rises at VG = 1 / 2.multidot.t, it changes along the straight line with the slope .beta..1 / 2.a in FIG.
When the value of A reaches the value of A, dID / dt is reduced to half, but the time to reach A is t = 2A / a, which is twice as long.

As described above, if the slope is above the slope β · a, the time to reach A can be short, but dID / dt
Becomes larger, and if lower than β · a, dID / dt
Can be small, but it will take longer to reach A.

Next, consider the case where the inclination changes at point C in FIG. The slope increases to β · 2a up to point C, and increases to β · 1/2 · a after point C. In this case, VG
When d-VT reaches the value of A, dID / dt has a slope β
Since it becomes equal to that at a and changes above β · a, the time to reach A becomes short. That is,
The same dID can be obtained by increasing the gate voltage rising speed in a low dID / dt region where the gate voltage is low and slowing the gate voltage rising speed in a large dID / dt region where the gate voltage is high. The charging speed can be increased while maintaining / dt.

This is realized by the circuit of the above embodiment, which is a CM for driving the gate of the N-transistor 25 in the output stage.
A resistor 28 is connected between the drain of the P transistor 23 in the OS inverter IN2 and the gate of the N transistor 25 in the output stage. With such a configuration, the gate voltage of the N-transistor 25 in the output stage rises, and when the off-state transits to the on-state, the current increase amount of the N-transistor 25 is small and di / dt is small. The node b is rapidly charged up to the gate voltage, and at the gate voltage where di / dt increases, the presence of the resistor 28 causes the node b to be charged slowly. Therefore, when the N-transistor 25 is turned on, the rate di / dt of the time change of the current flowing through the VSS line is reduced when the same speed is obtained,
When the di / dt is the same, the operation speed can be increased.

FIG. 3 shows the case of the P-transistor 23 alone,
FIG. 9 is a characteristic diagram showing the relationship between the drain voltage VD and the drain current ID of each P-transistor 23 when the gate voltage VG is used as a parameter when the resistor 28 is connected to the drain. In this characteristic diagram, the source is the ground voltage V
It is fixed at SS and the drain voltage is increased from 0 V in the negative direction.

In the figure, the solid line shows the case of the P-transistor 23 alone and corresponds to the conventional circuit, and the broken line shows the case of the P-transistor 23 in the case of the circuit of the above embodiment in which the resistor 28 is connected. By connecting the resistor 28 in the circuit of the above embodiment,
The lower the gate voltage VG, that is, the larger the negative voltage,
The P transistor 23 exhibits a constant resistance characteristic. In the region where the gate voltage VG is low and the drain voltage VD is high, the drain current ID is suppressed as compared with the case where the resistor 28 is not connected, and conversely, in the region where the drain voltage VD is low, the resistance is low.
The drain current ID is larger than that when 28 is not connected. That is, in the region where the conduction resistance of the P-transistor 23 having a low gate voltage is small, the characteristic of the resistor 28 connected in series appears more strongly. Above resistance
Needless to say, the conduction resistance of the P-transistor 23 of this embodiment circuit is smaller than that of the P-transistor 23 of the conventional circuit in which 28 is not provided.

In FIG. 1, the input of the inverter IN2 becomes "L" level, the P-transistor 23 is turned on, and the resistance
When the gate of the N-transistor 25 is charged via 28, a current flows according to the characteristic when VG = -5V in FIG. Immediately after the gate of the N-transistor 25 begins to be charged, more current flows than before because the potential difference between the source and drain of the P-transistor 23 is large, and the gate of the N-transistor 25 is Charges quickly. When the gate of the N-transistor 25 is charged above the potential at the point where the characteristic of the conventional solid line at VG = -5V in FIG. 3 and the characteristic of the broken line of this embodiment cross, the P-transistor 23 is charged. , The potential difference between the source and the drain becomes smaller, the current at the same drain voltage as in the prior art becomes smaller as shown by the broken line, and the gate charging speed of the N-transistor 25 becomes slower than in the prior art.

FIG. 4 is a characteristic diagram showing a voltage change of each node in the circuit of the embodiment and the conventional circuit. In the figure, the characteristics shown by the solid line are those of the conventional circuit, and the characteristics shown by the broken line are those of the above-mentioned circuit. The voltage Vb of the node b in the circuit of the embodiment shown by the broken line is charged more rapidly in the region where the drain voltage is low as described above than in the case of the conventional circuit shown by the solid line. On the contrary, as the drain voltage becomes higher, the node b becomes more difficult to be charged than in the case of the conventional circuit shown by the solid line.

As a result, in the circuit of the above embodiment, the node b is charged more rapidly than in the conventional circuit until the gate voltage at which the N-transistor 25 is sufficiently turned on is reached.
The load capacitance 27 connected to the node 26 charges faster than in the conventional circuit. However, the peak value of di / dt is the same as that of the conventional circuit. After the N-transistor 25 is fully turned on, the node b is charged more slowly than in the conventional circuit.

Therefore, in the circuit of the above embodiment, the load capacitance 27
Of the discharge current of the output stage N-transistor 25 when the discharge speed of
The value of / dt and the value of the peak current can be made smaller than that of the conventional circuit, and the potential fluctuation of the ground voltage VSS can be made smaller than that of the conventional circuit. As a result, it is possible to prevent the malfunction of other circuits caused by the potential fluctuation of the ground voltage.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the circuit of the above embodiment, the case where the resistor 28 is connected as a resistive element between the drain of the P-transistor 23 and the gate of the N-transistor 25 has been described. Elements can be used.

For example, in the modified circuit of FIG. 5A, a depletion type MOS transistor 41 is used as a resistive element instead of the resistor 28.
The data Dout 'is input to the gate of the transistor 41 so that the transistor 41 is turned on when the node b is charged by the power source voltage VDD.
However, the power supply voltage VDD is applied to the gate of the transistor 41.
May be supplied. Further, instead of the resistor 28, as shown in FIG.
Between the S transistor 41 and this transistor 41,
5 and the N-transistor 42 whose drains are connected in parallel may be provided, or only the N-transistor 42 acting as a resistance may be provided as shown in FIG. 5C.

FIG. 6 is a circuit diagram of FIG.
FIG. 4 is a characteristic diagram showing the relationship between the drain voltage VD and the drain current ID of the P-transistor 23 corresponding to FIG. 3 when the depletion type MOS transistor 41 as shown in FIG.

In the embodiment circuit of FIG. 1, the case where a resistive element such as a resistor 28 is connected between the drain of the P-transistor 23 and the gate of the N-transistor 25 has been described. And P transistor 18
A resistive element may be connected between the gate and the gate. In this way, the potential fluctuation of the power supply voltage VDD can be reduced and the characteristics can be further improved.

[0045]

As described above, according to the present invention,
Since the resistance element is used to control the current flowing through the output stage transistor, it is possible to suppress the potential fluctuation of the power supply voltage due to the level change of the output data. Moreover, the level change speed of the output data does not decrease.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the relationship between the gate voltage of a MOS transistor and di / dt in the circuit of the above embodiment.

FIG. 3 is a characteristic diagram showing the relationship between the drain voltage and the drain current of each of the corresponding MOS transistors in the circuit of the embodiment and the conventional circuit.

FIG. 4 is a characteristic diagram showing a voltage change of each node in the embodiment circuit and the conventional circuit.

FIG. 5 is a circuit diagram showing a configuration of a modified example of the circuit of the embodiment.

6 is an MO when one of the modified circuits of FIG. 5 is used.
The characteristic view which shows the relationship between the drain voltage and drain current of an S transistor.

FIG. 7 is a conventional circuit diagram.

FIG. 8 is a waveform diagram of each node of the conventional circuit.

[Explanation of symbols]

11 ... Input node, 12, 14, 16, 18, 20, 21, 23 ... P-channel MOS transistor (P transistor), 13, 15,
17, 19, 22, 24, 25, 42 ... N-channel MOS transistor (N transistor), 26 ... Signal output node (output terminal), 27 ... Load capacitance, 28 ... Resistor, 41 ... Depletion type MOS transistor, G1 ... NOR gate circuit, G2
... NAND gate circuit, IN1, IN2 ... CMOS inverter.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H03K 19/003 Z 8842-5J (72) Inventor Hiroto Nakai 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture 1-share Ceremony company Toshiba Tamagawa factory

Claims (1)

[Claims] 1. In order to output data inside the integrated circuit to the outside of the integrated circuit, it is connected between an output terminal and a first power supply potential supply terminal, and when the data is at a first logic level. A first MOS transistor for charging the output terminal toward the first power supply potential; first control means for controlling a gate potential of the first MOS transistor in response to the data; and the output terminal And a second power supply potential supply terminal, and a second MOS which discharges the output terminal toward the second power supply potential when the data is at the second logic level.
An output buffer circuit comprising a transistor and second control means for controlling the gate potential of the second MOS transistor in response to the data, wherein the second control means is different from the first control means. The second control means is independently provided, and has a resistive element having one end connected to the gate of the second MOS transistor, a drain connected to the other end of the resistive element, and a source connected to the first element. A third MOS transistor connected to the power supply potential supply terminal of 1 and having a gate controlled in response to the data, the initial stage of discharge of the output terminal when the data is at the second logic level. In order to quickly discharge the above data to output the above data quickly and to suppress the fluctuation of the power supply potential when discharging the capacitance existing in the above output terminal, the above-mentioned resistive element is used. It charges the gate of the second MOS transistor, and the second MO through the resistive element
An output buffer circuit characterized in that, when charging the gate of the S-transistor, the current flowing through the resistive element is increased at an initial stage and then gradually decreased to be charged. .