JPH01295531A - D/a converter circuit using digital trimming - Google Patents

Abstract

PURPOSE:To reduce the increase in a nonlinear error caused by the inversion of a stored data by reflecting a digital trimming data of a D/A converter and storing the data in a binary code. CONSTITUTION:A D/A converter 100 is a D/A converter having a nonlinear error. A D/A converter 200 is a D/A converter to correct the nonlinear error of the D/A converter 1. An input data (a) is added to the D/A converter 100 and a memory address decoder 2 of a memory 3 storing a data correcting the nonlinear error to access the memory 3. The output of the memory 3 is fed to a data converter 4, where the data is converted as the input of the D/A converter 200. In this case, the data is converted from a reflected binary data into a straight binary data. Outputs of the D/A converters 100, 200 are synthesized by an adder 5 and the result is outputted as an output signal (b).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A converter circuit using digital (IJ) mixing.

[Conventional technology]

Conventionally, this type of digital trimming circuit has a D/A converter having a main /A converter and a D/A converter for non-linearity error correction.
The digital input data of the A converter was stored in memory in straight binary code.

[Problem that the invention seeks to solve]

Table 1 shows the non-linear error correction amount of the conventional digital trimming circuit described above and the corresponding straight binary code stored in the memory when the correction data is 4 bits.

If there is a defect in the memory, the stored data will
A reversal may occur. Considering the case where one bit of memory data is inverted, when each weighting is a bit, the maximum error for the correction iK is an error of 8 caused by inverting the MSB by one bit. This occurs regardless of the amount of nonlinearity error correction. This has the disadvantage that a large nonlinearity error may occur regardless of the nonlinearity error of the D/A converter before nonlinearity error correction is performed.

[Means to solve the problem]

In the D/A converter circuit using digital trimming of the present invention, the final output is obtained by combining the output values of two or more D/A converters, and the nonlinearity error of the D/A converter with respect to input data is corrected. In a D/A converter having a D/A converter for storing data input to the D/A converter and a memory for storing input data of the D/A converter, the data stored in the memory is a folded binary code, and the data stored in the memory is a folded binary code. The D/A converter is configured to include a D/A converter that corrects non-linearity errors of the D/A converter by inputting .

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The D/A converter using digital trimming of the present invention has input data latches 1. D/A converter 100, D
/A converter 200, decoder 10 for each D/A converter. Decoder 20. It is composed of a memory address decoder 2, a memory 3, a memory output data converter 4, a D/A converter Too, and an output adder 5 of the D/A converter 200.

The D/A converter 100 is a D/A converter that has a nonlinearity error, and the D/A converter 200 is a D/A converter for correcting the nonlinearity error of the D/A converter 1. Input data a is applied to the D/A converter 100 and the address decoder 2 of the memory 3 in which data for correcting non-linearity errors is stored, and the memory 3 is accessed.

The output of the memory 3 is applied to a data converter 4 and converted as an input to a D/A converter 200.

At this time, folded binary data is converted to straight binary data.

The outputs of the D/A converter 100 and the D/A converter 200 are combined by an adder 5 and output as an output signal.

Note that it is also possible to use a plurality of D/A converters 200.

(Effects of the Invention) As explained above, the present invention reduces the increase in non-linearity errors caused by inversion of the digital trimming data of the D/A converter by storing the digital trimming data of the D/A converter in a folded binary code. 7,
For example, consider an example with 4-bit nonlinearity correction data.

Referring to Table 1, in the case of folded binary codes, as the absolute value of such data increases, the influence of errors due to inversion of memory data increases. However, when the correction amount is in the range of ±2LSB, there is a θ effect in that if the effect of inversion of any bit is only one bit, the error can be suppressed to ±4LSH. Since the correction data itself should be concentrated near the corpse, non-uniformity due to inversion of memory data
The increase in lrf training error can be kept small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Input data latch, 2...Memory address register, 3...Memory, 4...
...Data converter, 5...Adder, 10.2
0...Decoder, 100°200...
D/A converter, a...input signal, b...
...Output signal. Agent Patent Attorney Nai M Shinman 1@

Claims (1)

[Claims] The final output is obtained by combining the output values of two or more D/A converters, and the D/A converter has a D/A converter for correcting non-linearity errors of the D/A converters with respect to input data; In a D/A converter having a memory for storing input data, the data stored in the memory is a folded binary code,
A D/A converter circuit using digital trimming, comprising a D/A converter that receives such data and provides an output that corrects nonlinearity errors of the D/A converter.