JPH1049307A - A/d conversion device and d/a conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly decrease required storage capacity, obtain small-sized, lightweight constitution, and lower manufacture cost without decreasing the processing speed of A/D or D/A conversion. SOLUTION: Only an error part e1 of bits less than a prescribed number of bits of digital data b1 consisting of the prescribed number of bits outputted to an A/D converter 11 is stored and held in an error value memory 12. Then this stored and held conversion error value is converted by an adder subtracter 13 of simple hardware constitution and then added to and subtracted from the digital data b1 having the prescribed number of bits to obtain correct digital data c1 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an A / D converter for converting input analog data into digital data and a D / A converter for converting input digital data into analog data.

[0002]

2. Description of the Related Art In an information processing apparatus such as a computer for performing various types of information processing, generally, data to be processed is digital data. Therefore, when performing information processing on a physical quantity such as a measured value, it is necessary to convert the measured analog data into digital data having a prescribed number of bits that can be processed by the information processing apparatus. Also,
It is necessary to convert the digital operation result to the original analog data as needed.

A / D used for such data conversion
In the converter or the D / A converter, a number of reference resistors and a number of voltage comparators corresponding to a reference voltage source and resolution are incorporated. In some cases, a large number of window comparators may be incorporated. The number of built-in reference resistors, voltage comparators and window comparators corresponds to the resolution of the converter. That is, it corresponds to the number of bits of digital data input / output.

In a factory that manufactures such an A / D converter and a D / A converter, before shipping the product,
The output voltage and the resistance value of each electronic component described above are adjusted so as to be correctly converted, and the quantization error in the converted data is controlled to be equal to or less than a predetermined allowable limit.

However, the A / D converter and the D / A
The number of the above-described electronic components incorporated in the conversion device is enormous. For example, when the number of bits of digital data to be input / output is 8 bits, it is necessary to divide the analog voltage into 2 ⁸ (= 256) in each converter. Therefore, an enormous amount of labor and time are required for the adjustment work.

In order to avoid such inconvenience, it is conceivable to improve the accuracy of each electronic component to be incorporated. However, electronic components having high accuracy are very expensive, and the manufacturing cost of the entire conversion device increases significantly.

In order to eliminate such inconvenience, for example, the above-described fine adjustment of the A / D converter itself incorporated in the A / D converter is omitted, and the A / D converter after the conversion by the A / D converter is omitted. An A / D converter for correcting digital data has been proposed.

That is, in the A / D converter shown in FIG. 5, a correction memory 2 is provided at a stage subsequent to the A / D converter 1. When the analog data a is applied to the input terminal IN, the A / D converter 1 converts the analog data a into, for example, 8-bit digital data b having a specified number of bits and outputs the data from the data terminals D0 to D7. I do. The 8-bit digital data b output from the data terminals D0 to D7 is applied to the address terminals A0 to A7 of the correction memory 2 as address values.

[0009] The correction memory 2, as shown in FIG. 6, the respective regions 2a corresponding to 2 ⁸ each address value that can be specified by the address terminals A0 ~ A7, wherein A of the corresponding digital data b The corrected digital data c which is correct digital data corrected by the / D converter 1 is stored.

[0010] Specifically, for example separately, two ^eight reference voltage of the analog is applied to the A / D converter 1 with a reference voltage generator, is output from the A / D converter 1 at that time Correct digital data is written into the area of the address value corresponding to the digital data as corrected digital data c using a separate data writing device. Correction memory 2 in this case
Requires a storage capacity of [2 ⁸ × 8] bits.

Therefore, the input analog data a
Is converted into digital data b having a prescribed number of bits by the A / D converter 1 and then replaced by the correct corrected digital data c corresponding to the digital data b in the correction memory 2 to the outside. Is output.

In the A / D converter shown in FIG. 7, instead of the correction memory 2 in the A / D converter shown in FIG. 5, a control unit 3 having an arithmetic processing function such as a CPU and a correction parameter memory are used. 4 are incorporated.

The correction parameter memory 4 stores correction parameters for correcting the digital data b output from the A / D converter 1 to correct digital data c by the arithmetic processing in the control unit 3.

Next, the correction parameters will be described. FIG.
FIG. 3 is a diagram illustrating a relationship between an analog input value x and a digital output value y in a general A / D converter. The theoretical conversion characteristic without any conversion error is y = x as shown by the solid line. However, due to variations in the characteristic value of the reference voltage source and each reference resistor, the actually measured conversion characteristic y ₁ = Ax +
B does not match the theoretical conversion characteristic y = x as shown by the broken line.

Therefore, the theoretical conversion characteristic y at the lower limit value x _min and the upper limit value x _{max at} the analog input value x is
each offset error y in the digital output value y from x
_OFF1 and _yOFF2 and gain error E _G = A are previously written in the correction parameter memory 4 as correction parameters as correction parameters.

[0016] In the control unit 3, correction program for correcting the digital data b using the respective correction parameters is y _OFF1, y _OFF2, E _G is incorporated. Therefore, the analog data a input from the outside is first converted into digital data b having a prescribed number of bits by the A / D converter 1 and then corrected by the control unit 3 to correct digital data c using a correction program. Output to the outside.

[0017]

However, the A / D converter shown in FIGS. 5 and 7 still has the following problems to be solved. In the A / D converter shown in FIG. 5, the storage capacity required of the correction memory 2 is A
Assuming that the resolution of the / D converter (the number of bits of the digital data after conversion) is n, the number of bits is [2 ⁿ × n] bits, which significantly increases the manufacturing cost. For example, about 2K for 8 bits
A bit is needed. In recent years, the resolution of data handled by the information processing apparatus has tended to increase from 8 bits to 16 bits, so that the storage capacity required by the correction memory 2 has increased dramatically, and the manufacturing cost has increased significantly. is there.

In the A / D converter shown in FIG. 7, the digital data converted by the A / D converter 1 is converted into a digital signal by the control unit 3 using a complicated correction formula by software means such as a program. Since the correction is performed each time, the conversion processing speed of the A / D converter is reduced, and the information processing efficiency of the entire information processing apparatus incorporating the A / D converter is reduced.

In the D / A converter for converting digital data into analog data, almost the same problems as those in the above-described A / D converter occur. The present invention has been made in view of such circumstances, and A / D
By storing and holding only the error portion of the digital data of the specified number of bits input / output to / from the converter or the D / A converter, the conversion processing speed is not reduced.
It is an object of the present invention to provide an A / D converter and a D / A converter that can significantly reduce the required storage capacity, are small and lightweight, and can reduce manufacturing costs.

[0020]

In order to solve the above problems, an A / D converter according to the present invention converts an input analog data into a digital data having a specified number of bits and outputs the digital data. Digital data of a prescribed number of bits output from the A / D converter is applied to the address terminal as each address value, and the A of the corresponding digital data is assigned to each area specified by each address value. / D
An error value memory for storing and holding each conversion error value in the converter with a smaller number of bits smaller than the specified number of bits, digital data of a specified number of bits output from the A / D converter,
An adder / subtractor for adding / subtracting a conversion error value of a small number of bits corresponding to the digital data read from the error value memory and outputting the corrected digital data having a prescribed number of bits to the outside;

According to another aspect of the present invention, there is provided a D / A converter for converting digital data having an applied prescribed number of bits into analog data and outputting the same to the outside, and a prescribed number of inputted bits. Is applied as an address value to an address terminal, and the D / D of the corresponding digital data is applied to each area designated by the address value.
An error value memory for storing and holding each conversion error value in the A converter with a smaller number of bits smaller than the specified number of bits, digital data of the specified number of bits, and corresponding digital data read from the error value memory. An adder / subtractor for adding / subtracting a conversion error value of a small number of bits and applying the corrected digital data having a prescribed number of bits to a D / A converter.

In the A / D converter configured as described above, the error value memory has a prescribed number of corrected bits for each digital data converted from analog data by the A / D converter. Not the right digital data,
Only the conversion error value of a smaller number of bits than the specified number of bits for the correct digital data is stored and held.
Therefore, the required storage capacity can be reduced.

The input analog data is first converted into digital data having a specified number of bits by an A / D converter. Then, the digital data and the conversion error value of the digital data read from the error value memory are added and subtracted, and finally output to the outside as corrected digital data having a specified number of bits.

Since the adder / subtracter for adding / subtracting the digital data of a prescribed number of bits and the conversion error value of a small number of bits can be constituted by a simple hardware component such as a gate array, the processing speed does not decrease.

As a result, the required storage capacity can be greatly reduced without lowering the conversion processing speed. Further, in the D / A converter of the present invention, the error value memory stores, for each digital data converted into analog data by the D / A converter, correct digital data having a specified number of bits after correction. Instead, only the conversion error value of a smaller number of bits than the specified number of bits for the correct digital data is stored and held. Therefore, similarly to the A / D converter described above, the required storage capacity can be reduced.

The conversion error of the input digital data having the specified number of bits in the D / A converter is read out from the error value memory, and is added to or subtracted from the original digital data to obtain D.
/ A converter. That is, the digital data of the specified number of bits corrected in the reverse direction in anticipation of the conversion error in the D / A converter is applied to the D / A converter. As a result, the corrected analog data is output from the D / A converter.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of an A / D converter according to a first embodiment.

[0028] The A / D converter 10 mainly includes a conventional A / D converter 11 which is composed of a reference voltage source and a plurality of reference resistors and a plurality of voltage comparators, etc., for example, E ²
It comprises an error value memory 12 formed of a PROM or the like, and an adder / subtractor 13 formed of one hardware component such as a gate array.

When the analog data a ₁ is externally applied to the input terminal IN, the A / D converter 11 converts the analog data a ₁ into, for example, 8-bit digital data b ₁ having a specified number of bits. , And output from the data terminals D0 to D7. With this 8-bit output from the data terminal D0 -D7 digital data b ₁ is applied to the data terminal D0 -D7 of the input terminal A of the adder-subtractor 13, the address value to the address terminals A0 ~ A7 of the error value memory 12 Is applied.

[0030] The error value memory 12, as shown in FIG. 2, each region 12a corresponding to 2 ⁸ each address value that can be specified by the address terminals A0 ~ A7, the corresponding digital data b ₁ A conversion error value e ₁ represented by a small number of bits 4 smaller than the specified number of bits 8 in the A / D converter 11 is stored.

[0031] Specifically, for example, are output separately, two ^eight reference voltage of the analog with a reference voltage generator is applied to the A / D converter 11, the A / D converter 11 at that time that is calculated by using separate example an error calculation unit 14 comprising a computer conversion error value e ₁ between the digital data b ₁ and right 8-bit digital data corresponding to the applied reference voltage.

The error calculator 14 writes the calculated 4-bit conversion error value e ₁ into each area 12 a of the error value memory 12 corresponding to each digital data b ₁ using the ROM writer 15. When the process of writing each conversion error value e ₁ into each area 12 a of the error value memory 12 is completed, the A / D converter 10 is removed from the ROM writer 15.

[0033] Thus, when the digital data b ₁ error value memory 12 is output from the A / D converter 12 to the address terminals A0 ~ A7 are applied, the data terminal D0 to D3
Outputs a 4-bit conversion error value e ₁ corresponding to the digital data b ₁ . Conversion error value e ₁ of 4 bits output from the error value memory 12 is applied to the low-order 4 bits of the data terminals D0 to D3 of the data terminals D0 -D7 of the input terminal B of the adder-subtracter 13.

An adder / subtractor 13 formed of one hardware component such as a gate array has data terminals D0 to D at an input terminal A.
7 digital data b having a specified number of bits applied to 7
_By adding, for example, ₁ and the conversion error value e1 of the small number of bits 4 applied to the data terminals D0 to D3 of the lower 4 bits of the input terminal B, correct digital data having the specified number of bits 8 is obtained and output. outputs as digital data c ₁ corrected from each data terminal D0 -D7 end C.

Therefore, the input analog data a
₁ is _first converted into digital data b ₁ having a prescribed number of bits by the A / D converter 11 and then corrected by the adder / subtractor 13 to correct corrected digital data c ₁ corresponding to the digital data b _1. Output to the outside.

The A / D converter 10 thus configured
, The A / D converter 1 is stored in the error value memory 12.
For each digital data b ₁ converted from the analog data a _{1 by} 1, instead of the correct digital data having the corrected specified number of bits 8, the digital data b ₁ has a smaller number of bits 4 smaller than the specified number 8 of the correct digital data. only conversion error value e ₁ is stored and held. Therefore, the required storage capacity can be reduced.

Generally, the conversion error rate (%) of each digital data b ₁ output from the A / D converter 11 with respect to the correct digital data is determined by the above-mentioned electronic components incorporated in the A / D converter 11. However, even if it is a cheap general part, it does not exceed 5%.

When the conversion error rate of 5% is converted into the number of bits of digital data having a specified number of bits of 8, for example, the absolute error amount is as follows. 2 ⁸ × 0.05 = 256 × 0.05 = 12.8 This 12.8 is a maximum of 13 when represented by an integer, and is a maximum of 13
Can be represented by 4 bits, so that the storage capacity required by the error value memory 12 is reduced by the required amount of the conventional correction memory 2 shown in FIG. Storage capacity can be reduced by about half.

As the required resolution of the A / D converter 10 increases from 8 bits to 16 bits and further to 32 and 64, the storage capacity that can be saved increases, and the manufacturing cost of the entire A / D converter 10 decreases. Further savings can be made.

Also, digital data b ₁ of a specified number of bits
Since the adder / subtractor 13 for adding / subtracting the conversion error value e ₁ of a small number of bits can be constituted by a single hardware component of a simple gate array, the operation processing speed does not decrease.

As a result, the required storage capacity of the A / D converter 10 as a whole can be greatly reduced without lowering the conversion processing speed. Note that the present invention relates to the first
It is not limited to the embodiment. In the first embodiment, the specified number of bits is set to 8, but the A / D converter 1
It can be set arbitrarily according to the resolution required as 0.

Further, the number of bits of each conversion error e ₁ set in the error value memory 12 is not limited to four. It can be changed according to the conversion error rate (%) of the A / D converter 11. For example, if the conversion error rate (%) is 1
In the case of%, 2 bits are sufficient. In this case, the required storage capacity can be further reduced.

(Second Embodiment) FIG. 3 is a block diagram showing a schematic configuration of a D / A converter according to a second embodiment of the present invention.

The D / A converter 20 is roughly divided into an ordinary D / A converter 21 composed of a reference voltage source and a plurality of reference resistors, and an error formed by, for example, an E ² PROM. It comprises a value memory 22 and an adder / subtractor 23 formed of one hardware component such as a gate array.

The D / A converter 21 has data terminals D0 to D7.
8 bits of digital data c having the prescribed number of bits
_{When 2} is applied, the digital data c ₂ is converted into analog data a ₂ and output from the output terminal OUT to the outside.

On the other hand, the digital data b ₂ having a specified number of bits of 8 inputted from the outside is applied to the data terminals D 0 to D 7 of the input terminal A of the adder / subtractor 23 and the address terminal A 0 of the error value memory 22. To A7 as an address value.

[0047] The error value memory 22, as shown in FIG. 4, the respective regions 12a corresponding to 2 ⁸ each address value that can be specified by the address terminals A0 ~ A7, the corresponding digital data b ₂ A conversion error value e ₂ represented by a smaller number of bits 4 smaller than the specified number of bits 8 in the D / A converter 21 is stored.

[0048] Specifically, for example, are output separately, two ^eight digital reference voltage using the reference voltage generator is applied to the D / A converter 21, a D / A converter 21 at that time The conversion error value e ₂ between the digital data including an error of 8 bits corresponding to the analog data to be converted and the correct digital data of 8 bits previously applied is separately calculated using an error calculating device 24 composed of, for example, a computer. calculate.

The error calculation device 24 writes the calculated 4-bit conversion error value e ₂ into each area 22 a corresponding to each digital data b ₂ using the ROM writer 25. Incidentally, the writing process for each area 22a of the error value memory 22 for each conversion error value e ₂ is finished, D / A converter 20 is removed from the ROM writer 25.

Therefore, the error value memory 22 stores the digital data b input from the outside to the address terminals A0 to A7.
When ₂ is applied, and outputs the converted error value e ₂ of 4 bits corresponding from the data terminal D0 to D3 to the corresponding digital data b _2. Converting the error value e ₂ of 4 bits output from the error value memory 22, the lower 4 bits of the data terminals D0 ~ of the data terminals D0 -D7 of the input terminal B of the subtracter 23
D3.

The adder / subtractor 23 formed of one hardware component such as a gate array has data terminals D0 to D at the input terminal A.
7 digital data b having a specified number of bits applied to 7
₂ and the input end lower 4 bits of a conversion error value e ₂ of a few number of bits that are applied to the data terminal D0 to D3 for example by adding the B, digital data c with a defined bit number 8
₂ is obtained and transmitted from the data terminals D0 to D7 of the output terminal C to the next data terminals D0 to D7 of the D / A converter 21.

The D / A converter 21 converts the input digital data c ₂ into analog data a ₂ and outputs it to the outside. Therefore, the input digital data b ₂ is calculated using the conversion error value e ₂ stored in the error value memory 22.
In subtracter 23, the digital data c ₂ which is previously corrected in the opposite direction in anticipation conversion errors in D / A converter 21. As a result, correct analog data a ₂ of the corrected from the D / A converter 21 is outputted.

The D / A converter 20 constructed as described above
In, the error value memory 22, for two ^eight respective possible values specified number of bits of the digital data b ₂ input, conversion error e in anticipation of the conversion error in the D / A converter 21 ² is stored. The number of bits required by the conversion error e ² is determined by the A / D converter 10
Is at most 4 bits, like the conversion error e ^{1 of}

Therefore, the A / D converter 1 shown in FIG.
Like 0, the required storage capacity of the error value memory 22 can be greatly reduced. Further, similarly to the adder / subtractor 13 of the A / D converter 10 shown in FIG. 1, the adder / subtractor 23 of the second embodiment can be constituted by one hardware component of a simple gate array, so that the arithmetic processing speed is reduced. I will not do it.

As a result, the required storage capacity of the D / A converter 20 as a whole can be greatly reduced without lowering the conversion processing speed. Also in the second embodiment, it is needless to say that can be changed to any value as needed number of bits defining the number of bits and a conversion error value e ^2.

[0056]

As described above, in the A / D converter and the D / A converter of the present invention, the prescribed number of bits output or input to the A / D converter or the D / A converter Only the error portion of the digital data of the number of bits smaller than the specified number of bits is stored and held in the error value memory,
The conversion error value stored and held by the adder / subtractor having a simple hardware configuration is added to or subtracted from the digital data having a specified number of bits after conversion or before conversion to obtain correct digital data or correct analog data. Therefore, the required storage capacity can be significantly reduced without reducing the conversion processing speed as a conversion device, and the conversion device can be formed small and lightweight.
In addition, manufacturing costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an A / D converter according to a first embodiment of the present invention;

FIG. 2 is a diagram showing storage contents of an error value memory incorporated in the A / D converter.

FIG. 3 is a block diagram showing a schematic configuration of a D / A conversion device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing storage contents of an error value memory incorporated in the D / A converter.

FIG. 5 is a block diagram showing a schematic configuration of a conventional A / D converter.

FIG. 6 is a diagram showing storage contents of a correction memory incorporated in the A / D converter.

FIG. 7 is a block diagram showing a schematic configuration of another conventional A / D converter.

FIG. 8 is a view showing a calculation procedure of a correction parameter stored in a correction parameter memory of the A / D converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... A / D converter 11 ... A / D converter 12,22 ... Error value memory 13,23 ... Adder / subtractor 20 ... D / A converter 21 ... D / A converter

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Tadano 5-10-27 Minamiazabu, Minato-ku, Tokyo Anritsu Corporation (72) Inventor Yoichi Maeda 3-9-1-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Inside Telegraph and Telephone Corporation (72) Inventor Seiichi Yamano 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Inside Telegraph and Telephone Corporation (72) Masaru Tsuchiya 3-192-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation

Claims (2)

[Claims] An A / D converter (1) that converts input analog data into digital data having a prescribed number of bits and outputs the digital data.
1), each digital data of a specified number of bits output from this A / D converter is applied to each address terminal as each address value, and each area of the corresponding digital data is assigned to each area designated by each address value. An error value memory (12) for storing and holding each conversion error value in the A / D converter with a smaller number of bits smaller than the specified number of bits; and a digital data of a specified number of bits output from the A / D converter. An adder / subtractor (13) for adding and subtracting a conversion error value of a small number of bits corresponding to the digital data read from the error value memory and outputting the result as corrected digital data having a specified number of bits to the outside. A / D converter provided. 2. A D / A converter (21) for converting applied digital data of a prescribed number of bits into analog data and outputting the same to the outside, and each digital data of a prescribed number of bits inputted to an address terminal. An error that is applied as an address value and stores and holds each conversion error value of the corresponding digital data in the D / A converter with a smaller number of bits than the specified number of bits in each area specified by each address value. Value memory
(22), the corrected digital data having the specified number of bits by adding and subtracting the input specified digital data of the specified number of bits and the conversion error value of the small number of bits corresponding to the digital data read from the error value memory. And an adder / subtractor (23) for applying the digital data to the D / A converter.