JPH01293557A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01293557A JPH01293557A JP12444588A JP12444588A JPH01293557A JP H01293557 A JPH01293557 A JP H01293557A JP 12444588 A JP12444588 A JP 12444588A JP 12444588 A JP12444588 A JP 12444588A JP H01293557 A JPH01293557 A JP H01293557A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- fusion
- semiconductor
- chips
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012768 molten material Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 15
- 238000003466 welding Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、半導体チップを銅張積層絶縁基板上または
電極板上に溶着させた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device in which a semiconductor chip is welded onto a copper-clad laminated insulating substrate or an electrode plate.
［従来の技術〕
第５図は、従来の半導体装置を示す平面図であり、第６
図は側面図である。放熱用の金属ベース板１の上面には
半田印刷が施されており、この金属ベース板１上に銅張
積層絶縁基板２が載せられている０この銅張積層絶縁基
板２の電極上には所定の箇所に半導体チップが裁せられ
、この半導体チップが載せられる部分には予め半田印刷
が施されている。[Prior Art] FIG. 5 is a plan view showing a conventional semiconductor device, and FIG.
The figure is a side view. Solder printing is applied to the upper surface of a metal base plate 1 for heat dissipation, and a copper-clad laminated insulating board 2 is placed on this metal base plate 1. On the electrodes of this copper-clad laminated insulating board 2, A semiconductor chip is cut at a predetermined location, and solder printing is applied in advance to the area on which the semiconductor chip is to be placed.
この半田印刷が施されている部分の上に、トランジスタ
チップ３、フライホイールダイオードチップ６およびス
ピードアップダイオードチップ５が載せられる。半導体
チップを載せた銅張積層絶縁基板２および金属ベース板
１の組合わせを加熱板上に載せるか、あるいは加熱炉中
に入れるかして加熱し、半田の溶着により各部分を溶着
させて固定する。なお、スピードアップダイオードチッ
プ５は、ダーリントントランジスタのスイッチング速度
を速くするために入れるダイオードチップである。また
、第５図および第６図において４はアルミワイヤを示し
ている。A transistor chip 3, a flywheel diode chip 6, and a speed-up diode chip 5 are placed on the solder printed portion. The combination of the copper-clad laminated insulating substrate 2 on which the semiconductor chip is mounted and the metal base plate 1 is heated by placing it on a heating plate or in a heating furnace, and each part is welded and fixed by solder welding. do. Note that the speed-up diode chip 5 is a diode chip inserted to increase the switching speed of the Darlington transistor. Further, in FIGS. 5 and 6, 4 indicates an aluminum wire.
［発明が解決しようとする課題］
しかしながら、このような従来の半導体装置では、加熱
して半導体チップを半田付けする際、半導体チップが半
田の表面張力により浮いて、その位置がずれ、傾斜して
半導体チップが固定されてしまうという問題点があった
。第７図の部分拡大平面図では、フライホイールダイオ
ードチップ６が傾いて固定されている状態を示している
。また第８図の部分拡大断面図では、スピードアップダ
イオードチップ５が傾いて固定されている状態を示して
いる。[Problems to be Solved by the Invention] However, in such conventional semiconductor devices, when a semiconductor chip is soldered by heating, the semiconductor chip floats due to the surface tension of the solder, shifts its position, and tilts. There was a problem that the semiconductor chip was fixed. The partially enlarged plan view of FIG. 7 shows a state in which the flywheel diode chip 6 is tilted and fixed. Further, the partially enlarged sectional view of FIG. 8 shows a state in which the speed-up diode chip 5 is tilted and fixed.
このように、半導体チップが所定の位置からずれ、傾い
て固定されると、後工程である自動ワイヤボンディング
装着によるボンディングが行ないにくくなったり、ある
いはボンディング強度が著しく低下するという問題を生
じる。この発明は、かかる従来の問題を解消するためな
されたもので、半導体チップが所定の位置からずれ、傾
いて固定されることを防止した半導体装置を提供するこ
とを目的としている。If the semiconductor chip deviates from a predetermined position and is fixed at an angle in this way, problems arise in that it becomes difficult to perform bonding by automatic wire bonding in the subsequent process, or the bonding strength is significantly reduced. The present invention has been made to solve such conventional problems, and it is an object of the present invention to provide a semiconductor device in which a semiconductor chip is prevented from shifting from a predetermined position and being fixed at an angle.
［課題を解決するための手段］
この発明の半導体装置では、金属ベース板と、金属ベー
ス板上に設けられる絶縁層または絶縁基板と、絶縁層ま
たは絶縁基板上に設けられる電極と、電極のうち所定の
電極上に溶着される半導体チップとを備え、半導体チッ
プが溶着される位置の近傍の電極部分に溝が形成されて
いることを特徴としている。[Means for Solving the Problems] In the semiconductor device of the present invention, a metal base plate, an insulating layer or an insulating substrate provided on the metal base plate, an electrode provided on the insulating layer or the insulating substrate, and a A semiconductor chip is welded onto a predetermined electrode, and a groove is formed in the electrode portion near the position where the semiconductor chip is welded.
［作用］
この発明の半導体装置では、半導体チップが溶着される
位置の近傍の電極部分に溝が形成されている。このため
、半田を溶融して溶着する際、溶融した半田は溝を越え
て流れず゛、従来のように半田が広がりその上の半導体
装置がそれとともに移動し位置ずれしてしまうというこ
とがない。[Function] In the semiconductor device of the present invention, a groove is formed in the electrode portion near the position where the semiconductor chip is welded. Therefore, when melting and welding the solder, the molten solder does not flow over the groove, and the semiconductor device above it does not spread and shift its position as in the conventional case. .
［実施例］
第１図は、この発明の一実施例を示す平面図であり、第
２図は、第１図の実施例の側面図である。[Embodiment] FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a side view of the embodiment of FIG. 1.
従来と同様に、放熱用の金属ベース板１の上面には予め
半田印刷が施されており、その上に銅張積層絶縁基板２
が載せられる。銅張積層絶縁基板２の上の電極部分の半
導体チップが載せられる部分には、予め半田印刷が施さ
れている。半田印刷の施されている部分の上に、トラン
ジスタチップ３、フライホイールダイオードチップ６お
よびスピードアップダイオードチップ５を載せ、加熱し
て１、 それぞれの部分を半田により溶着する。この後
ワイヤボンディング工程によりアルミワイヤ４を取付け
る。As in the past, the upper surface of the metal base plate 1 for heat dissipation is printed with solder in advance, and a copper-clad laminated insulating substrate 2 is placed on top of it.
will be posted. Solder printing is applied in advance to the electrode portion of the copper-clad laminated insulating substrate 2 on which the semiconductor chip is placed. A transistor chip 3, a flywheel diode chip 6, and a speed-up diode chip 5 are placed on the solder-printed part, heated, and then each part is welded with solder. After this, aluminum wire 4 is attached by a wire bonding process.
従来の半導体装置と異なる部分は、スピードアップダイ
オードチップ５およびフライホイールダイオードチップ
６が溶着される位置の近傍の電極部分に溝７〜１２が形
成されていることである。The difference from conventional semiconductor devices is that grooves 7 to 12 are formed in the electrode portions near the positions where the speed-up diode chip 5 and the flywheel diode chip 6 are welded.
第３図には、第１図に示す実施例のフライホイールダイ
オードチップ６の近傍を部分拡大平面図で示す。第３図
に示されるように、フライホイールダイオードチップ６
のまわりには、銅の部分を切欠いて形成した溝７および
銅の部分をくりぬいて形成した満８が設けられている。FIG. 3 shows a partially enlarged plan view of the vicinity of the flywheel diode chip 6 of the embodiment shown in FIG. As shown in FIG. 3, the flywheel diode chip 6
A groove 7 formed by cutting out the copper part and a groove 8 formed by hollowing out the copper part are provided around the .
半田溶着させるため加熱した際、溶融した半田はこの満
７．８を越えて流れ出すことがないため、フライホイー
ルダイオードチップ６は位置ずれすることなく半田溶着
により固定される。When heated for solder welding, the molten solder does not flow out beyond this 7.8 mm, so the flywheel diode chip 6 is fixed by solder welding without shifting its position.
第４図は、第１の実施例のスピードアップダイオードチ
ップ５の近傍を示す部分拡大平面図である。スピードア
ップダイオードチップ５が溶着される位置の近傍の電極
部分には銅の部分を切欠いて形成された溝９〜１２が設
けられている。スピードアップダイオードチップ５を半
田溶着により電極上に固定するため加熱した際、溶融し
た半田は溝９〜１２を越えて流れ出ることなく、このた
めスピードアップダイオードチップ５は位置ずれするこ
となく電極に固定される。FIG. 4 is a partially enlarged plan view showing the vicinity of the speed-up diode chip 5 of the first embodiment. Grooves 9 to 12 formed by cutting out the copper portion are provided in the electrode portion near the position where the speed-up diode chip 5 is welded. When the speed-up diode chip 5 is heated to be fixed on the electrode by solder welding, the molten solder does not flow out beyond the grooves 9 to 12, and therefore the speed-up diode chip 5 is fixed on the electrode without shifting. be done.
この実施例では、金属ベース板上に設けられた銅張積層
絶縁基板を例示して説明したが、たとえば、メタライズ
絶縁基板の上に金属電極板を載せた場合にも、金属電極
板に同様の溝を形成することにより、この実施例と同様
の効果が得られる。In this example, a copper-clad laminated insulating substrate provided on a metal base plate was explained as an example, but for example, when a metal electrode plate is placed on a metallized insulating substrate, a similar method can be applied to the metal electrode plate. By forming the grooves, the same effects as in this embodiment can be obtained.
［発明の効果］
以上説明したように、この発明の半導体装置では、小片
の半導体チップが溶着される位置の近傍の？！！極部骨
部分が形成されているため、加熱して半導体チップを溶
着させる際、溶着のための溶融物は半導体チップ周辺の
溝を越えることができず、このため溶融物上に載ってい
る半導体チップは位置ずれを生じることがない。したが
って、この半導体装置では、半導体チップが傾いて固定
されることなく、後工程におけるワイヤボンディングが
容易となり、かつ信頼性の高いボンディングを行なうこ
とができる。[Effects of the Invention] As explained above, in the semiconductor device of the present invention, a small piece of semiconductor chip is welded in the vicinity of a position where a small piece of semiconductor chip is welded. ! ! Due to the formation of the extreme ribs, when welding the semiconductor chip by heating, the molten material for welding cannot cross the groove around the semiconductor chip, and therefore the semiconductor placed on the molten material cannot The chip will not be misaligned. Therefore, in this semiconductor device, the semiconductor chip is not fixed in an inclined manner, making wire bonding easy in the subsequent process, and making it possible to perform highly reliable bonding.
第１図は、この発明の一実施例を示す平面図である。第
２図は、第１図の実施例の側面図である。
第３図は、第１図の実施例のフライホイールダイオード
チップの近傍を示す部分拡大平面図である。
第４図は、第１図の実施例のスピードアップダイオード
チップの近傍を示す部分拡大平面図である。
第５図は、従来の半導体装置を示す平面図である。
第６図は、同じ〈従来の半導体装置を示す側面図である
。第７図は、従来の半導体装置のフライホイールダイオ
ードチップの近傍を示す部分拡大平面図である。第８図
は、従来の半導体装置のスピードアップダイオードチッ
プの近傍を示す部分拡大平面図である。
図において、１は金属ベース板、２は銅張積層絶縁基板
、３は半導体トランジスタチップ、４はアルミワイヤ、
５はスピードアップダイオードチップ、６はフライホイ
ールダイオードチップ、７〜１２は溝を示す。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a plan view showing an embodiment of the present invention. 2 is a side view of the embodiment of FIG. 1; FIG. 3 is a partially enlarged plan view showing the vicinity of the flywheel diode chip of the embodiment shown in FIG. 1. FIG. FIG. 4 is a partially enlarged plan view showing the vicinity of the speed-up diode chip of the embodiment shown in FIG. FIG. 5 is a plan view showing a conventional semiconductor device. FIG. 6 is a side view showing the same conventional semiconductor device. FIG. 7 is a partially enlarged plan view showing the vicinity of a flywheel diode chip of a conventional semiconductor device. FIG. 8 is a partially enlarged plan view showing the vicinity of a speed-up diode chip of a conventional semiconductor device. In the figure, 1 is a metal base plate, 2 is a copper-clad laminated insulating substrate, 3 is a semiconductor transistor chip, 4 is an aluminum wire,
5 is a speed-up diode chip, 6 is a flywheel diode chip, and 7 to 12 are grooves. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
縁層または絶縁基板と、前記絶縁層または絶縁基板上に
設けられる電極と、前記電極のうち所定の電極上に溶着
される半導体チップとを備え、樹脂封止される半導体装
置において、 前記半導体チップが溶着される位置の近傍の前記電極部
分に溝が形成されていることを特徴とする、半導体装置
。[Scope of Claims] A metal base plate, an insulating layer or an insulating substrate provided on the metal base plate, an electrode provided on the insulating layer or insulating substrate, and a metal base plate welded onto a predetermined electrode among the electrodes. What is claimed is: 1. A semiconductor device which is resin-sealed and includes a semiconductor chip, wherein a groove is formed in the electrode portion near a position where the semiconductor chip is welded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124445A JPH07120680B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124445A JPH07120680B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01293557A true JPH01293557A (en) | 1989-11-27 |
| JPH07120680B2 JPH07120680B2 (en) | 1995-12-20 |
Family
ID=14885688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63124445A Expired - Lifetime JPH07120680B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120680B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021044452A (en) * | 2019-09-12 | 2021-03-18 | 富士電機株式会社 | Semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58106942U (en) * | 1982-01-13 | 1983-07-21 | セイコーエプソン株式会社 | Circuit board for wire bonding |
| JPS60194552A (en) * | 1984-03-16 | 1985-10-03 | Nec Corp | Hybrid ic device |
| JPS60200546A (en) * | 1984-03-26 | 1985-10-11 | Hitachi Ltd | Semiconductor device |
| JPS61136579U (en) * | 1985-02-14 | 1986-08-25 | ||
| JPS6289141U (en) * | 1985-11-25 | 1987-06-08 | ||
| JPS6346844U (en) * | 1986-09-16 | 1988-03-30 |
-
1988
- 1988-05-20 JP JP63124445A patent/JPH07120680B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58106942U (en) * | 1982-01-13 | 1983-07-21 | セイコーエプソン株式会社 | Circuit board for wire bonding |
| JPS60194552A (en) * | 1984-03-16 | 1985-10-03 | Nec Corp | Hybrid ic device |
| JPS60200546A (en) * | 1984-03-26 | 1985-10-11 | Hitachi Ltd | Semiconductor device |
| JPS61136579U (en) * | 1985-02-14 | 1986-08-25 | ||
| JPS6289141U (en) * | 1985-11-25 | 1987-06-08 | ||
| JPS6346844U (en) * | 1986-09-16 | 1988-03-30 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021044452A (en) * | 2019-09-12 | 2021-03-18 | 富士電機株式会社 | Semiconductor device |
| US11552065B2 (en) | 2019-09-12 | 2023-01-10 | Fuji Electric Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120680B2 (en) | 1995-12-20 |
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