JPH01293556A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the mounting density of a semiconductor device such as a memory device, etc., by connecting the bump electrodes of a semiconductor chip to leads, and connecting the plurality of the chips having the leads to the interconnections of a module board to compose a semiconductor device. CONSTITUTION:The bump electrodes 6 of a semiconductor chip 4 are connected to leads 5, and a plurality of semiconductor chips 4 having the leads 5 are connected to the interconnections of a module board 1 to compose a semiconductor device. For example, eight semiconductor chips 4A to 4D are mounted on the front and rear faces of the board 1 composed by laminating a plurality of ceramic and interconnecting layers. The chips 4A to 4D are not sealed by a package made of ceramics, resin, etc., but the side provided with semiconductor elements and interconnections is molded with resin 7. Bump electrodes 6 are provided on the chips 4A to 4D, and the leads 5A to 5D are connected to the electrodes 6 by TABs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device configured by modularizing semiconductor chips and mounting a plurality of semiconductor chips on a module substrate.

Furthermore, the present invention relates to a technology for stacking tape carriers.

[Conventional technology]

A semiconductor device with high packaging density, which is created by mounting multiple packages with sealed semiconductor chips on a mounting board (module board), is published by Nikkei McGloch Hill, Nikkei Electronics Special Edition, -2 "i-iku". Four Devices J
p150.

One of the technologies for integrating semiconductor elements is the tape carrier method. This method uses a film carrier or T A
B (Tape Automated Bonding
) method. In this method, semiconductor elements are successively assembled into a resin tape with long tin rocket holes (/<-7 holes), and the tape carrier is used to arrange the electrodes of the semiconductor elements (chips). A lead pattern is formed on a resin film that has a sprocket hole and a device hole. It is manufactured through the steps of punching device holes, laminating copper foil, and forming a desired lead pattern using photoresist technology and etching technology.

An example of a document describing the tape carrier is Matsuf Glorer Hill Book Company Japan (
Me Graw-Hllll Book Company
Japan) Co., Ltd. 1983 Copyright l”VLS
ITECHNOLOGYJ p 558 is mentioned.

[Problem to be solved by the invention]

As a result of studying the semiconductor device, the present inventors discovered the following problems.

Since it is difficult to reduce the size of the package itself, it is difficult to increase the packaging density of semiconductor chips on a module board.

However, conventional tape carriers are manufactured in one type and have the same lead pattern, making it impossible to stack tape carriers of the same type and mount them on a mounting board.

Therefore, if high-density mounting is attempted, it is necessary to arrange tape carriers of the same type on the mounting board side by side, which complicates the layering on the surface of the mounting board such as a printed wiring board, and may lead to wire breakage. This makes it more likely to occur, reducing its reliability.

An object of the present invention is to increase the packaging density of semiconductor devices.

Another object of the present invention is to provide a high density memory device suitable for surface mounting.

Another object of the present invention is to provide a memory device that can be mounted at high density.

Another object of the present invention is to provide a high-density surface mounting technology that is well matched with TAB (tape automated bonding) technology.

Another object of the present invention is to provide a high-density packaging method that can utilize TAB technology.

Another object of the present invention is to provide a method for assembling a memory device that can simplify and save labor.

Another object of the present invention is to provide a memory module that can compactly mount a large number of mesori chips.

Another object of the present invention is to provide a multi-tipped lead composite which has good solderability during soldering.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to clear the issue]

A first summary of typical inventions disclosed in this application will be briefly described below.

That is, bank electrodes of semiconductor chips are connected with leads, and a plurality of semiconductor chips having leads are connected to wiring of a module board to form a semiconductor device.

Furthermore, a second summary of typical inventions disclosed in this application will be briefly explained below.

In the present invention, in a plurality of tape carriers at the same time,
Prepare a partially changed lead pattern for each tape carrier. This change is made, for example, only to read the chip select signal. Then, in step 5, the tape carrier whose lead pattern has been partially changed is stacked and mounted on a mounting board.

Furthermore, the outline of other inventions is as follows.

The semiconductor integrated circuit memory device has the following configuration. ,
(a) The substantially square or rectangular plate-shaped IIl and the second SRAM semiconductor chip have first and second main surfaces, respectively, and the main parts of the SRAM integrated circuit are formed on the main surfaces of the Ill, respectively. (b) a large number of electrode pads provided near a pair of opposing sides of the first main surface of each of the chips; (c) the first main surface of each of the chips; each chip select electrode pad provided near one of the pair of sides; (d) a number of metal sheets each having an inner end connected to the number of pads of each of the chips; (e) first and second leads made of metal sheets whose inner ends of the warp are connected to the chip select pad of each of the chips; (f) a second lead of the first chip; (g) an insulating member provided between the main surface of the second chip and the first main surface of the second chip that is close to the main surface in parallel with the main surface of the second chip; A heavy connection part in which the ends and their neighbors are connected in a manner that their extending directions are the same.

Furthermore, the outline of other inventions is as follows.

A method for assembling a semiconductor integrated circuit in which memory chips are connected via bank electrodes to a number of openings for mounting semiconductor chips provided along the center of a carrier tape, the above assembly method comprising the following steps. . :(a) 1st
．． A step of gang-bonding memory chips having the same or substantially the same pattern to the second carrier tape through bump electrodes: Here, the first step described above is performed. The second carrier tape has a large number of leads made of a metal sheet on each first main surface and in the chip mounting opening, and the lead patterns of the first and second tapes are arranged so that each chip Patterns other than the leads to be connected to the select terminal or an equivalent terminal are substantially the same or have the same pattern;
(b) Camp-bonding memory chips having the same or substantially the same pattern to each of the openings of the first and second carrier tapes via bump electrodes; (e) A second tape is superimposed so that the matching patterns overlap, and the leads of each of the openings extending in the superimposed manner are crimped to form a multi-tap lead complex consisting of the plurality of memory chips and a large number of leads. (d) A step of separating the composite from each of the tapes.

Furthermore, the present invention forms a 5OP (Small Act 2-in-Package)-like multi-memory tip-lead complex by bonding multiple memory leads together using TAB (Tape Automated Bonding) and using chips and leads. This makes it possible to realize high-density memory modules using surface mount technology.

[For production]

According to the first means described above, since the semiconductor chips are not sealed with a package, it is possible to increase the packaging density of the semiconductor chips on the module substrate.

According to the second means, as described above, a part of each lead pattern of the tape carriers to be stacked is changed so that stacking can be performed, so it is possible to stack the tape carriers, Therefore, high-density mounting is possible.
Wiring can also be simplified and reliability can be improved.

〔Example〕

(1) Embodiment 1 In this application, unless otherwise specified, those having the same function are indicated by the same number in the last two digits, and redundant explanation will be omitted as much as possible.

EMBODIMENT OF THE INVENTION Hereinafter, the process of Example 1 of this invention is demonstrated using drawings.

FIG. 1 is a plan view showing a schematic structure of the semiconductor device I of Example 1 of the present invention. The second factor is a side view showing the schematic structure of the semiconductor device. FIG. FIG. 1 is a front view showing a schematic configuration of the device.

In FIGS. 1 to 3, l is a module board constructed by laminating a plurality of layers of ceramic l and wiring layers using a multilayer ceramic, and each of the front and back sides of this module board has eight
It is equipped with semiconductor chips 4A, 4Bp 4C, and 4D. The semiconductor chips 4A, 4B, 4C, and 4D are, for example, configured static RAM, and are not sealed with a package made of ceramic or resin, and are equipped with semiconductor elements and wiring. It has a structure in which the surface is molded with resin 7.

K of each of the semiconductor chips 4A, 4B, 4C, and 4D is
A bump electrode 6 made of solder, gold, etc. is provided, and a T A B (Tape Autan) is provided on this bump electrode 6.
mt@d Bonding) leads 5A, 5B
, 5C, and 5D are connected to each other. The semiconductor chip 4A is stacked on the semiconductor chip 4B by connecting the sole leads 5A to the leads 5B of the semiconductor chip 4B by, for example, solder. That is, for example, a lead 5A for inputting an address signal to the semiconductor chip 4A is connected to a lead 5B for inputting an address signal to the semiconductor chip 4B. Similarly, the leads 5A for inputting and outputting data of the semiconductor chip 4A are the leads 5B for inputting and outputting data of the semiconductor chip 4B.
is connected to. That is, in each of the leads 5A and 5B, those having the same function are connected by, for example, solder. Each lead 5B is connected to the decoder 3 and the lead 2 through wiring (not shown) in the module board 1. However, the lead 5A for inputting the chip select signal to the semiconductor chip 4A is connected to the lead 3A of the decoder 3 without being connected to the lead 5B for inputting the chip select signal to the semiconductor chip 4B. There is. Also, lead 5
B1 is connected to a lead 3A different from the lead 3A to which the lead 5A is connected. 8 by decoder 3
One semiconductor chip 4A or 4B is selected from among the semiconductor chips 4A and 4B.

The semiconductor chip 4D is mounted on the semiconductor chip 4C by connecting each lead 5D of the semiconductor chip 4D to the lead 5C of the semiconductor chip 4C using, for example, solder. Each lead 5C is connected to the decoder 3 or the lead 2 through wiring within the module board 1. However, the lead 5D for inputting the chip select signal of the semiconductor chip 4D is connected directly to the lead 3A of the decoder 3 without being connected to the lead 5CI for inputting the chip select signal of the semicircular chip 4C. ing. Further, the lead 5C1 is connected to a lead 3A different from the lead 3A to which the lead 5D of the decoder 3 is connected. 8 semiconductor chips 4C, 4D by decoder 3
One semiconductor chip 4C or 4D is selected from among them.

The main surfaces of each of the semiconductor chips 4A, 4B, 4C, and 4D, that is, the surfaces on which semiconductor elements and wiring are provided, are molded with silicone rubber 7 or resin 7.

As explained above, without sealing with a package, TA
By configuring the semiconductor device by mounting the semiconductor chips 4A, 4B, 4C, and 4D to which the leads 5A, 5B, 5C, and 5D are connected at B on the module substrate 1, respectively,
Since the area occupied by one semiconductor chip 4A, 4B, 4C, 4D on the module board 1 can be reduced, many semiconductor chips 4A, 4B, 4 can be mounted on the module board 1.
C, 4D can be installed. That is, the packaging density of semiconductor devices can be increased.

Furthermore, by stacking the semiconductor chip 4A on the semiconductor chip 4B and stacking the semiconductor chip 4D on the semiconductor chip 4C, many semiconductor chips 4A can be stacked without increasing the size of the module board 1. , 4B, 4C, 4D
can be installed.

Next, a modification of the process of Example 1 will be described.

FIG. 4 is a perspective view of a part of the module board 1 for explaining a modification of I of the first embodiment.

As shown in FIG. 4, a semiconductor chip 4B may be further mounted on the semiconductor chip 4A. Reference numeral 5g is a lead of the semiconductor chip 4E, which is connected to the lead 5A. However, the leads 5E, for inputting the chip select signal to the semiconductor chip 4E, are the leads 5A, 5B.
, without connecting to leads 5A, 5B of decoder 3.
, is connected to three leads different from lead 3A to which it is connected. Although the back surface of the module substrate 1 is not shown, another semiconductor chip is similarly mounted on the semiconductor chip 4D on the back surface, so that three semiconductor chips are stacked.

FIG. 5 is a front view of the semiconductor device (2) of Example 1 of the present invention.

In FIG. 5, one terminal on the front surface of the module board 10 is a connection terminal, and IB is a connection terminal on the back surface. In this embodiment, semiconductor chips 4B and 4 are provided on the surface of the module substrate 1.
Three pieces A and 4E form one set, and four sets are arranged.

Similarly, on the back side, four sets of three semiconductor chips 4C, 4D, and 4F are arranged.

Example (2) is semiconductor chips 4B, 4A, and 4E.

Leads 5A, 5B,
The lengths of 5B, 5C, 5D, and 5F are shortened.

The sixth factor is a side view of the semiconductor device (2) of Example 1 of the present invention, and FIG. 7 is a front view of the semiconductor device.

In the embodiment (2) of the present invention, the semiconductor chip 4A mounted on the front surface of the module substrate 1 has its back surface mounted on the module substrate 1.
The semiconductor chip 4C mounted on the back surface of the module board l has its main surface facing the module board l. By doing so, when the semiconductor device is viewed from the side of the semiconductor chip 4B, the leads 5B of the semiconductor chip 4B and the leads 5C of the semiconductor chip 4C have the same function.

The overlapping leads 5B and 5C having the same function are connected by through-hole wiring (through-hole wiring) 8 of the module board 1. In other words, each lead 5B is 1
Each book has a lead 5C that has the same function as its lead 5B.
For example, the lead 5B for inputting an address signal to the semiconductor chip 48 is connected to the lead 5C for inputting an address signal to the semiconductor chip 4C through the through wiring 8. Similarly,
Each lead 5B, which is a data output terminal of the semiconductor chip 4B, is connected to the semiconductor chip 4C through the through wiring 8.
It is connected to lead 5C, which is a data input/output terminal. However, the lead 5B for inputting the chip select signal of the semiconductor chip 4B and the lead 5C for inputting the chip select signal of the semiconductor chip 4C are not connected by the through wiring 8, and the lead 5B is It is connected to the decoder 3 provided on the surface of the module board 1, and the lead 5CL
is connected to the decoder 3 on the front surface of the module board 1. Here, the module board 1 in this embodiment has a single-layer structure made of resin such as glass epoxy, and has no wiring other than the through wiring 8 inside.However, the module board 1 Wirings connecting between the semiconductor chips 4B, 4C and the leads 20 or wirings connecting between the decoder 3 (not shown in FIGS. 6 and 7) and the semiconductor chips 4B, 4C are provided on the front and back surfaces of the . The through hole M8 provided with the through hole M8 is formed by drilling a through hole in the module board 1 using a drill or the like, and then plating the steel layer with gold using, for example, vapor deposition or electroless plating. .

As described above, by connecting the leads 5B and 50 of the same function with the through wiring 8, a single layer structure is achieved by eliminating any wiring other than the through wiring 8 in the module board 1. , the reliability of the module board 1 can be improved.

Further, by connecting the leads 5B and 50 having the same function with the through wiring 8, the number of wirings provided on the front and back surfaces of the module board 1 can be reduced.

It should be noted that the circuit board 1 and the wiring board m8 may be formed by laminated security. In this case, the wiring connecting the semiconductor chips 4B, 4C and the leads 2, the semiconductor chips 4B, 4C and the decoder 3 Wiring and the like for connecting are embedded in the module substrate 1. However, the number of these wirings is reduced due to the provision of the through wiring 8. For example, the semiconductor chip 4B on the surface of the board 10 is
Since it is only necessary to provide the wiring that connects to the wiring, the number of embedded wiring can be significantly reduced, and therefore, the reliability of the module board 1 can be increased.

FIG. 8 is a plan view of two semiconductor chips in Example 1 (■) of the present invention, and FIG. 9 is a plan view of two semiconductor chips shown in FIG. 8 facing each other and connected to the same lead. FIG. 10 is a side view of two semiconductor chips connected to the same lead as viewed from the direction .

In Embodiment 1 of the present invention, six bump electrodes are arranged sequentially from the upper left corner on the semiconductor chip 4A, and panda electrodes 6B having the same function as the bump electrodes 6A are arranged from the upper right corner on the semiconductor chip 4B. That is, the bump electrode 6A of the semiconductor chip 4A, -6AN-1e 6 A Hz S
ANTl”・SAN◆proof・6B of semiconductor chip 4B
,...68N-1t 6 B N・"68N"I
In e6BN+, those with the same suffix are bump electrodes with the same function. When stacked so that the main surface of the semiconductor chip 4B faces the main surface of the semiconductor chip 4A, the panda electrodes 6B, -68N-, .
68Nm 68N,,,68N+Reika, semiconductor chip 4
A bump electrode 6 At = 6 AN-s@6AN
# 6AN+1...6 so that it overlaps with AN+ the foot of the mountain,
The panda electrodes 6A and 6B are arranged symmetrically. These symmetrically arranged pant electrodes 6A, 6B are connected to the same board 5. However, the bump electrode 6A1 for inputting the chip select signals of the four semiconductor chips and the bump electrode 6B for inputting the chip select signal of the semiconductor chip 4B are shifted so that they do not overlap, and are connected to separate leads 5. Connected. 9 is an insulating material, which insulates the lead 5 to which the bump electrode 6A is connected from the semiconductor tip 4B, and also insulates the bump 'a% 6B,
The connected board 5 is insulated from the semiconductor chip 4A. Note that the leads 5 are molded into an appropriate shape after the semiconductor chips 4A and 4B are faced to each other and connected to the leads 5. Then, as a set of semiconductor chips 4A and 4B,
A plurality of modules are arranged on the front and back surfaces of the module board 10.

As described in 5 above, by arranging the bank electrodes 6A and 6B symmetrically and connecting them to the same lead 5, the packaging density of the semiconductor chips 4A and 4B on the module substrate 1 can be doubled.

As shown in FIGS. 11 and 12, when the bump electrodes 6A of the four semiconductor chips and the bump electrodes 6B of the semiconductor chip 4B are placed in symmetrical positions, that is, when the semiconductor chip 4B is stacked on the four semiconductor chips, Those bump electrodes 6A,
, 6B may be arranged so that they overlap, provided that the punctured electrodes 6A.

The lead 5 connected to the bump electrode 6B and the lead 5 connected to the bump electrode 6B are overlapped, but there is an insulating material 9 between them.
Insulate with. In addition, FIG. 11 is a plan view of two semiconductor chips 4A and 4B that are stacked on top of each other. In Figure 12, semiconductor chips 4A and 4B are connected to the same lead 5 facing each other,
It is a side view when it is seen from the direction of the semiconductor chip 4A.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

By configuring a semiconductor device by mounting multiple semiconductor chips with leads connected by TAB on a module board without sealing them with a package, one semiconductor chip occupies less space on the module board. Since the area can be reduced, many semiconductor chips can be mounted on a modular board. That is, the packaging density of semiconductor devices can be increased.

(2) Example 2 Next, a second embodiment of the present invention will be described based on the drawings.

The 13th prisoner is the principle color showing Embodiment 2 of the present invention, and the device hole 10 drilled in the plastic film tape.
A part of the lead pattern 102 formed on the film tape protrudes into the inside of the film tape 1 . Furthermore, among the lead patterns 102, the lead 102m at the right end in the figure is
On the 13th day, the remaining lead 102bK is installed in parallel, whereas! In FIG. 13 (G), the lead 102 at the right end in the figure is bent at a right angle.

A semiconductor element (not shown) is built into this device hole 101, and on the 13th day, the lead 102a at the right end in the figure is used for the chip select signal of the semiconductor element (Tep) built into the mt* device hole 101. In addition, in FIG. 130, the lead 102 bent at right angles at the end of the upper cloth similarly serves as a lead for a chip select signal.

FIG. 13 (Q conceptually shows how tape carriers in which some of the leads 102a of each lead pattern 102 are changed in this way are stacked and mounted, and the lead 102a at the right end in the diagram is The lead 102, which is in charge of the input/output of the chip select signal of the upper chip selected and adjacent to the lead 1021 at the right end in the figure, is
It is designed to control the input/output of the chip select signal of the lower chip mounted on the chip.

The other leads 102b serve as input/output terminals common to each chip. Figure 14 is! ! Figure 13 shows the details of the prisoner's deep carrier, and Figure 15 shows the details of the prisoner's deep carrier.
The details of the tape carrier are shown below.

As shown in these figures, plastic film tape 1
A plurality of sprocket holes 104 for feeding and positioning the tape 103 are provided at appropriate intervals on both ends of the tape 103, and a device hole for incorporating a semiconductor element is provided in the center of the tape 103. 101 is drilled, and a chip 105 is face-down bonded (guyang bonding) to the tip of the lead pattern 102 protruding into the device hole 101 as shown in the figure.
Join by.

This bonding is performed by forming a bang 108 on the electrode part of the chip 105 and using a thermocompression method.
You may form the bang 108 at 02m and perform the same process.
After the bonding (inner lead bonding) of the chip 105, as shown in the 169th cross-sectional view, sealing is performed by potting a sealing resin to form a resin seal 5107.

Tape carrier package 108 sealed in this way 5
are stacked and mounted on the mounting board 109 at step 5 as shown in FIG.

In FIG. 17, the upper tape carrier package 108a
is a tape carrier package having the lead pattern 102 shown on the 13th day, and the lower tape carrier package 108b is a tape carrier package having the lead pattern 102 shown in FIG. 13(6).

The plastic film tape used in the present invention is composed of, for example, a polyimide resin film slit to an appropriate width. The lead pattern 102 can be formed on the film tape using, for example, a double layer of steel foil, a photoresist technique, or an etching technique, and each tape carrier package 108 m, 1
08b, some of them will be changed accordingly.

The semiconductor element (chip) 105 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed in this chip by a well-known technique, and is an example of a zero-circuit element that is given one circuit function. consists of transistors (for example MOS), and these circuit elements form the circuit functions of one, for example a logic circuit and a memory.

The bump 106 is composed of, for example, a gold (Au) bump.

As the botting resin used for sealing, for example, a botting liquid mainly composed of epoxy resin is used.

The mounting board 109 is composed of, for example, a printed circuit board.

According to the present invention, as shown in the above embodiment, by changing the lead 102 of each lead pattern 102, two tape carrier packages 108m and 108
b can be stacked and mounted on the mounting board 109, and the tape carrier package 108 m can be temporarily mounted on the mounting board 109.

The packaging density can be improved compared to the case where the tape carrier packages 108b are arranged in parallel.
In the case of arranging 108b and 108b in parallel, the wiring is long and complicated, whereas the wiring is short and simple, and the rate of disconnection is reduced, which contributes to improved reliability.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is understood that changes can be made without departing from the gist of the invention. Needless to say.

For example, in the above embodiment, two tape carrier packages are mounted on the mounting substrate, but three or more tape carrier packages can be stacked, and if necessary, they can be mounted on both sides of the mounting substrate.

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, high-density packaging is possible in a tape carrier, and it is possible to provide a semiconductor package that is advantageous in terms of wiring and has improved reliability.

Margin below (3) Example 3 This example is a modification corresponding to Examples 1 and 2, and provides a further specific example.

FIG. 18 is an overall system circuit diagram of the memory module of this embodiment. In the same figure, RAM1~16#
``t1 each 256 kilobit SRAM (Static Random Access Memory) MOS type or BIMO8 (Bipolar-MOS) type integrated circuit chip,
C8 is their chip select terminal, Decode
rl and 2 are resin-sealed dual units for decoder integrated circuits.
In-line type element, l10i~■10. is the data input/output bin.

AO-A18 (or A0-A, 8) is an address input bin. WE, OR, and DS are a series of control bins. Among these, WE is light
The enable bin OE is an output enable bin, and DS is also commonly called KC8, but its function is different from the C8 terminal of the RAM chip. That is,
This DS terminal determines which of the upper and lower decoders is selected depending on the input 10'' and ``1''. Ve
CP V S l is a power supply terminal in a broad sense, and special KVc
c is a power supply voltage terminal*V 8 S is called a reference voltage terminal. A voltage of 5V is supplied to VccK, and a voltage of oV is supplied to VssK.

FIG. 19 is a layout of the first main surface of memory chips RAM1-16. In the same figure, A6 to AI4 are
Address pad, I10° to I10° are input/output pads, WE is write enable pad, OE is output enable pad, csh chip select pad* V CC is power supply voltage pad + VSS is reference Voltage pads, 211 and 212, peripheral circuit blocks such as address buffers and I10 buffers, 213
~216 is a memory mat having a 4-transistor MO8 type SRAM cell with a high resistance poly-Si load, 21
7 to 218 are X-system circuits such as Roku decoders etc. 0. the law of nature.

219-222 are Y-system circuit blocks including column decoders and sense amplifiers corresponding to 213-216, respectively. Note that 205 is a Si single crystal substrate.

FIG. 20 shows the bin arrangement of memory modules corresponding to the previous overall layerer)K.

FIGS. 21a, b, and c are a top view, a front view, and a side view of the above-mentioned menu/module. In the same figure, 2
09 is a laminated ceramic substrate, VCC-V in Fig. 18
The chip capacitor 232 connected between gs and 7 is a soldering pad for this chip capacitor.

233a and b are decoder ICs corresponding to decoding l and 2 in FIG. 18, respectively, and 234a is an RA in FIG.
Memory chip complex corresponding to MI and RAM5, 2
34b is the same as chip complexes #234C and 234d corresponding to RAM2 and RAM6. Furthermore, the same goes for 234C.

Chip complex corresponding to RAM9 and 13, 234f
~h is also the same as above. 235 is a metal lead soldered to the metallized pad on the side surface of the ceramic substrate, and corresponds to each pin in FIG. 20.

Figure 22 shows the polyimide used in the manufacturing method of the present invention.
Show tape. In the same figure, 201 is a device mounting hole (device hole) or bar 7
205 is the installation position of the 3i chip (memory chip), 2
04 is a tin rocket hole used for automatic feed or positioning button of carrier tape, 2 is isolation hole for separating common copper wiring on carrier tape into each unit tape section, 242 is polyimide thin plate It is laminated with a carrier tape on which a thin copper plate is formed into a predetermined shape by photolithography.

FIG. 23 shows RAM1 to 4 and RAM9 to 1 in FIG.
2, that is, an enlarged view of a unit part of the upper tape corresponding to FIG. 22 for mounting the upper chip. In the figure, 201 is a device hole, 204 is a sprocket hole, 205 is a chip mounting position, 2 is an isolation hole, 242 is a carrier tape, and 24 is an isolation hole.
3 is a wide steel bell), 244 is a copper lead provided on the tape, 245 is an outer lead and inner lead area made of thin steel plates, and 246 is an end extending from above the tape into the device hole. 247a is a steel lead for HC8, 248 is a copper plate, 249 is a test copper pad with 14 pads on each side of the tape, and other straight or broken thin wires are copper wiring patterns. be.

Figure 24 shows RAM5-8 and RAM13-1 in Figure 18.
FIG. 6 is an enlarged view of a unit part of the lower tape corresponding to FIG. 22 above, in which the lower chip is mounted. In the figure, 247b is a steel lead for C8, and the other patterns are exactly the same as in FIG. 23.

25-28 show a process flow for forming bump electrodes on memory chip 205. FIG. In the same figure, 20
5 is a Si single crystal substrate, 251 is an underlying inorganic substrate including an interlayer insulating film such as thermally oxidized Sin as a first pass-through film, and PSG (phos 7 silicate glass) as a second pass-through film. Insulating film, 254 is memory
A! which is identical to the AJ layer for interconnections inside the chip. AI bonding pad made by patterning a film,
252 is a 7-ainal consisting of Sin, or si, and N4.
Pudge page seal l1ll! , 253HPIQ (polyimide iso-indolo-quinazoline dione). 255 is the base metal layer and is made of TI (titanium).
256 is another base metal layer made of Pd (palladium). 257 is a photoresist layer for forming a bang, and 255 is an Au (gold) bump formed using the photoresist layer.

29 is a sectional view showing the next state after gang bonding the bump shown in FIG. 28 and the inner lead shown in FIGS. 23 and 24; FIG.

In the figure, 245 is the tip region of the copper inner lead;
259 is Ni (metal) plating layer, 260 is Au (gold)
Figure 30, which is the plating layer, shows the state shown in Figure 29 above, in which the resin encapsulant is potted almost over the entire surface of the chip, and the surrounding carrier.
FIG. 3 is a cross-sectional view shown in relation to the tape. In the same figure,
205 is a memory chip.

242 is the inner end of the carrier tape on the device hole side, 2
45 is actor lead part (cu7 ilm) t258
261 is an Au bump, and 261 is a sealing resin layer (epoxy resin).

FIG. 31 is a plan view of the tape carrier (upper side) divided into individual unit parts at the stage of FIG. 29. In the same figure, 14 Cu test pads were provided on each side of the 281 and 282 Fi carrier tapes.
The first major surface P 2628 and b of the first orifice of FIG.

Figure 32 shows a state in which the lower carrier tape corresponding to Figure 31 above has been separated so that only the essential parts of the unit parts remain.
It is a top view which shows m. In the same figure, 205b is the first
Upper l1l (first) main surface 1 262a and b of the lower chip corresponding to RAMs 5 to 8 and RAMs 13 to 16 in FIG.
is the upper and lower lead joining area #2 where the leads corresponding to the same part of the queen upper chip are crimped and joined so that they coincide and overlap.
84a and b are tin rocket holes.

Figures 338 and b show that the actor leads are thermocompression bonded to the chiabu tape composite of Figures 31 and 32, and then the outer leads are cut and separated near the inner edge of the device hole, and the outer leads are finally made into 5OP (small inner).・A bottom view and a cross-sectional view (A-A) of a multi-chip composite body bent and formed into a line package). In the figure, 205a and 205b are upper and lower chips, respectively (although they are upside down in this figure, they are referred to as such for the purpose of explaining the assembly method), and 245 is an outer lead that is overlapped and bent. e 2 4 7 a and b are not crimped by the C8 terminal leads of the upper and lower chips, respectively, and are individually shaped into the same shape as the other leads. 261. 261a and b are the first overly formed resin botting layers of each chip.

34 to 37 are cross-sectional flowcharts showing a process of mounting the multi-chip composite shown in FIGS. 331 and 331b on both sides of the laminated ceramic wiring board 209 as shown in FIG. 21 by soldering 70-.

In the same figure, 209 is a ceramic package board;
263 is the actor lead of the module, 264m-d is the multiple f-tube complex 234a-h and the decoder IC 233.
Seven prints consisting of metallized layers for soldering a and b.

265a-d are solder cream layers formed thereon by screen printing. 266 is an adhesive member for holding the multi-chip composite on the lower side during solder reflow. 267a-d are the solidified solder joints after being reflowed.

FIG. 38 is a sectional view showing the next state after the completed memory module is soldered and mounted on an insertion type printed wiring board by the solder wave method. In the figure, 271 is a glass epoxy wiring board, 273 is a bottle insertion hole, and 2
74 is a soldering pad, 272 is a soldering resist layer, and 275#i is a soldering portion.

Figures 39 to 39 are plan views of a chip/tape composite for explaining the above embodiment and its modifications. The patterns in Figures 39 and 40 are exactly the same as those in Figures 23 and 24, respectively.

FIG. 39 is a top view of the upper chip, ie, upper tip lead tape complex. In the same figure, % 204a to hFi sprocket holes, 205aFi upper memory chip,
247a upper chip C8 lead, 281 and 28
2Fi each 14 on each side of the carrier tape
Individually disposed Cu test pads 293 indicate portions where the leads of the upper and lower chips are pressed together and then separated and cut from the carrier tape.

FIG. 40 is a top view of the lower chip/tape composite.

In the figure, %284a-h are sprocket holes, and 205b is a lower memory chip.

247b is a lead for the C8 terminal of the lower chip; 291 and 292 are 14 test pads arranged on each side of the tape; and 293 is a cut region indicating the separation between the tape and the multi-chip composite.

In Figure 1, in order to explain the above embodiment, the upper and lower tapes are arranged so that the top and bottom patterns almost match! This is a top view for explaining an overlapping state assuming that the tapes are folded together, and only the portions of the lower tape that are different from the upper tape are shown. In the figure, 204a to 204h are tin rocket holes # 205a are the first main surface e of the top chip 2478
and b are upper and lower CS IJ-do, respectively, 293
is the cutting separation area between the multi-chip complex and the tape.

Next, the manufacturing process will be explained. First, prepare the upper and lower carrier tapes. A polyimide resin film/tape having a thickness of 125 μm is punched to form openings other than the isolation holes shown in FIGS. 23 and 24. Next, the wiring patterns shown in Figures 23 and 24 above were formed by etching a 35 μm thick copper foil, and the second wiring pattern was formed on the entire surface.
As shown in FIG. 9, Ni (metal) barrier layer 259 and A
U (gold) layers are formed by plating each having a thickness of 0.5 μm.

On the other hand, the memory chip process will be explained starting from the wafer process. As shown in FIG.
After forming 51, the internal interconnector was attacked!
Ki bonding pad (100μm square) at the same time as wiring
254 is formed. This Al film is deposited on the entire surface by sputtering to a thickness of about 1 μm, and then patterned by photophosphorography. Next, the inorganic final
Approximately 1.4 μm 0FSGl12, which is a pudge page attack
52t-CVD (chemical paper deposition)
Then, as before, an opening is formed by button photolithography. Next, apply 2 coats of polyimide coating liquid such as KPIO.
．． Spin coat to a thickness of about 3 μm. At this time,
When the surface of P2O,y film 252 is subjected to Al chelate treatment, polyimide film 253 and PSG film 2
52 has good adhesion. After polyimide coat,
Baking is performed to evaporate the solvent, and then an opening is formed in the polyimide film [7, Trisogera fiber] 10 μm wider than the previous opening, and then baking is performed for curing.

Furthermore, as shown in Fig. 26, the base barrier for the bump electrode
Metal Film, Nawachi, 0. i sμmo'r
i (f tan) 74 kA and 0.17 μm 0 Pd (palladium) films are formed by sequential vapor deposition.

Next, as shown in Fig. 27, a 20 μm thick laminate and dowel
7, Tresist (Laminated photo-r)
esist) 257 is pasted on the entire surface, and an opening is formed 10 μm wider than the underlying polyimide opening by etching. In this state, this opening is electroplated with Au (gold) with a thickness of about 203a. Form an Au (gold) panda electrode.

Next, as shown in FIG. 28, the photoresist film 257 is removed leaving the Au bumps 258.
Using the u-bump 258 as a mask, unnecessary portions of the UBM (underlying barrier metal) are removed by chemical etching or back sputtering. This completes the Au bump electrode.

Next, after an electrical test in the wafer state, the wafer is diced into individual chips (4
Divide into 25 mm x 10 mm x O, 25 mm). Here, the thickness was made to be 250 μm by back-etching and back-grinding before dicing.

Next, as shown in FIG. 29, the first main surface of the chip is placed at the position indicated by the broken line 205 in FIGS. 23 and 24, and the TAB bonding is heated from above.
Pressing the tool K from Au bump and lead 245
The Au plating layer 260 is bonded by thermocompression. This is a process called gang bonding.

Next, as shown in FIG. 30, with a large number of chips bonded to the long tape 242, a fluid epoxy resin is applied from above and cured.
An organic resin sealing layer 261 with a thickness of about 50 μm is formed. This sealing layer protects the surface of the chip 205 and can ensure the Au bumps 258 and leads 245 themselves and their bonding.

Next, as shown in FIGS. 39 and 40, aging and selection tests are performed on the upper TAB and lower TAB using test pads 281, 282, 291, and 292 in the long tape state.

Next, as shown in Figures 31 and 32, the upper and lower TAB
Divided into ft units, with upper and lower TABKs 262
Parts a and b can be overlapped by TAB on the upper and lower sides, 15KSO
Perform a 7-ohm mink of the lead in a P shape. In this case, the upper stage TAB is deformed so little that it can be made into a complete unit TAB state, but the lower stage TAB has a large amount of deformation, so the tape is divided near the outermost side of the actor lead.

Next, the sedge rocket holes 204a are used as alignment holes to overlap the leads so that the leads are in a positional relationship as schematically shown in the figure.
Bonding tool (tool load: 57
0-750 g/lead.

Tool temperature: 530-570℃, suppression time 21-5 seconds)
Press to heat and press the corresponding leads together.

Next, remove the carrier from the cutting area 293 in the figure.
Cutting the tape and tape lead composite
Therefore, separate. In this way, a multi-chip composite having a cross-sectional shape as shown in FIG. 33(b)K is completed.

34 to 37 show a mounting process on the memory module ceramic substrate 209 shown in FIG. 21.

First, a ceramic package substrate as shown in FIG. 34 is prepared. Typical sizes for ceramic packages are: Length: 4011111r Width: 15m Thickness 2 rm P-lead (N'8") y Ki.

42 alloy) 263 pitch: 2.54 am.

The material is a multilayer wiring board made of alumina ceramics.

Next, as shown in FIG. 35, solder cream layers 265aS-d are formed by screen printing on the metal 2 size foot prints 264-d on this substrate.

Next, as shown in FIG. 36, the actuator leads are placed on top and bottom of the substrate 209 so that the tips and their vicinity are in contact with the respective solder cream layers. The lower side is the adhesive body 266
Depending on the back surface, it may be necessary to adhere or adhere it.

Next, in the above state, the product is inserted into a glue furnace at about 220 DEG C., and soldering is performed as shown in FIG.

Further, as shown in FIG. 38, soldering is completed by applying a solder wave from below the printed circuit board 271 with the memory module inserted into the printed circuit board made of glass, epoxy, etc.

No. 42. i and brI! J is a bottom view and a BB sectional view of a multi-tipped lead composite according to another embodiment of the present invention. In the same figure, 205a and bFi upper and lower memory chips, 245 are leads (external leads) connected to pads other than C8 having the same function, 247
Jl and b are external leads connected to the upper and lower CS pins and pins, respectively.

261a and 261b are epoxy resin layers potted onto the device surfaces of the upper and lower chips. In the case of this example, the assembly process is almost the same as the example shown in FIG. It is also possible to bend and form the actor lead of the multi-tipped lead composite in the tape state with the other parts separated from the tape. This also applies to the SOP types mentioned above.

Although the present invention has been described above using a specific TAB method as an example with respect to FIGS. 18 to 42, the present invention is not limited thereto.

That is, the examples shown in FIGS. 18 to 42 are specific examples of the examples shown in FIGS. 1 to 17, and it goes without saying that the examples shown in FIGS. 18 to 42 are applicable to these examples.

Further, although only a double step-read complex has been described here, complexes of 3 to 5 times or more can be implemented in substantially the same manner.

Furthermore, module wiring boards are limited to ceramics4. As shown in the cited document below, glass and
Plastic substrates such as epoxy, printed, and wiring boards can be used.

Furthermore, the pressure contact between the outer leads of the upper and lower TABs is a long T.
This is possible even in the AB state, and can be performed with the outer lead being substantially flat.

Furthermore, in addition to the above, it goes without saying that various technical changes are possible, as shown in the cited documents below.

(4) Regarding literature, etc. to supplement the description of each example, 8RAM (state random access memory)
For details on the monolithic chip wafer process, device structure, system, etc., see U.S. Patent Application No. 899,404 (filed August 22, 1986), N1
875,674 (June 18, 1986), opening 764
, 208 (August 8, 1985), and U.S. Pat.
No. 554.279 and corresponding UK patent no. 2,092,8
No. 26, etc., so these constitute the description of the present application.

Regarding TAB (Tape Automated Bonding), for example, polyimide tape.

Regarding the copper metallization thereon, the method of forming bump electrodes for connecting the TAB inner leads to the semiconductor chip, the gang bonding of the TAB inner leads to the chip, the mounting method, and the sealing method, please refer to U.S. Patent Application No. 052, 386
(filed on May 21, 1987), Doden 946,951 (filed on May 21, 1987)
(filed on December 29, 1986), [Nikkei Electronics J November 27, 1978 issue, pages 197-211 (
Nikkei Electronics), same magazine 19
December 19, 1983 issue, pages 82 to 85, “Nikkei Micro Devices, October 1998 issue, pages 36 to 38
kkeiMicrodevices), same magazine 1987
February 1984 issue, pages 43-44; June 11, 1984 issue, pages 148-159; same issue, pages 130-147; same issue, pages 46-48; March 1986 issue, page 128. ～Page 135, “Solid State Technology J
March 1979 issue (Solid 5tate 'l'
ech-nologY) O pages 52-55, "Electronic Materials Co. (Denshi Zalryo) 198
September 7th issue 51-56 Jj, l"' Engineering vp)
o Nix J (Electron-fcs) 1986 8
Pages 74-76 of the 21st issue of the month.

“JETNe
ws) Volume 3, No. 2, April 1984, pp. 42-43, “
VLSI Technology J
ology) G 1F (Sze) 1983 0558X
~570 pages, “IC Mounting Technology” edited by Japan Microelectronics Association, published by Kogyo Kenkyukai Co., Ltd. 102
~175 pages, "Introduction to automatic assembly of electronic components" 1986 July
Since it is described on pages 90 to 100 of the Nikkan Kogyo Shimbun issue on March 30th, the description of the present application will be replaced with these.

Furthermore, regarding memory modules, "Nikkei Electronic
s) On pages 99 to 107 of the September 7, 1987 issue, there is an article titled ``Nikkei Micro
devices) June 11, 1984 issue 160-16
Since these are described on page 8, the description of the embodiments of the present application will be changed with these.

〔Effect of the invention〕

A brief explanation of the effects obtained by the first representative invention disclosed in this application is as follows.

Since the leads are connected with TAB without being sealed in a package and the semiconductor device is constructed by mounting multiple semiconductor chips on a module board, one semiconductor chip can be mounted on a module board. Since the area occupied can be reduced, many semiconductor chips can be mounted on the module board. That is, the packaging density of semiconductor devices can be increased.

A brief explanation of the effects obtained by the second typical invention disclosed in this application is as follows.

According to the present invention, it is possible to provide a semiconductor device that enables high-density mounting on a tape carrier, is advantageous in terms of wiring, and has improved reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to Example 1-1 of the present invention, FIG. 2 is a side view showing a schematic configuration of the semiconductor device, and FIG. FIG. 4 is a perspective view of a part of the module board 1 for explaining a modification of I of Example 1, and FIG. 5 is a front view showing the schematic configuration of the device. FIG. 6 is a side view of the semiconductor device of Example 1 of the present invention (■); FIG. 7 is a front view of the semiconductor device; FIG. 9 is a plan view of two semiconductor chips in the IVK of Example 1 of the present invention. FIG. 9 is a plan view of two semiconductor chips shown in FIG. 8 facing each other and connected to the same lead. Figure 10 is a side view of two semiconductor chips connected to the same lead, viewed from direction ■. Figure 11 is a side view of two semiconductor chips that are stacked together. FIG. 12 is a side view of the semiconductor chips 4A and 4B facing each other and connected to the same lead 5 when viewed from the direction I of the semiconductor chip 4A. . 13(A) to 0 are principle diagrams showing Embodiment 2 of the present invention, FIG. 14 is a plan view of essential parts showing Embodiment 2 of the present invention, and FIG. 15 is a diagram showing Embodiment 2 of the present invention. FIG. 16 is a sectional view showing Embodiment 2 of the present invention, and FIG. 17 is a sectional view showing Embodiment 2 of the present invention. FIG. 18 is a circuit block diagram showing the overall system of the memory module of the present invention, and FIG. 19 is a circuit block diagram showing the first chip of 8 RAM (static random access memory) of the multi-chip complex of the present invention.
Main surface circuit and bonding pad layout diagram; FIG. 20 shows the pins of the memory module of the present invention. 21(a) to 21(c) are top views, front views, and side views showing the external shape of the memory module of the present invention, and FIG. 22 is a plan view showing the global characteristics of the tape carrier of the present invention. Figures 23 and 24 are top views of unit parts of the tape carrier (upper stage TAB, lower stage TAB) of the present invention; Figures 25 to 28 are flow sectional views showing the wafer process of the SRAM chip of the present invention; Figure 29 is an enlarged cross-sectional view of the main part showing the state of gang bonding between the leads of the tape carrier and the bump electrodes of the chip. 31 is a top view showing the upper TAB divided into unit parts; FIG. 32 is a top view showing the lower TAB divided into unit parts; 33(a) and ( b) The figure shows the bottom view and A-A sectional view of the multiplex memory tip lead complex, and Figures 34 to 37 show the 5op (
Figure 38 is a cross-sectional flow diagram showing the surface mounting process flow for a multi-tipped lead composite and decoder IC manufactured by Small Outline Package (Small Outline Package). Figure 39 is a top view showing the upper TAB in a tentative state after gang bonding has been completed; Figure 40 is a top view of the similar lower TAB;
The top view showing the state where AB is stacked on the lower TAB, Figures 42(a) and 42(b) are the multi-step structure shown in Figure 33.
Other examples of lead complexes i.e. rose) IJ-do (
FIG. 2 is a bottom view and a sectional view showing the Butt Lead) type. In the figure, 1... module board, 2.3A, 5A. 5B, 5C, 5D, 5E, 5F...Lead, 3...
Decoder, 4A, 4B, 4C, 4D...Semiconductor chip, 6A, 6B...Bump electrode, 7...Silicone rubber or resin, 8...Through wiring, 9...Insulating material. Figure 4 Figure 5 * Figure 73(c1) Figure 73(b) Figure 13(
c) Figure 01b Figure 76 Figure 77 o U NC'J Figure 23 Figure 24 Figure 25 Figure '205 Figure 31 Figure 3
2rjgJl○ is)
284b Fig. 33(a) M 35 Fig. 36 Fig. 37 Fig. 38 Fig. 39 Fig. 204f 204b 2) 4g

Claims (1)

[Scope of Claims] 1. A semiconductor device configured by connecting bump electrodes of a semiconductor chip to leads, and connecting a plurality of semiconductor chips having the leads to wiring on a module board. 2. The semiconductor device according to claim 1, wherein the semiconductor chip is not sealed with a package. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on both the front and back surfaces of the module substrate. 4. The semiconductor device has a second semiconductor chip on top of the first semiconductor chip.
By stacking the semiconductor chips, leads that input or output the same signal or the same potential are connected to form a set of semiconductor chips, and a plurality of sets of semiconductor chips are mounted on the module board. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 5. The semiconductor chip mounted on the front surface of the module board faces the mounting board with the surface opposite to the surface on which the bump electrode is provided, and the semiconductor chip mounted on the back surface of the module board faces the mounting board. 2. The semiconductor device according to claim 1, wherein the surface on which the bump electrodes are provided faces the module substrate. 6. Make the arrangement of the bump electrodes of the semiconductor chip symmetrical between the first semiconductor chip and the second semiconductor chip, and turn the second semiconductor chip upside down so that the bump electrodes are connected to each other. 2. The semiconductor device according to claim 1, wherein the semiconductor device is stacked on a chip, and a lead is interposed between the first semiconductor chip and the second semiconductor chip. 7. A semiconductor device comprising two or more tape carrier packages in which a part of each lead pattern is modified so that the tape carrier packages can be mounted in a stacked manner on a mounting substrate. 8. The semiconductor device according to claim 7, wherein a part of the changed lead pattern is a lead for a chip select signal in a tape carrier package. 9. The semiconductor integrated circuit memory device consists of the following configuration: (a) First and second S in the form of substantially square or rectangular plates;
Each of the RAM semiconductor chips has a first main surface and a second main surface, and a main part of the SRAM integrated circuit is formed on each of the first main surfaces; a large number of electrode pads provided near a pair of opposing sides of the surface; (c) a large number of electrode pads provided near either of the pair of sides of the first main surface of each of the chips; a chip select electrode pad; (b) a metal electrode whose inner ends are connected to the plurality of pads of each of the chips;
a large number of leads consisting of sheets; (e) the chip select of each of the chips;
(f) a second main surface of the first chip and the second main surface of the second chip adjacent thereto in a substantially parallel manner; an insulating member provided between the first principal surfaces; (g) such that the outer ends of each of the plurality of leads corresponding to pads having the same function and their neighboring comrades have the same extending direction; 10. The above leads are SOP (Small Outline).
10. The memory device of claim 9, wherein the memory device is shaped like a package. 11. The memory device according to claim 9, wherein the lead is shaped like a pad lead so that the tip of the lead can come into contact with the soldering surface at a substantially right angle. 12. In a method for assembling a semiconductor integrated circuit in which memory chips are connected via bump electrodes to a number of semiconductor chip mounting openings provided along the center of a carrier tape, the above assembly method includes the following steps: (a) Gang-bonding memory chips having the same or substantially the same pattern to the first and second carrier tapes via bump electrodes;・The tape has a large number of leads made of metal sheets on each first main surface and in the chip mounting opening, and the lead patterns of the first and second tapes are connected to the respective chip select terminals or the like. Patterns other than the leads to be connected to equivalent terminals have substantially the same or the same pattern; (b) a memory having the same or substantially the same pattern in each of the openings of the first and second carrier tapes;・Gang-bonding the chips through their respective bump electrodes; (c) Overlapping the first and second tapes so that matching patterns overlap, and forming the leads of each of the openings extending in an overlapping manner. (d) separating the composite from each of the tapes; and (d) separating the composite from each of the tapes. 13. Between the above steps (b) and (c), the above first and second
Claim 12, further comprising the step (e) of botting a resin encapsulant on the device-forming main surface of the memory chip so as to cover each of the main surfaces and each lead and bump electrode on the same main surface. How to assemble. 14. The assembly method according to claim 12, wherein between steps (b) and (c), each chip is electrically tested on each carrier tape. 15. The assembly method according to claim 12, wherein after said step (d), said composite body is solder reflow mounted on a board via its leads by a surface mounting method.