JPH01289271A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01289271A JPH01289271A JP63120039A JP12003988A JPH01289271A JP H01289271 A JPH01289271 A JP H01289271A JP 63120039 A JP63120039 A JP 63120039A JP 12003988 A JP12003988 A JP 12003988A JP H01289271 A JPH01289271 A JP H01289271A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- semiconductor
- insulating film
- gate insulating
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 239000007789 gas Substances 0.000 abstract description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 2
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.
Ａ、産業上の利用分野
Ｂ６発明の概要
Ｃ３従来技術［第３図コ
０１発明か解決しようとする問題点
Ｅ１問題点を解決するための手段
Ｆ１作用
Ｇ、実施例［第１図、第２図コ
Ｈ１発明の効果
（Ａ、産業上の利用分野）
本発明は半導体装置の製造方法、特にシリコン基板の表
面部に加熱酸化によりシリコン酸化膜を形成し、該シリ
コン酸化膜上に半導体層又は半導体を主成分とする層を
形成する半導体装置の製造方法に関する。A. Industrial field of application B6 Summary of the invention C3 Prior art [Fig. 3 C01 Problem to be solved by the invention E1 Means for solving the problem F1 Effect Figure H1 Effects of the Invention (A, Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device, in particular, forming a silicon oxide film on the surface of a silicon substrate by thermal oxidation, and forming a semiconductor layer or a silicon oxide film on the silicon oxide film. The present invention relates to a method for manufacturing a semiconductor device in which a layer containing a semiconductor as a main component is formed.
（Ｂ、発明の概要）
本発明は、上記の半導体装置の製造方法において、
シリコン基板上に形成したシリコン酸化膜の膜質を低下
させないようにするため、
シリコン基板表面部を加熱酸化してシリコン酸化膜を形
成した後、シリコン基板を外気に触れさせないで半導体
層あるいは半導体を主成分とする層を形成する工程に移
行するようにしたものである。(B. Summary of the Invention) In the method for manufacturing a semiconductor device described above, the present invention includes heating and oxidizing the surface of the silicon substrate to prevent deterioration in the quality of the silicon oxide film formed on the silicon substrate. After the film is formed, the silicon substrate is not exposed to the outside air, and the process proceeds to a step of forming a semiconductor layer or a layer mainly composed of a semiconductor.
（Ｃ，従来技術）［第３図］
第３図に示すようなＭＯ３構造のＬＳＩａのゲート絶Ｍ
＠ｂ及びシリコンゲート環ｖＵｃの形成には、一般にＬ
ＯＣＯ５等のプロセスを終えたシリコン半導体基板ｄを
拡散炉内に入れ、シリコン基板ｄの表面部を加熱酸化し
てゲート絶縁膜すを形成し、次いでそのシリコン半導体
基板ｄを一旦拡散炉から出し、水洗い、乾燥をしてゲー
ト絶縁膜す上の汚染物質を除去し、しかる後、ＣＶＤ装
置において減圧ＣＶＤ法等によりゲート電極を成す多結
晶シリコン層を気相成長させるという方法が用いられる
。(C, prior art) [Figure 3] Gate disconnection M of LSIa with MO3 structure as shown in Figure 3
@b and the silicon gate ring vUc are generally formed using L
A silicon semiconductor substrate d that has undergone a process such as OCO5 is placed in a diffusion furnace, the surface portion of the silicon substrate d is heated and oxidized to form a gate insulating film, and then the silicon semiconductor substrate d is temporarily taken out of the diffusion furnace. A method is used in which contaminants on the gate insulating film are removed by washing with water and drying, and then a polycrystalline silicon layer forming the gate electrode is grown in a vapor phase by low pressure CVD or the like in a CVD apparatus.
（Ｄ、発明が解決しようとする問題点）ところで、上述
した従来の半導体装置の製造方法にはシリコン半導体基
板６表面部の加熱酸化により形成したゲート絶縁膜すの
膜質を向上させるには限界があるといえる。なぜならば
、水Ｈ２０を含む洗浄処理液や雰囲気にシリコン酸化膜
５ｉ０２を曝すと水Ｈ２０分子がシリコン酸化膜５ｉ０
２のＳｉと０との結合を破壊し、シリコン酸化膜Ｓ ｉ
０２膜すに微細な割れを生せしめる現象を起こし、そ
の結果、耐圧の低下、耐圧のバラツキが生じるからであ
る。尚、５ｉｎ２に水が付着したとき何故５ｉｎ２の膜
質が悪くなるかについては、月刊誌「サイエンスＪ１９
８８年１月号第３０頁〜３８頁「ガラスはなぜ壊れやす
いのか」においても詳細に説明されている。(D. Problems to be Solved by the Invention) However, the conventional semiconductor device manufacturing method described above has a limit in improving the film quality of the gate insulating film formed by thermal oxidation of the surface portion of the silicon semiconductor substrate 6. It can be said that there is. This is because when the silicon oxide film 5i02 is exposed to a cleaning treatment solution or atmosphere containing water H20, water H20 molecules are released into the silicon oxide film 5i0.
The bond between Si and 0 of 2 is broken, and the silicon oxide film S i
This is because a phenomenon occurs in which fine cracks are generated in the 02 film, resulting in a decrease in breakdown voltage and variations in breakdown voltage. In addition, as for why the film quality of 5in2 deteriorates when water adheres to it, please refer to the monthly magazine "Science J19".
It is also explained in detail in the January 1988 issue, pages 30 to 38, ``Why is glass so fragile?''
しかるに、ＭＯ５構造のＬＳＩにおいてはゲート絶縁膜
の膜質の向上を図ることが要求されている。というのは
、ＭＯ５ＬＳＩは高集積化が進むに従って、ゲート絶縁
膜を薄くする必要性が生じ、その膜厚を１００人あるい
はそれ以下にする要請が為されるに至っている。そして
、ゲート絶縁膜の膜厚を１００Å以下にした場合には、
従来の数千あるいは数百人の膜厚で済んだ場合に比較し
てゲート絶縁膜に要求される膜質が高くなる。However, in the MO5 structure LSI, it is required to improve the film quality of the gate insulating film. This is because, as MO5LSIs become more highly integrated, it becomes necessary to make the gate insulating film thinner, and there are demands to reduce the film thickness to 100 or less. When the thickness of the gate insulating film is set to 100 Å or less,
The film quality required for the gate insulating film is higher than the conventional case where the film thickness is several thousand or hundreds.
なぜならば、膜厚が薄くなっても電源電圧は低くならな
いから、単位厚さ当りの耐圧を高くする必要性があるか
らである。ちなみに、ＶＬＳＩのＭＯＳトランジスタの
設計ルールとゲート絶縁膜の膜厚の関係について示すと
、１．２μｍルールではゲート絶縁膜の膜厚が２５０人
、１．０μｍルール
は膜厚が１５０人、０．５μｍルールでは膜厚が１００
〜１２０人であり、０．５μｍルールの場合のゲート絶
縁膜の膜厚は１、２μｍルールの場合のそれの２分の１
以下になっているのである。This is because the power supply voltage does not decrease even if the film thickness becomes thinner, so it is necessary to increase the withstand voltage per unit thickness. By the way, to show the relationship between the design rules of VLSI MOS transistors and the film thickness of the gate insulating film, the 1.2 μm rule has a gate insulating film thickness of 250, and the 1.0 μm rule has a film thickness of 150 and 0. According to the 5μm rule, the film thickness is 100
~120 people, and the thickness of the gate insulating film in the case of the 0.5 μm rule is half that of that in the case of the 1 or 2 μm rule.
It is as follows.
それに対して、電源電圧の方といえば５Ｖから３、３Ｖ
に低下しているに過ぎず、ゲート絶縁膜の単位Ｍ５当り
の要求される耐圧は上昇している。従って、ゲート絶縁
膜の膜質を向上させる必要性があるのである。On the other hand, the power supply voltage ranges from 5V to 3.3V.
The breakdown voltage required per unit M5 of the gate insulating film is increasing. Therefore, there is a need to improve the quality of the gate insulating film.
本発明はこのような問題点を解決すべく為されたもので
あり、シリコン基板の加熱酸化によって形成され半導体
層あるいは半導体を主成分とする層の下地となるシリコ
ン酸化膜の膜質の向上を図り、耐圧を高くすることを目
的とする。The present invention has been made to solve these problems, and aims to improve the film quality of a silicon oxide film that is formed by thermal oxidation of a silicon substrate and serves as a base for a semiconductor layer or a layer containing semiconductor as a main component. The purpose is to increase the withstand voltage.
（Ｅ．問題点を解決するための手段）
本発明半導体装置の製造方法は上記問題点を解決するた
め、シリコン基板表面部を加熱酸化してシリコン酸化膜
を形成した後シリコン基板を外気に触れさせないで半導
体層あるいは半導体を主成分とする層を形成する工程に
移行するようにしたことを特徴とする。(E. Means for Solving Problems) In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention heats and oxidizes the surface of a silicon substrate to form a silicon oxide film, and then exposes the silicon substrate to outside air. The present invention is characterized in that the process proceeds to the step of forming a semiconductor layer or a layer containing a semiconductor as a main component without causing the formation of the semiconductor layer.
（Ｆ、作用）
本発明半導体装置の製造方法によれば、シリコン酸化膜
形成後その表面に水分を付着させないで半導体層あるい
は半導体を生成分とする層を形成することができる。従
って、従来におけるようなシリコン酸化膜表面に付着し
た水分による膜質の劣化がなく、シリコン酸化膜の膜厚
を高く維持することが可能になり、延いてはシリコン酸
化膜の耐圧の向上を図ることができる。(F. Effect) According to the method for manufacturing a semiconductor device of the present invention, a semiconductor layer or a layer containing a semiconductor can be formed without allowing moisture to adhere to the surface of the silicon oxide film after it is formed. Therefore, there is no deterioration of the film quality due to moisture adhering to the silicon oxide film surface as in the past, and it is possible to maintain a high film thickness of the silicon oxide film, which in turn improves the withstand voltage of the silicon oxide film. I can do it.
（Ｇ、実施例）［第１図、第２図］
以下、本発明半導体装置の製造方法を図示実施例に従っ
て詳細に説明する。(G, Embodiment) [FIGS. 1 and 2] Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described in detail according to the illustrated embodiment.
第１図（Ａ）、（Ｂ）及び第２図（Ａ）乃至（Ｃ）は本
発明半導体装置の製造方法の一つの実施例を工程順に示
すもので、第１図（Ａ）、（Ｂ）は加熱酸化及び半導体
層を形成するＣＶＤ装置の断面図、第２図（Ａ）乃至（
Ｃ）は半導体装置の断面図である。1(A), (B) and FIGS. 2(A) to (C) show one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps. ) is a cross-sectional view of a CVD apparatus for thermal oxidation and forming a semiconductor layer, and FIGS. 2(A) to (
C) is a cross-sectional view of the semiconductor device.
先ず、第２図（Ａ）に示すように選択酸化法によりフィ
ールド絶縁膜１が形成され、素子形成領域表面２が露出
せしめられたシリコン半導体基板３．３、・・・を第１
図（Ａ）に示すようにＣＶＯ装置４の炉５内部に入れる
。そして、炉５をヒータ６で加熱して内部を所定温度（
例えば１０００℃）に高めると共に炉５を真空装置によ
り減圧しながら窒素ガスＮ２と酸素ガス０２を炉５内部
に供給してドライ酸化法による加熱酸化をする。すると
、第２図（Ｂ）に示すようにシリコン半導体基板３の素
子形成領域２表面に５ｉｎ２からなる、ゲート絶縁膜７
が形成される。First, as shown in FIG. 2(A), silicon semiconductor substrates 3.3, .
As shown in Figure (A), it is placed inside the furnace 5 of the CVO device 4. Then, the furnace 5 is heated with the heater 6 to bring the inside to a predetermined temperature (
For example, the temperature is increased to 1000° C.) and nitrogen gas N2 and oxygen gas 02 are supplied into the furnace 5 while reducing the pressure in the furnace 5 using a vacuum device to carry out heating oxidation by a dry oxidation method. Then, as shown in FIG. 2(B), a gate insulating film 7 of 5 in 2 is formed on the surface of the element formation region 2 of the silicon semiconductor substrate 3.
is formed.
次に、シリコン半導体基板、３．３、・・・をＣＶＤ装
置４の炉５から取り出すことなく、単に供給ガスを第１
図（Ｂ）に示すようにモノシランＳｉＨ４ガスに切換え
、必要に応じて加熱温度を変化して減圧ＣＶＤにより第
２図（Ｃ）に示すようにゲート絶縁膜２の表面に多結晶
シリコン層８を形成する。尚、ガスの切換は、具体的に
は加熱酸化終了後Ｎ２等の不活性ガスを炉５内に供給し
て炉５内部の酸素０□ガスを充分にパージした後ＣＶＤ
用のモノシランＳｉＨ４ガスを供給するというように行
う。Next, without taking out the silicon semiconductor substrates 3.3, . . . from the furnace 5 of the CVD apparatus 4, simply supply gas to the first
As shown in FIG. 2(B), the polycrystalline silicon layer 8 is formed on the surface of the gate insulating film 2 by low pressure CVD by switching to monosilane SiH4 gas and changing the heating temperature as necessary. Form. In addition, gas switching is specifically performed after heating and oxidation is completed, by supplying an inert gas such as N2 into the furnace 5 to sufficiently purge the oxygen 0□ gas inside the furnace 5, and then starting the CVD.
This is done by supplying monosilane SiH4 gas.
このような半導体装置の製造方法によれば、加熱酸化後
シリコン半導体基板３．３、−・を炉５から出さないで
そのままＣＶＤ装置４によって多結晶シリコン層８の形
成を行うのでゲート絶縁膜７の表面か外気に曝されるこ
とがない。従って、ゲート絶縁膜７の表面に水分が付着
せず、ゲート絶縁膜７は水分により膜質が劣化する虞れ
がない。According to this method of manufacturing a semiconductor device, the polycrystalline silicon layer 8 is directly formed in the CVD device 4 without taking the silicon semiconductor substrate 3.3, - out of the furnace 5 after heating and oxidation, so that the gate insulating film 7 surface is not exposed to outside air. Therefore, moisture does not adhere to the surface of the gate insulating film 7, and there is no risk that the film quality of the gate insulating film 7 will deteriorate due to moisture.
水分等が付着しない５ｉｎ２は非常に強いことは上記サ
イエンスの記事「ガラスはなぜ壊れやすいのか」からも
明らかである。依って、ゲート絶縁膜７の耐圧を従来よ
りも高くすることができる。It is clear from the above-mentioned Science article, ``Why is glass so fragile?'' that 5in2 is extremely strong as it does not allow moisture to adhere to it. Therefore, the breakdown voltage of the gate insulating film 7 can be made higher than that of the conventional method.
尚、ゲート絶縁膜の形成と、多結晶シリコンのＣＶＤに
よる形成とを別の装置により行うようにすることもでき
る。例えば、加熱酸化用の装置とＣＶＤ装置とを適宜な
手段で連通し、その間をシリコン半導体基板３．３、・
・・が移動できるようにしたものを用いることとし、そ
して、先ず加熱酸化用の装置内にシリコン半導体基板３
．３、・・・を入れ、加熱酸化用装置とＣＶＤ装置との
間を連通ずる部分を遮断して加熱酸化をし、加熱酸化が
終るとその遮断状態を解除し、シリコン半導体基板３．
３、・・・をＣＶＤ装置内部に移し、再び、上記の連通
ずる部分を遮断してＣＶＤ装置によりＣＶＤをすること
により実現することができる。Note that the formation of the gate insulating film and the formation of polycrystalline silicon by CVD may be performed using separate apparatuses. For example, a thermal oxidation device and a CVD device are connected by appropriate means, and the silicon semiconductor substrates 3.3, .
. . , which can be moved, and first place the silicon semiconductor substrate 3 in a device for thermal oxidation.
．． 3, .
This can be realized by moving 3, .
この場合、加熱酸化後ＣＶＤを開始するまでの間シリコ
ン半導体基板３．３、・・・の雰囲気を不活性雰囲気あ
るいは酸化性雰囲気（０２）にしてゲート絶縁膜２の表
面に水分が付着しないようにさえすれば、やはり第１図
及び第２図で示した方法の場合と全く同じようにゲート
絶縁膜の耐圧を高くすることができ、そして、耐圧値の
バラツキをなくすことができる。In this case, the atmosphere of the silicon semiconductor substrates 3.3, . By doing so, the withstand voltage of the gate insulating film can be increased just as in the case of the method shown in FIGS. 1 and 2, and variations in the withstand voltage values can be eliminated.
尚、本発明半導体装置の製造方法は、シリコン酸化膜が
ゲート絶縁膜を成す場合だけでなく、例えばトレンチキ
ャパシタの誘電体膜を成す場合にも適用することができ
る。また、シリコン酸化膜の表面に形成する層がシリコ
ン半導体層である場合に限らず例えばポリサイドの如く
半導体を主成分とする層である場合にも適用することが
できる。Note that the method of manufacturing a semiconductor device of the present invention can be applied not only to the case where the silicon oxide film forms the gate insulating film but also to the case where the silicon oxide film forms the dielectric film of a trench capacitor, for example. Further, the present invention can be applied not only when the layer formed on the surface of the silicon oxide film is a silicon semiconductor layer but also when it is a layer mainly composed of a semiconductor such as polycide.
（Ｈ，発明の効果）
以上に述べたように、本発明半導体装置の製造方法は、
シリコン基板の表面部に加熱酸化によりシリコン酸化膜
を形成し、該シリコン酸化膜上に半導体層又は半導体を
主成分とする層を形成する半導体装置の製造方法におい
て、一つの加熱装置内部に上記シリコン基板を入れて上
記シリコン酸化膜を加熱酸化により形成した後、該シリ
コン基板を外気に触れさせないで該加熱装置内部におけ
る又は該加熱装置と別の装置における上記の半導体層又
は半導体を主成分とする層を形成する工程に移ることを
特徴とするものである。(H, Effects of the Invention) As described above, the method for manufacturing a semiconductor device of the present invention is as follows:
In a method for manufacturing a semiconductor device in which a silicon oxide film is formed on the surface of a silicon substrate by thermal oxidation, and a semiconductor layer or a layer mainly composed of a semiconductor is formed on the silicon oxide film, the silicon After placing the substrate and forming the silicon oxide film by thermal oxidation, the silicon substrate is not exposed to the outside air and the semiconductor layer or the semiconductor is the main component is formed inside the heating device or in a device separate from the heating device. This is characterized by moving on to the step of forming layers.
・従って、本発明半導体装置の製造方法によりば、シリ
コン酸化膜形成後その表面に水分を付着させないで半導
体層あるいは半導体を主成分とする層を形成することが
できる。従って、従来におけるようなシリコン酸化膜表
面に付着した水分による膜質の劣化がなく、シリコン酸
化膜の膜厚を高く維持することが可能になり、延いては
シリコン酸化膜の耐圧の向上を図り、耐圧のバラツキを
小さくすることができる。- Therefore, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor layer or a layer mainly composed of a semiconductor can be formed without allowing moisture to adhere to the surface of the silicon oxide film after it is formed. Therefore, there is no deterioration of the film quality due to moisture adhering to the surface of the silicon oxide film as in the past, and it is possible to maintain a high film thickness of the silicon oxide film, which in turn improves the withstand voltage of the silicon oxide film. Variations in breakdown voltage can be reduced.
第１図（Ａ）、（Ｂ）及び第２図（Ａ）乃至（Ｃ）は本
発明半導体装置の製造方法の一つの実施例を工程順に示
すもので、第１図（Ａ）、（Ｂ）はＣＶＤ装置の断面図
、第２図（Ａ）乃至（Ｃ）は半導体装置の断面図、第３
図は半導体装置の断面図である。
符号の説明
３・・・シリコン基板、４・・・ＣＶＤ装置、７・・・
シリコン酸化膜、
８・・・半導体層。
半導体８置の断面図
第３図1(A), (B) and FIGS. 2(A) to (C) show one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps. ) is a cross-sectional view of the CVD device, Figures 2 (A) to (C) are cross-sectional views of the semiconductor device, and Figure 3 is a cross-sectional view of the semiconductor device.
The figure is a cross-sectional view of a semiconductor device. Explanation of symbols 3...Silicon substrate, 4...CVD device, 7...
silicon oxide film, 8... semiconductor layer; Figure 3: Cross-sectional view of semiconductor 8-position
Claims (1)
酸化膜を形成し、該シリコン酸化膜上に半導体層又は半
導体を主成分とする層を形成する半導体装置の製造方法
において、 一つの加熱装置内部に上記シリコン基板を入れて上記シ
リコン酸化膜を加熱酸化により形成した後、該シリコン
基板を外気に触れさせないで該加熱装置内部における又
は該加熱装置と別の装置における上記の半導体層又は半
導体を主成分とする層を形成する工程に移る ことを特徴とする半導体装置の製造方法(1) In a method for manufacturing a semiconductor device in which a silicon oxide film is formed on the surface of a silicon substrate by thermal oxidation, and a semiconductor layer or a layer mainly composed of a semiconductor is formed on the silicon oxide film, the inside of one heating device After placing the silicon substrate in the heating device and forming the silicon oxide film by thermal oxidation, the semiconductor layer or semiconductor is mainly heated inside the heating device or in a device separate from the heating device without exposing the silicon substrate to outside air. A method for manufacturing a semiconductor device, characterized by moving to a step of forming a layer as a component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120039A JP2687427B2 (en) | 1988-05-17 | 1988-05-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120039A JP2687427B2 (en) | 1988-05-17 | 1988-05-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01289271A true JPH01289271A (en) | 1989-11-21 |
| JP2687427B2 JP2687427B2 (en) | 1997-12-08 |
Family
ID=14776390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63120039A Expired - Fee Related JP2687427B2 (en) | 1988-05-17 | 1988-05-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687427B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015514314A (en) * | 2012-03-23 | 2015-05-18 | サンパワー コーポレイション | Solar cell having an emitter region containing a wide bandgap semiconductor material |
| US11462654B2 (en) * | 2015-06-30 | 2022-10-04 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
-
1988
- 1988-05-17 JP JP63120039A patent/JP2687427B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015514314A (en) * | 2012-03-23 | 2015-05-18 | サンパワー コーポレイション | Solar cell having an emitter region containing a wide bandgap semiconductor material |
| US10170657B2 (en) | 2012-03-23 | 2019-01-01 | Sunpower Corporation | Solar cell having an emitter region with wide bandgap semiconductor material |
| US10490685B2 (en) | 2012-03-23 | 2019-11-26 | Sunpower Corporation | Solar cell having an emitter region with wide bandgap semiconductor material |
| US10957809B2 (en) | 2012-03-23 | 2021-03-23 | Sunpower Corporation | Solar cell having an emitter region with wide bandgap semiconductor material |
| US11605750B2 (en) | 2012-03-23 | 2023-03-14 | Sunpower Corporation | Solar cell having an emitter region with wide bandgap semiconductor material |
| US12009449B2 (en) | 2012-03-23 | 2024-06-11 | Maxeon Solar Pte. Ltd. | Solar cell having an emitter region with wide bandgap semiconductor material |
| US11462654B2 (en) * | 2015-06-30 | 2022-10-04 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2687427B2 (en) | 1997-12-08 |
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