JPH01288783A - Test circuit - Google Patents

Abstract

PURPOSE:To enable the detection of a fault without increasing the number of terminals, by a method wherein an arbitrary number of output terminals connected to a gate to be tested of a semiconductor integrated circuit are switched over according to an external instruction to be connected selectively to an output terminal. CONSTITUTION:A clock input terminal 3 of a counter circuit 4 is connected to an arbitrary internal clock signal terminal, and based on the clock signal thereof, the circuit 4 is made to operate. Based on selector control signals 51-5n from this circuit 4, a selector circuit 2 switches over input terminals 11-1m thereof. Then, an output signal of an internal gate of a semiconductor integrated circuit connected to the switched input terminal is outputted sequentially to an external output terminal 6. A fault of the internal gate is detected from a signal of this terminal 6.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a test circuit for semiconductor integrated circuits.

[Conventional technology]

Conventionally, in order to improve the failure detection rate in semiconductor integrated circuits, the test pattern has been improved using a test pattern, and if a change in the signal at an internal gate does not appear as a change in the signal at the external output terminal, the output of the internal gate is The failure detection rate was improved by connecting to an external output terminal for failure detection.

[Problem to be solved by the invention]

The fault detection circuit in the conventional semiconductor integrated circuit described above requires a large number of external output terminals for fault detection when there are multiple internal gates in which a signal change at an internal gate does not appear as a signal change at an external output terminal. This increases the number of terminals in the entire circuit, and due to the limited number of terminals, there is a possibility that some internal gates may become undetectable.

An object of the present invention is to provide a test circuit that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the test circuit according to the present invention switches an arbitrary number of input terminals connected to the gate under test of a semiconductor integrated circuit based on an external command and selectively connects them to output terminals. and a counter that outputs an electrical selector control signal as an external command to the selector circuit in response to input of a clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, 2 is a selector circuit, and 4 is a counter circuit.

Input terminal 1 of selector circuit 2. ~1. is connected to the internal gate under test of the semiconductor integrated circuit in which a change in the internal gate output signal does not appear as a change in the external output terminal signal, and the output terminal 6 of the selector circuit 2 is connected to an external output terminal for failure detection. Furthermore, the selector circuit 2 has a function of switching the input terminals 11 to 1 based on an external command and selectively connecting them to the output terminal 6. The clock input terminal 3 of the counter circuit 4 is connected to an arbitrary internal clock signal terminal, and based on the clock signal, the input terminals 1, .
1. Selector control signal as an external command to switch5.
~5. is output to the selector circuit 2.

In the embodiment, when the counter circuit 4 operates according to the internal clock signal, the selector control signals 5, to 5 . Based on this, the selector circuit 2 selects its input terminals 1, -1 . is switched, and the output signals of the internal gates of the semiconductor integrated circuits connected to the switched input terminals are sequentially outputted to the external output terminal 6. The signal from this output terminal 6 is used to detect a failure in the internal gate.

〔Effect of the invention〕

As explained above, when the present invention is applied to a semiconductor integrated circuit, it is possible to improve the failure detection rate by simply increasing the number of output terminals by one terminal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 11-11...Input terminal of selector circuit 2...Selector circuit 3...Tarlock input terminal 4...Counter circuit 5, -5. ...Selector control signal 6...Selector output terminal Patent applicant: NEC Corporation NEC Corporation Engineering Co., Ltd.

Claims (1)

[Claims] (1) A selector circuit that switches an arbitrary number of input terminals connected to the gate under test of a semiconductor integrated circuit based on an external command and selectively connects them to output terminals, and an electrical A test circuit comprising: a counter that outputs a selector control signal as an external command to the selector circuit.