JPS63150936A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63150936A
JPS63150936A JP29922486A JP29922486A JPS63150936A JP S63150936 A JPS63150936 A JP S63150936A JP 29922486 A JP29922486 A JP 29922486A JP 29922486 A JP29922486 A JP 29922486A JP S63150936 A JPS63150936 A JP S63150936A
Authority
JP
Japan
Prior art keywords
input
output
semiconductor device
cells
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29922486A
Other languages
Japanese (ja)
Inventor
Masaki Ebina
蝦名　正樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29922486A priority Critical patent/JPS63150936A/en
Publication of JPS63150936A publication Critical patent/JPS63150936A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To test a semiconductor device extremely easily and in a short time by forming input/output test exclusive circuits to all the input/output cells corresponding to package terminals or predetermined input/output cells besides a product circuit originally produced in the master slice system semiconductor device. CONSTITUTION:A buffer is taken as an example as input/output cells. A signal input from an input buffer 1 at the time of an actual use state as a product passes through a desired product circuit 2. The signal is output at desired expected values from output buffers 4 through two-input one-output selectors 3. A select signal is transmitted over the two-input one-output selectors 3 from an input buffer 5 for changing over input/output cell tests so that the signal from the desired product circuit 2 is sent to the output buffers 4 at that time. When the input/output cells are tested, the two-input one-output selectors 3 select a bypass circuit 101 passing no desired product circuit 2 by the select signal from the input buffer 5 for changing over the input/output tests. Signals entering the input buffers 1 are transmitted directly over the output buffers 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し特にマスタスライス方式で形
成された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device formed by a master slicing method.

〔従来の技術〕[Conventional technology]

従来マスタスライス方式で形成されたＣＭＯ８半導体素
子を有する半導体装置はその入出力セル部専用の試験用
回路は持っていなかった。Conventionally, a semiconductor device having a CMO8 semiconductor element formed by the master slice method did not have a test circuit dedicated to its input/output cell section.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置は半導体装置につくりこめら
れた製品回路とは独立して入出力セル部を動作させるこ
とができないため、各端子ごとに、ある特定パターンま
で半導体装置全体を動作さ、せねばならず、その入出力
セルの機能確認に時間がかかるとともに、その試験用プ
ログラムは複雑であった。これは、開発及び量産の時間
がかかることになり、コスト高となってしまう。In the conventional semiconductor device described above, it is not possible to operate the input/output cell section independently of the product circuit built into the semiconductor device. Therefore, it took time to confirm the function of the input/output cells, and the test program was complicated. This requires time for development and mass production, resulting in high costs.

本発明の目的は上記欠点を除去し低コストの半導体装置
を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a low-cost semiconductor device.

上述した従来の半導体装置に対し、本発明は、製品回路
とは独立して入出力セルを自由に動作させる試験専用回
路をパッケージ端子に対応する全人出セルに設けるとい
う独創性を有する。In contrast to the conventional semiconductor device described above, the present invention has the originality of providing a test-dedicated circuit for freely operating input/output cells independently of the product circuit in a full-scale cell corresponding to a package terminal.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、マスタスライス方式で形成され
た半導体装置であって半導体装置に本来つくりこまれる
製品回路の他に、入力セルの１入力セルあるいは複数入
力セルからの出力信号が出力セルの１出力セルまたは複
数出力セルに伝達される様な入出力セル試験専用回路を
パッケージ端子に対応する全入出力セルもしくは予じめ
定めた入出力セルにわたって設けられている。The semiconductor device of the present invention is a semiconductor device formed using a master slice method, and in addition to the product circuit originally created in the semiconductor device, an output signal from one input cell or a plurality of input cells is transmitted to an output cell. A dedicated input/output cell test circuit for transmitting data to one output cell or a plurality of output cells is provided over all input/output cells or predetermined input/output cells corresponding to the package terminal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の半導体装置の一実施例を示す回路図で
あり、入出力セルとしてバッファを例にしている。製品
としての実使用状態のとき人力バッファ１より入力され
た信号は所望の製品回路２を通り、２人力１出力セレク
タ３を経て出力バッファ４より所望の期待値で出力され
る。このとき所望の製品回路２からの信号が出力バッフ
ァ４に伝わる用に、入出力セル試験切換用人力バッファ
５から２人力１出力セレクタ３にセレクト信号が送られ
ている。次に入出力セルの試験の時には、２人力１出力
セレクタ３は、入出力試験切換用人力バッファ５からの
セレクト信号により所望の製品回路２を通らないバイパ
ス回路１０１を選択し、入力バッファ１に入った信号は
直接出力バッファ４に伝達される。FIG. 1 is a circuit diagram showing an embodiment of the semiconductor device of the present invention, using a buffer as an example of an input/output cell. When the product is in actual use, a signal input from the manual buffer 1 passes through a desired product circuit 2, passes through the two-manual one output selector 3, and is output from the output buffer 4 at a desired expected value. At this time, in order to transmit the signal from the desired product circuit 2 to the output buffer 4, a select signal is sent from the input/output cell test switching manual buffer 5 to the two-manpower one-output selector 3. Next, when testing input/output cells, the two-manpower one-output selector 3 selects the bypass circuit 101 that does not pass through the desired product circuit 2 in response to the selection signal from the input-output test switching manual buffer 5, and selects the bypass circuit 101 that does not pass through the desired product circuit 2. The input signal is directly transmitted to the output buffer 4.

第２図は本発明の半導体装置の第２の実施例を示す回路
図であり、第１の実施例同様入出力セルとしてバッファ
を例にしている。６は２人力１出カセレクタを内蔵した
出力バッファであり、入出力セル試験切換用人力バッフ
ァ５より入力される信号により所望の製品回路２からの
信号と入力バッファ１からの直接の信号のどちらかを選
択して出力させることができる。FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor device of the present invention, in which a buffer is used as an example of an input/output cell as in the first embodiment. Reference numeral 6 denotes an output buffer with a built-in two-manpower one-output selector, which selects either the signal from the desired product circuit 2 or the direct signal from the input buffer 1, depending on the signal input from the manual input/output cell test switching buffer 5. can be selected and output.

なお、第１および第２図に示されるバイパス回路１０１
．セレクタ３は、半導体装置が収容されるパッケージの
入出力端子に対応する全入出力セル、もしくは予じめ定
めた入出力セルについて設ければよい。Note that the bypass circuit 101 shown in FIGS. 1 and 2
．． The selector 3 may be provided for all input/output cells corresponding to input/output terminals of a package in which a semiconductor device is housed, or for predetermined input/output cells.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は製品回路とは独立して入出
力セルを試験する回路を設けることにより半導体装置の
試験、すなわち出力バッファの高レベル出力電圧、低レ
ベル出力電圧、高レベル出力電流、低レベル出力電流等
の試験、及び入力レベルの試験が非常に簡単に短時間に
行うことができる。また、半導体装置が所望の動作をし
ない時その原因が内部セルにあるのか入出力セルにある
のか、製品回路とは独立して入出力セルを動作させるこ
とができるので不良解析に非常に有効である。As explained above, the present invention can test semiconductor devices by providing a circuit that tests input/output cells independently of the product circuit, that is, the high level output voltage, low level output voltage, high level output current of the output buffer, Tests such as low level output current and input level tests can be performed very easily and in a short time. In addition, when a semiconductor device does not operate as desired, it is very effective for failure analysis because it allows you to determine whether the cause lies in the internal cells or the input/output cells, since the input/output cells can be operated independently of the product circuit. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す回路図、第２図は
本発明の第２の実施例を示す回路図である。 １・・・入力バッファ、２・・・所望の製品回路、３・
・・２人力１出力セレクタ、４・・・出力バッファ、５
・・・入出力セル試験切換用人力バッファ、６・・・２
人力１出力セレクタ内蔵出力バッファ。 代理人　弁理士　内　原　　音／ネみ・々光 〈−二FIG. 1 is a circuit diagram showing a first embodiment of the invention, and FIG. 2 is a circuit diagram showing a second embodiment of the invention. 1... Input buffer, 2... Desired product circuit, 3.
・・2 manual output selector, 4・output buffer, 5
...Manual buffer for input/output cell test switching, 6...2
Output buffer with built-in human power 1 output selector. Agent Patent Attorney Oto Uchihara/Nemi Riko〈-2

Claims (1)

【特許請求の範囲】[Claims] マスタスライス方式で形成され入力セルおよび出力セル
を有する半導体装置において、前記入力セルおよび出力
セルの機能試験時に、該半導体装置に作りこまれる製品
回路と独立して前記入力セルの１入力セルあるいは複数
入力セルからの出力信号が前記出力セルの一出力セルあ
るいは複数出力セルに伝達される入出力セル部の試験専
用回路を前記半導体装置が収容されるパッケージの入出
力端子に対応する全入出力セルもしくは予じめ定めた入
出力セルにわたって設けたことを特徴とする半導体装置
。In a semiconductor device formed by a master slice method and having an input cell and an output cell, during a functional test of the input cell and output cell, one or more of the input cells are tested independently of the product circuit built into the semiconductor device. All input/output cells corresponding to the input/output terminals of the package in which the semiconductor device is housed include test-dedicated circuits in the input/output cell section in which an output signal from the input cell is transmitted to one output cell or multiple output cells of the output cell. Alternatively, a semiconductor device characterized in that it is provided over predetermined input/output cells.
JP29922486A 1986-12-15 1986-12-15 Semiconductor device Pending JPS63150936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29922486A JPS63150936A (en) 1986-12-15 1986-12-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29922486A JPS63150936A (en) 1986-12-15 1986-12-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63150936A true JPS63150936A (en) 1988-06-23

Family

ID=17869755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29922486A Pending JPS63150936A (en) 1986-12-15 1986-12-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63150936A (en)

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