JPH0128386B2 - - Google Patents

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Publication number
JPH0128386B2
JPH0128386B2 JP54101912A JP10191279A JPH0128386B2 JP H0128386 B2 JPH0128386 B2 JP H0128386B2 JP 54101912 A JP54101912 A JP 54101912A JP 10191279 A JP10191279 A JP 10191279A JP H0128386 B2 JPH0128386 B2 JP H0128386B2
Authority
JP
Japan
Prior art keywords
electrode
liquid crystal
tft
film
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54101912A
Other languages
Japanese (ja)
Other versions
JPS5626468A (en
Inventor
Hirosaku Nonomura
Yutaka Takato
Sadatoshi Takechi
Hisashi Kamiide
Tomio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP10191279A priority Critical patent/JPS5626468A/en
Priority to DE3028718A priority patent/DE3028718C2/en
Priority to US06/173,818 priority patent/US4404578A/en
Priority to GB8025044A priority patent/GB2056770B/en
Publication of JPS5626468A publication Critical patent/JPS5626468A/en
Priority to GB08316195A priority patent/GB2127216B/en
Priority to GB08316196A priority patent/GB2126779B/en
Publication of JPH0128386B2 publication Critical patent/JPH0128386B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Description

【発明の詳細な説明】 本発明は薄膜トランジスタ（以下TFTと略す）
を用いた液晶表示装置に関するもので、特に
TFTの電極構造に、技術的手段を駆動すること
により、TFT特性の向上を計つたものである。
TFTを付加した液晶表示装置としては、1972年、
各絵素に各１個づつトランジスタ（Tr）及びコ
ンデンサを蒸着膜（Thin Film）で構成したマト
リツクス型液晶表示パネルがウエステング ハウ
ス（Westing house）社より発表されている。[Detailed Description of the Invention] The present invention relates to a thin film transistor (hereinafter abbreviated as TFT)
It relates to liquid crystal display devices using
This is an attempt to improve TFT characteristics by applying technical means to the TFT electrode structure.
In 1972, the first liquid crystal display device with TFT added was
A matrix type liquid crystal display panel in which each picture element has one transistor (Tr) and one capacitor made of thin film has been announced by Westing House.

この仕様の詳細については、IEEE Trans on
Electrsn Devices ED―20 P995、1973、Ｔ、
Ｐ、Brody etal“A6″×6″ 20l／inch Liquid
Crystal Display Panel”及び1974年のSIDの論
文集P166“Operational Charactaristics of ａ
6″×6″ TFT Matrix Array Liquid Crystal
Display”に述べられているが、以下この動作原
理を簡単に説明する。 For more information about this specification, see IEEE Trans on
Electrsn Devices ED-20 P995, 1973, T,
P, Brody etal “A6″×6″ 20l/inch Liquid
Crystal Display Panel” and 1974 SID Proceedings P166 “Operational Charactaristics of a
6″×6″ TFT Matrix Array Liquid Crystal
The operating principle will be briefly explained below.

第１図は、液晶セルの１絵素４をTFT３及び
コンデンサ（Cs）５を用いて駆動する等価回路
図、第２図はその駆動波形を示す。図では４絵素
の等価回路を示したが、これをＸ―Ｙに配して結
線し、それぞれに応じた信号波形を与えることに
よりマトリツクス表示が可能となる。 FIG. 1 is an equivalent circuit diagram for driving one pixel 4 of a liquid crystal cell using a TFT 3 and a capacitor (Cs) 5, and FIG. 2 shows its driving waveform. Although the figure shows an equivalent circuit of four picture elements, a matrix display is possible by arranging and connecting these in an X-Y direction and giving signal waveforms corresponding to each.

第１図のソース電極１からソース電圧として
V1、ゲート電極２からゲート電圧としてV1を印
加すると、TFT３は導通（ON）状態となり、ソ
ース電極１からTFTのON抵抗（RON）を通し
て液晶の容量（CLC）４と並列に接続されてい
るコンデンサ（Cs）５に充電が行なわれ、ドレ
イン電極６の電位（Ｖドレイン１）は式(1)に従つ
て変化する。 As the source voltage from source electrode 1 in Figure 1
When V 1 is applied as the gate voltage from the gate electrode 2, the TFT 3 becomes conductive (ON), and the TFT 3 is connected in parallel with the liquid crystal capacitor (CLC) 4 from the source electrode 1 through the ON resistance (RON) of the TFT. The capacitor (Cs) 5 is charged, and the potential of the drain electrode 6 (V drain 1) changes according to equation (1).

Ｖドレイン１＝V1（１−e-ｔ／τ1） …(1) 但しτ1＝RON（CLC＋CS） 次にゲート電極２のゲート電圧を−V2にする
とTFT３は遮断（OFF）状態となり、容量CLC及
びCs５に充電されている電荷は、TFT３のOFF
抵抗（ROFF）及び液晶の抵抗（RLC）を通して放
電を開始するが、抵抗ROFF，RLC，RONは ROFF》RON，RLC＞ROFF の関係があるため、その放電は徐々にしか行なわ
れず、ドレイン電極の電位（Ｖドレイン２）は式
(2)に従つて長い時間、高電位で保持される。 V drain 1 = V 1 (1-e - t/τ 1 ) ...(1) However, τ 1 = RON (C LC + C S ) Next, when the gate voltage of gate electrode 2 is set to -V 2 , TFT 3 is cut off (OFF). ) state, and the charges charged in the capacitors CLC and Cs5 are turned off when TFT3 is turned off.
Discharge starts through the resistor (R OFF ) and the liquid crystal resistor (R LC ), but since the resistors R OFF , R LC , and R ON have the relationship of R OFF 》R ON , R LC > R OFF , the discharge is It is carried out only gradually, and the potential of the drain electrode (V drain 2) is determined by the formula
According to (2), it is held at a high potential for a long time.

Ｖドレイン２＝V1e−-ｔ／τ2 …(2) 但しτ2＝（ROFFRLC）（CLC＋CS） この様子を各電極の電圧波形によつて第２図に
示すが、ソース電極１に加わる電圧のデユーテイ
が小さく実効電圧が極めて小さいにもかゝわら
ず、ドレイン電極に生じる実効電圧、即ち、液晶
エレメントに印加される実効電圧は非常に大きく
なりデユーテイフアクタが小さくても高コントラ
ストの表示が行なわれることとなる。 V drain 2 = V 1 e- - t/τ 2 ...(2) However, τ 2 = (R OFF R LC ) (C LC + C S ) This situation is shown in Figure 2 by the voltage waveform of each electrode. Although the duty of the voltage applied to the source electrode 1 is small and the effective voltage is extremely small, the effective voltage generated at the drain electrode, that is, the effective voltage applied to the liquid crystal element is extremely large, and the duty factor is Even if the size is small, a high-contrast display will be performed.

以上のような原理で動作する為のセル構成を第
３図に示す。これはガラス基板７上にTFT３及
び容量５、それに液晶エレメントの片方電極１１
を蒸着法によつて形成し、それをＸ―Ｙに配列し
且つＸバー、Ｙバーに結線を行なつて構成した薄
薄トランジスタアレイ基板２２と、ガラス基板
７′上に各絵素に共通の全面透明導電膜１７を備
えた基板２３とからなる。これら両方の電極基板
上にはsio又はsio2等の透明絶縁膜１４，１５を
蒸着した後斜蒸着又はラビング等によつてTN配
向処理を行なう。この２枚の基板をシール材２１
で封止し、これに液晶１６、例えばTN―FEM
液晶又はゲストホスト型液晶を注入させることに
よりTFTを用いたマトリツクス型液晶表示セル
が完成する。これに偏光板１８及び１９、反射板
２０を組み合わせることによつて第３図に示した
マトリツクス型液晶表示装置が構成される。 FIG. 3 shows a cell configuration for operating on the principle described above. This consists of a TFT 3 and a capacitor 5 on a glass substrate 7, and one electrode 11 of a liquid crystal element.
A thin transistor array substrate 22 is formed by evaporation, arranged in an X-Y pattern, and connected to X bars and Y bars, and a thin transistor array substrate 22 is formed by arranging them in an X-Y direction and connecting them to X bars and Y bars. and a substrate 23 provided with a transparent conductive film 17 over the entire surface. Transparent insulating films 14, 15 such as sio or sio 2 are deposited on both electrode substrates, and then TN alignment treatment is performed by oblique evaporation or rubbing. Seal material 21
and seal it with a liquid crystal 16, such as TN-FEM.
A matrix-type liquid crystal display cell using TFT is completed by injecting liquid crystal or guest-host type liquid crystal. By combining this with polarizing plates 18 and 19 and a reflecting plate 20, the matrix type liquid crystal display device shown in FIG. 3 is constructed.

なお、図中８はＡ１等よりなるゲート電極、９
は容量Csの一方の電極、１０はTFTを構成する
ためのゲート絶縁膜及び容量Csの誘電体膜、１
１は液晶エレメントの一方の電極パツド、１２は
ソース電極、１３はドレイン電極、２４は半導体
膜を示す。 In addition, 8 in the figure is a gate electrode made of A1 etc., 9
is one electrode of the capacitor Cs, 10 is a gate insulating film for configuring the TFT and a dielectric film of the capacitor Cs, 1
1 is one electrode pad of the liquid crystal element, 12 is a source electrode, 13 is a drain electrode, and 24 is a semiconductor film.

このような液晶表示装置を駆動する波形を第２
図に、またその改良した駆動波形（特願昭53−
15583号）を第４図に示すが、いずれも(1)及び(2)
式によつて、充放電を行なつて駆動を行なう駆動
方式である。この式でτ（τ1，τ2）を大きくする
ことが駆動周波数（フレーム周波数）を下げ、ひ
いては表示装置の周辺駆動回路の消費電力の低減
につながるが、その為にはコンデンサ（Cs）を
できるだけ大きくするか、ROFF／RON比はそのま
までRONを大きくすることが望ましい。 The waveform that drives such a liquid crystal display device is
The figure also shows the improved drive waveform (patent application 1983-
15583) is shown in Figure 4, both (1) and (2)
This is a drive method that performs driving by charging and discharging according to the formula. Increasing τ (τ 1 , τ 2 ) in this equation lowers the drive frequency (frame frequency), which in turn leads to a reduction in the power consumption of the peripheral drive circuit of the display device, but in order to do so, it is necessary to increase the capacitor (Cs). It is desirable to make it as large as possible, or to increase R ON while keeping the R OFF /R ON ratio unchanged.

Csを大きくする一方法として、Csの誘電体層
の膜厚を薄くすることが考えられるが薄くすれば
する程誘電体膜の耐圧を下げ、またピンホールも
でき易くなるといつた問題が生じる。 One way to increase Cs is to reduce the thickness of the Cs dielectric layer, but the thinner the Cs layer, the lower the withstand voltage of the dielectric film, and the more likely pinholes will form.

次に考えられるのがTFTの相互コンダクタン
スが小さくなつてもRONの値を大きくすること、
即ち、ドレイン電流（ID）を小さくすることであ
る。TFTのIDを決定する式は ID＝ε1ε0μW／LTox 〔（Vg−Vo）VD−１／２V2 D〕 …(3) 但し Vg：ゲート電圧 Tox：ゲート酸化膜の厚さ ε0：誘電率 ε1：ゲート酸化膜の比誘電率 μ：半導体のモビリテイ Ｗ：チヤネルの幅 Ｌ：チヤネルの長さ VD：ドレイン電圧 VO：ピンチオフ電圧 であるがTFTの形状を変えることによりIDを小
さくする方法としてはチヤネル幅（Ｗ）を細く、
チヤネルギヤツプ(L)を長くすることが考えられ
る。本発明はIDを小さくする為に、チヤネル幅及
びギヤツプの形状に技術的手段を駆使した新規有
用な薄膜トランジスタの構造を提供することを目
的とするものである。 The next possibility is to increase the value of R ON even if the TFT mutual conductance decreases.
That is, the purpose is to reduce the drain current (I D ). The formula for determining the TFT ID is I D = ε 1 ε 0 μW/LTox [(Vg−Vo)V D −1/2V 2 D ] …(3) where Vg: gate voltage Tox: gate oxide film thickness ε 0 : Dielectric constant ε 1 : Relative permittivity of gate oxide film μ : Mobility of semiconductor W : Width of channel L : Length of channel V D : Drain voltage V O : Pinch-off voltage but changes the shape of TFT One way to reduce I D is to make the channel width (W) thinner.
One possibility is to lengthen the channel gap (L). It is an object of the present invention to provide a new and useful thin film transistor structure in which technical means are utilized for channel width and gap shape in order to reduce ID .

以下、本発明を実施例に従つて図面と共に詳説
する。 Hereinafter, the present invention will be explained in detail according to examples and with drawings.

第５図ａに示す従来のチヤネル部分（チヤネル
幅をＷ、ギヤツプをl1で表わす）に対して、第５
図ｂ，ｃに示す如く、チヤネル部分の外形及び面
積をあまり変化させることなく、チヤネル幅を1/
６に設定し、従来のチヤネル部分に切り込みを加
えてチヤネル通路を迂回路となる形状とする。即
ち、第５図ｂはソース電極―ドレイン電極方向と
直交する方向にチヤネル部分を両側より切り込
み、切り込み方向に迂回路を形成したものであ
り、第５図ｃはソース電極側とドレイン電極側の
両方向より螺旋状の迂回路を形成し中心部で連結
したものである。 For the conventional channel part shown in Fig. 5a (the channel width is represented by W and the gap is represented by l1 ), the fifth
As shown in Figures b and c, the channel width can be reduced by 1/2 without changing the outer shape or area of the channel part.
6, and a notch is added to the conventional channel portion to shape the channel passage into a detour. That is, in FIG. 5b, the channel portion is cut from both sides in a direction perpendicular to the source electrode-drain electrode direction, and a detour is formed in the direction of the cut, and in FIG. 5c, a detour is formed in the direction of the source electrode and the drain electrode. A spiral detour is formed from both directions and connected at the center.

第５図ｂ，ｃに示すように半導体膜を加工する
ことによりチヤネル部を占める面積は同じでも
TFTのID特性を決定するチヤネルの幅は数分の
１に、チヤネルのギヤツプ（チヤネルの長さl2）
は数倍になり、IDを１桁以上小さくすることがで
き、それだけコンデンサの値を変えることなくτ
の値を大きくすることが可能となる。またτの値
をそのままで、コンデンサーの値を小さくするこ
ともでき、この場合は、充放電に伴なう電荷の移
動が少なくなりその分だけ表示装置内部での電力
消費が少なくなるという利点も得られる。 As shown in Figure 5b and c, by processing the semiconductor film, even though the area occupied by the channel portion is the same,
The channel width, which determines the ID characteristics of TFT, is reduced to a fraction of the channel gap (channel length l 2 ).
becomes several times larger, making it possible to reduce I D by more than an order of magnitude, and without changing the value of the capacitor, τ
It becomes possible to increase the value of . It is also possible to reduce the value of the capacitor while keeping the value of τ unchanged. In this case, there is an advantage that the movement of charge due to charging and discharging is reduced, and the power consumption inside the display device is reduced accordingly. can get.

IDを小さくする方法として第５図ｄに示すよう
にチヤネルの長さを直線的に引き伸すことも可能
であるが、Ｘ―Ｙマトリツクスの場合、絵素の大
きさにより制限が課せられる。しかしながら、本
発明の第５図ｂ及びｃの形状にした場合そういつ
た制限が無く、ソース電極―ドレイン電極間隔を
拡げることなくチヤネルの長さを長くすることが
できる。 As a way to reduce I D , it is possible to linearly extend the length of the channel as shown in Figure 5d, but in the case of an XY matrix, restrictions are imposed by the size of the picture element. . However, in the case of the shapes shown in FIGS. 5b and 5c of the present invention, there is no such limitation, and the length of the channel can be increased without increasing the distance between the source electrode and the drain electrode.

本発明のチヤネル構造を代表的なTFT構造に
適用した場合を第６図ａ，ｂに示す。第６図ｂは
第６図ａのＡ―A′断面図である。第７図乃至第
１１図はそれぞれ本発明が適用されるTFTの各
種構造を例示する断面図である。図中、２５はガ
ラス等の絶縁膜基板２６はゲート電極、２７はゲ
ート絶縁膜、２８はCdSe，CdSTe等の半導体
膜、２９はソース電極、３０はドレイン電極を示
す。 A case where the channel structure of the present invention is applied to a typical TFT structure is shown in FIGS. 6a and 6b. FIG. 6b is a sectional view taken along the line AA' in FIG. 6a. FIGS. 7 to 11 are cross-sectional views illustrating various structures of TFTs to which the present invention is applied. In the figure, 25 indicates an insulating film substrate 26 made of glass or the like, 27 indicates a gate insulating film, 28 indicates a semiconductor film such as CdSe or CdSTe, 29 indicates a source electrode, and 30 indicates a drain electrode.

上記構造を有する薄膜トランジスタを液晶表示
装置に実装することにより、駆動周波数が下が
り、ドレイン電流が小さくなるため駆動回路の消
費電力が低減される。薄膜トランジスタの実装は
第３図に説明した如く、ガラス基板上に本発明の
TFT及び容量を形成し、液晶エレメントの一方
の電極を配列し、このガラス基板と対向して他方
の電極を形成した対向基板を配置することにより
行なわれる。電極構成はＸ―Ｙマトリツクス構
造、日の字型、田の字型等のセグメント構造、そ
の他のパターン構造が採用される。 By mounting a thin film transistor having the above structure in a liquid crystal display device, the driving frequency is lowered and the drain current is reduced, so that the power consumption of the driving circuit is reduced. As explained in FIG. 3, the thin film transistor is mounted on a glass substrate.
This is carried out by forming a TFT and a capacitor, arranging one electrode of a liquid crystal element, and arranging a counter substrate on which the other electrode is formed to face this glass substrate. As for the electrode structure, an XY matrix structure, a segment structure such as a Japanese character shape or a Japanese character shape, and other pattern structures are adopted.

以上詳説した如く、本発明のTFTはドレイン
電流（ID）を小さくすることができ、良好な素子
特性の得られる非常に技術的卓越性の顕著な素子
構造である。 As explained in detail above, the TFT of the present invention is a highly technologically superior device structure that can reduce the drain current (I D ) and provide good device characteristics.

また、半導体膜自体をパターニングしてチヤネ
ルを形成することにより、適用可能な電圧範囲が
従来に比べて大幅に広がるため、本発明は駆動電
圧幅の広い液晶セルのTFTとして優れており、
信頼性の高いものである。 In addition, by patterning the semiconductor film itself to form a channel, the applicable voltage range is significantly expanded compared to conventional methods, so the present invention is excellent as a TFT for liquid crystal cells with a wide driving voltage range.
It is highly reliable.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のTFTを用いたマトリツクス型
液晶表示装置の回路図、第２図は第１図の回路を
説明するタイムチヤート、第３図はTFTを用い
たマトリツクス液晶表示装置の断面図、第４図は
第２図を改良した駆動波形を説明するタイムチヤ
ート、第５図ａは従来のTFT素子のチヤネル部
の電極形状、第５図ｂ，ｃ，ｄは本発明のTFT
素子のチヤネル部の電極形状を説明する説明図、
第６図ａ，ｂは本発明のチヤネル部の電極構造を
有するTFT素子の平面図及びその断面図、第７
図乃至第１１図は、本発明が適用されるTFTの
断面図である。 ２５…絶縁膜基板、２６…ゲート電極、２７…
ゲート絶縁膜、２８…半導体膜、２９…ソース電
極、３０…ドレイン電極。 Fig. 1 is a circuit diagram of a matrix type liquid crystal display device using a conventional TFT, Fig. 2 is a time chart explaining the circuit of Fig. 1, and Fig. 3 is a cross-sectional view of a matrix liquid crystal display device using a TFT. Fig. 4 is a time chart explaining the drive waveform improved from Fig. 2, Fig. 5 a is the electrode shape of the channel part of the conventional TFT element, and Fig. 5 b, c, and d are the TFT of the present invention.
An explanatory diagram illustrating the shape of the electrode in the channel part of the element,
Figures 6a and 6b are a plan view and a cross-sectional view of a TFT element having a channel electrode structure according to the present invention;
1 to 11 are cross-sectional views of a TFT to which the present invention is applied. 25... Insulating film substrate, 26... Gate electrode, 27...
Gate insulating film, 28... semiconductor film, 29... source electrode, 30... drain electrode.

Claims (1)

【特許請求の範囲】 １ 絶縁性基板と、 該絶縁性基板上に形成されたゲート電極と、 該ゲート電極を覆うゲート絶縁膜と、 該ゲート絶縁膜上に形成され、ゲート絶縁膜の
一端から他端へ向けて延在し、ほぼ一定の幅で屈
曲成形された半導体膜と、 該半導体膜の一端と電気的に接続され、半導体
膜の幅とほぼ等しい幅を有するドレイン電極と、 前記半導体膜の他端と電気的に接続され、半導
体膜の幅とほぼ等しい幅を有するソース電極と、 を備えた薄膜トランジスタと、 前記絶縁性基板上に形成され、前記ドレイン電
極と電気的に接続された表示画素電極と、 前記絶縁性基板とで液晶層を挾持する対向基板
と、 該対向基板上に形成された対向電極と、 を具備してなることを特徴とする液晶表示装置。[Scope of Claims] 1. an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film covering the gate electrode, and a gate insulating film formed on the gate insulating film from one end of the gate insulating film. a semiconductor film extending toward the other end and bent to have a substantially constant width; a drain electrode electrically connected to one end of the semiconductor film and having a width substantially equal to the width of the semiconductor film; a source electrode electrically connected to the other end of the film and having a width approximately equal to the width of the semiconductor film; a thin film transistor formed on the insulating substrate and electrically connected to the drain electrode; A liquid crystal display device comprising: a display pixel electrode; a counter substrate sandwiching a liquid crystal layer between the insulating substrates; and a counter electrode formed on the counter substrate.
JP10191279A 1979-07-31 1979-08-09 Structure of membrane transistor Granted JPS5626468A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP10191279A JPS5626468A (en) 1979-08-09 1979-08-09 Structure of membrane transistor
DE3028718A DE3028718C2 (en) 1979-07-31 1980-07-29 Thin film transistor in connection with a display device
US06/173,818 US4404578A (en) 1979-07-31 1980-07-30 Structure of thin film transistors
GB8025044A GB2056770B (en) 1979-07-31 1980-07-31 Thin film transistors
GB08316195A GB2127216B (en) 1979-07-31 1983-06-14 Improved s of thin film transistors and manufacture method thereof
GB08316196A GB2126779B (en) 1979-07-31 1983-06-14 Thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10191279A JPS5626468A (en) 1979-08-09 1979-08-09 Structure of membrane transistor

Publications (2)

Publication Number Publication Date
JPS5626468A JPS5626468A (en) 1981-03-14
JPH0128386B2 true JPH0128386B2 (en) 1989-06-02

Family

ID=14313113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10191279A Granted JPS5626468A (en) 1979-07-31 1979-08-09 Structure of membrane transistor

Country Status (1)

Country Link
JP (1) JPS5626468A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608070A (en) * 1983-06-28 1985-01-16 株式会社アイジ−技術研究所 Production unit for composite board
JPH0828508B2 (en) * 1986-10-31 1996-03-21 松下電器産業株式会社 Thin film transistor and manufacturing method thereof
CN101009322B (en) * 2001-11-09 2012-06-27 株式会社半导体能源研究所 Light-emitting device
JP4149168B2 (en) 2001-11-09 2008-09-10 株式会社半導体エネルギー研究所 Light emitting device
CN101673508B (en) 2002-01-18 2013-01-09 株式会社半导体能源研究所 Light-emitting device
US7592980B2 (en) 2002-06-05 2009-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102709478B (en) 2003-03-26 2016-08-17 株式会社半导体能源研究所 Light-emitting device
US7221095B2 (en) * 2003-06-16 2007-05-22 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method for fabricating light emitting device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5032186A (en) * 1973-07-17 1975-03-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5032186A (en) * 1973-07-17 1975-03-28

Also Published As

Publication number Publication date
JPS5626468A (en) 1981-03-14

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